The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ieee1394/ieee1394reg.h

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    1 /*      $NetBSD: ieee1394reg.h,v 1.17 2003/08/04 07:00:19 mrg Exp $     */
    2 
    3 /*-
    4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by 
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *        This product includes software developed by the NetBSD
   21  *        Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 #ifndef _DEV_IEEE1394_IEEE1394REG_H_
   40 #define _DEV_IEEE1394_IEEE1394REG_H_
   41 
   42 #include <dev/std/ieee1212reg.h>
   43 
   44 /* Transaction Codes (Table 6-9)
   45  */
   46 #define IEEE1394_TCODE_WRITE_REQUEST_QUADLET    0
   47 #define IEEE1394_TCODE_WRITE_REQUEST_DATABLOCK  1
   48 #define IEEE1394_TCODE_WRITE_RESPONSE           2
   49 #define IEEE1394_TCODE_RESERVED_3               3
   50 #define IEEE1394_TCODE_READ_REQUEST_QUADLET     4
   51 #define IEEE1394_TCODE_READ_REQUEST_DATABLOCK   5
   52 #define IEEE1394_TCODE_READ_RESPONSE_QUADLET    6
   53 #define IEEE1394_TCODE_READ_RESPONSE_DATABLOCK  7
   54 #define IEEE1394_TCODE_CYCLE_START              0x8
   55 #define IEEE1394_TCODE_LOCK_REQUEST             9
   56 #define IEEE1394_TCODE_ISOCHRONOUS_DATA_BLOCK   10
   57 #define IEEE1394_TCODE_LOCK_RESPONSE            11
   58 #define IEEE1394_TCODE_RESERVED_12              12
   59 #define IEEE1394_TCODE_RESERVED_13              13
   60 #define IEEE1394_TCODE_RESERVED_14              14
   61 #define IEEE1394_TCODE_RESERVED_15              15
   62 
   63 /* Extended transaction codes (Table 6-10)
   64  */
   65 #define IEEE1394_XTCODE_RESERVED_0              P1212_LOCK_RESERVED_0
   66 #define IEEE1394_XTCODE_MASK_SWAP               P1212_LOCK_MASK_SWAP
   67 #define IEEE1394_XTCODE_COMPARE_SWAP            P1212_LOCK_COMPARE_SWAP
   68 #define IEEE1394_XTCODE_FETCH_ADD               P1212_LOCK_FETCH_ADD
   69 #define IEEE1394_XTCODE_LITTLE_ADD              P1212_LOCK_LITTLE_ADD
   70 #define IEEE1394_XTCODE_BOUNDED_ADD             P1212_LOCK_BOUNDED_ADD
   71 #define IEEE1394_XTCODE_WRAP_ADD                P1212_LOCK_WRAP_ADD
   72 #define IEEE1394_XTCODE_VENDOR_DEPENDENT        P1212_LOCK_VENDOR_DEPENDENT
   73 /* 0x0008 .. 0xFFFF are reserved.
   74  */
   75 
   76 /* Response codes (Table 6-11)
   77  */
   78 #define IEEE1394_RCODE_RESP_COMPLETE            0
   79 #define IEEE1394_RCODE_RESERVED_1               1
   80 #define IEEE1394_RCODE_RESERVED_2               2
   81 #define IEEE1394_RCODE_RESERVED_3               3
   82 #define IEEE1394_RCODE_RESP_CONFLICT_ERROR      4
   83 #define IEEE1394_RCODE_RESP_DATA_ERROR          5
   84 #define IEEE1394_RCODE_RESP_TYPE_ERROR          6
   85 #define IEEE1394_RCODE_RESP_ADDRESS_ERROR       7
   86 #define IEEE1394_RCODE_RESERVED_8               8
   87 #define IEEE1394_RCODE_RESERVED_9               9
   88 #define IEEE1394_RCODE_RESERVED_10              10
   89 #define IEEE1394_RCODE_RESERVED_11              11
   90 #define IEEE1394_RCODE_RESERVED_12              12
   91 #define IEEE1394_RCODE_RESERVED_13              13
   92 #define IEEE1394_RCODE_RESERVED_14              14
   93 #define IEEE1394_RCODE_RESERVED_15              15
   94 
   95 #define IEEE1394_TAG_UNFORMATTED                0
   96 #define IEEE1394_TAG_RESERVED_1                 1
   97 #define IEEE1394_TAG_RESERVED_2                 2
   98 #define IEEE1394_TAG_RESERVED_3                 3
   99 
  100 #define IEEE1394_ACK_RESERVED_0                 0
  101 #define IEEE1394_ACK_COMPLETE                   1
  102 #define IEEE1394_ACK_PENDING                    2
  103 #define IEEE1394_ACK_RESERVED_3                 3
  104 #define IEEE1394_ACK_BUSY_X                     4
  105 #define IEEE1394_ACK_BUSY_A                     5
  106 #define IEEE1394_ACK_BUSY_B                     6
  107 #define IEEE1394_ACK_RESERVED_7                 7
  108 #define IEEE1394_ACK_RESERVED_8                 8
  109 #define IEEE1394_ACK_RESERVED_9                 9
  110 #define IEEE1394_ACK_RESERVED_10                10
  111 #define IEEE1394_ACK_RESERVED_11                11
  112 #define IEEE1394_ACK_RESERVED_12                12
  113 #define IEEE1394_ACK_DATA_ERROR                 13
  114 #define IEEE1394_ACK_TYPE_ERROR                 14
  115 #define IEEE1394_ACK_RESERVED_15                15
  116 
  117 /* Defined IEEE 1394 speeds.
  118  */
  119 #define IEEE1394_SPD_S100       0       /* 1394-1995 */
  120 #define IEEE1394_SPD_S200       1       /* 1394-1995 */
  121 #define IEEE1394_SPD_S400       2       /* 1394-1995 */
  122 #define IEEE1394_SPD_S800       3       /* 1394b */
  123 #define IEEE1394_SPD_S1600      4       /* 1394b */
  124 #define IEEE1394_SPD_S3200      5       /* 1394b */
  125 #define IEEE1394_SPD_MAX        6
  126 
  127 #define IEEE1394_SPD_STRINGS    "100Mb/s", "200Mb/s", "400Mb/s", "800Mb/s", \
  128                 "1.6Gb/s", "3.2Gb/s"
  129 
  130 #if 0
  131 struct ieee1394_async_nodata {
  132         u_int32_t an_header_crc;
  133 } __attribute((__packed__));
  134 #endif
  135 
  136 #define IEEE1394_BCAST_PHY_ID   0x3f
  137 #define IEEE1394_ISOCH_MASK     0x3f
  138 
  139 /*
  140  * Transaction code
  141  */
  142 #define IEEE1394_TCODE_WRITE_REQ_QUAD   0x0
  143 #define IEEE1394_TCODE_WRITE_REQ_BLOCK  0x1
  144 #define IEEE1394_TCODE_WRITE_RESP       0x2
  145 #define IEEE1394_TCODE_READ_REQ_QUAD    0x4
  146 #define IEEE1394_TCODE_READ_REQ_BLOCK   0x5
  147 #define IEEE1394_TCODE_READ_RESP_QUAD   0x6
  148 #define IEEE1394_TCODE_READ_RESP_BLOCK  0x7
  149 #define IEEE1394_TCODE_CYCLE_START      0x8
  150 #define IEEE1394_TCODE_LOCK_REQ         0x9
  151 #define IEEE1394_TCODE_STREAM_DATA      0xa
  152 #define IEEE1394_TCODE_LOCK_RESP        0xb
  153 
  154 /*
  155  * Response code
  156  */
  157 #define IEEE1394_RCODE_COMPLETE         0x0
  158 #define IEEE1394_RCODE_CONFLICT_ERROR   0x4
  159 #define IEEE1394_RCODE_DATA_ERROR       0x5
  160 #define IEEE1394_RCODE_TYPE_ERROR       0x6
  161 #define IEEE1394_RCODE_ADDRESS_ERROR    0x7
  162 
  163 /*
  164  * Signature
  165  */
  166 #define IEEE1394_SIGNATURE              0x31333934
  167 
  168 /*
  169  * Tag value
  170  */
  171 #define IEEE1394_TAG_CIP                0x1
  172 #define IEEE1394_TAG_GASP               0x3
  173 
  174 /*
  175  * Control and Status Registers (IEEE1212 & IEEE1394)
  176  */
  177 #define CSR_BASE_HI                     0x0000ffff
  178 #define CSR_BASE_LO                     0xf0000000
  179 #define CSR_BASE                        0x0000fffff0000000LL
  180 
  181 #define CSR_STATE_CLEAR                 0x0000
  182 #define CSR_STATE_SET                   0x0004
  183 #define CSR_NODE_IDS                    0x0008
  184 #define CSR_RESET_START                 0x000c
  185 #define CSR_INDIRECT_ADDRESS            0x0010
  186 #define CSR_INDIRECT_DATA               0x0014
  187 #define CSR_SPLIT_TIMEOUT_HI            0x0018
  188 #define CSR_SPLIT_TIMEOUT_LO            0x001c
  189 #define CSR_ARGUMENT_HI                 0x0020
  190 #define CSR_ARGUMENT_LO                 0x0024
  191 #define CSR_TEST_START                  0x0028
  192 #define CSR_TEST_STATUS                 0x002c
  193 #define CSR_INTERRUPT_TARGET            0x0050
  194 #define CSR_INTERRUPT_MASK              0x0054
  195 #define CSR_CLOCK_VALUE                 0x0058
  196 #define CSR_CLOCK_PERIOD                0x005c
  197 #define CSR_CLOCK_STROBE_ARRIVED        0x0060
  198 #define CSR_CLOCK_INFO                  0x0064
  199 #define CSR_MESSAGE_REQUEST             0x0080
  200 #define CSR_MESSAGE_RESPONSE            0x00c0
  201 
  202 #define CSR_SB_CYCLE_TIME               0x0200
  203 #define CSR_SB_BUS_TIME                 0x0204
  204 #define CSR_SB_POWER_FAIL_IMMINENT      0x0208
  205 #define CSR_SB_POWER_SOURCE             0x020c
  206 #define CSR_SB_BUSY_TIMEOUT             0x0210
  207 #define CSR_SB_PRIORITY_BUDGET_HI       0x0214
  208 #define CSR_SB_PRIORITY_BUDGET_LO       0x0218
  209 #define CSR_SB_BUS_MANAGER_ID           0x021c
  210 #define CSR_SB_BANDWIDTH_AVAILABLE      0x0220
  211 #define CSR_SB_CHANNEL_AVAILABLE_HI     0x0224
  212 #define CSR_SB_CHANNEL_AVAILABLE_LO     0x0228
  213 #define CSR_SB_MAINT_CONTROL            0x022c
  214 #define CSR_SB_MAINT_UTILITY            0x0230
  215 #define CSR_SB_BROADCAST_CHANNEL        0x0234
  216 
  217 #define CSR_CONFIG_ROM                  0x0400
  218 
  219 #define CSR_SB_OUTPUT_MASTER_PLUG       0x0900
  220 #define CSR_SB_OUTPUT_PLUG              0x0904
  221 #define CSR_SB_INPUT_MASTER_PLUG        0x0980
  222 #define CSR_SB_INPUT_PLUG               0x0984
  223 #define CSR_SB_FCP_COMMAND_FRAME        0x0b00
  224 #define CSR_SB_FCP_RESPONSE_FRAME       0x0d00
  225 #define CSR_SB_TOPOLOGY_MAP             0x1000
  226 #define CSR_SB_END                      0x1400
  227 
  228 #define IEEE1394_MAX_REC(i)     ((0x1 << (i + 1)))
  229 #define IEEE1394_BUSINFO_LEN    3
  230 
  231 #define IEEE1394_MAX_ASYNCH_FOR_SPEED(i) (IEEE1394_MAX_REC(8+i))
  232 #define IEEE1394_GET_MAX_REC(i) ((i & 0x0000f000) >> 12)
  233 #define IEEE1394_GET_LINK_SPD(i) (i & 0x00000007)
  234 
  235 #define IEEE1394_CREATE_ADDR_HIGH(x) (htonl((x & 0xffffffff00000000LL) >> 32))
  236 #define IEEE1394_CREATE_ADDR_LOW(x)  (htonl((x & 0x00000000ffffffffLL)))
  237 
  238 
  239 /*
  240  * Allocated CSR space initiator drivers have reserved. Add allocations here to
  241  * avoid overlaps. Use the initial 64k space for register space and alloc large
  242  * blocks within the initial 4G for virtualizing data space (ala SBP).
  243  */
  244 
  245 /*
  246  * 0xfffff0010000 - if_fw fifo  XXX - Move this below the 4G mark 
  247  * 0x0000f0010004 - 0x0000f0020000 - SBP2 addr range (64k in 4 byte chunks)
  248  * 0x0000f0020000 - 0x0000f101ffff - SBP2 data address range (16M in 512 byte
  249  *                                                            chunks)
  250  *
  251  */
  252 
  253 /* if_fw fifo for receiving packets. */
  254 
  255 #define FW_FIFO_HI      0xffff
  256 #define FW_FIFO_LO      0xf0010000
  257 #define FW_FIFO         0x0000fffff0010000LL
  258 
  259 #define SBP_ADDR_BEG_HI 0x0000
  260 #define SBP_ADDR_BEG_LO 0xf0010004
  261 #define SBP_ADDR_BEG    0x00000000f0010004LL
  262 
  263 #define SBP_ADDR_MAX_HI 0x0000
  264 #define SBP_ADDR_MAX_LO 0xf0020004
  265 #define SBP_ADDR_MAX    0x00000000f0020004LL
  266 
  267 #define SBP_ADDR_SIZE   (SBP_ADDR_MAX - SBP_ADDR_BEG)
  268 #define SBP_ADDR_BLOCK_SIZE     4
  269 
  270 #define SBP_DATA_BEG_HI 0x0000
  271 #define SBP_DATA_BEG_LO 0xf0020000
  272 #define SBP_DATA_BEG    0x00000000f0020000LL
  273 
  274 #define SBP_DATA_MAX_HI 0x0000
  275 #define SBP_DATA_MAX_LO 0xf101ffff
  276 #define SBP_DATA_MAX    0x00000000f1020000LL
  277 
  278 #define SBP_DATA_SIZE   (SBP_DATA_MAX - SBP_DATA_BEG)
  279 #define SBP_DATA_BLOCK_SIZE     512
  280 
  281 
  282 /* CIP format (isochronous transaction, tag 1) */
  283 #define IEEE1394_CIP_SID_MASK           0x3f000000
  284 #define IEEE1394_CIP_SID_OFFS           24
  285 #define IEEE1394_CIP_DBS_MASK           0x00ff0000
  286 #define IEEE1394_CIP_DBS_OFFS           16
  287 #define IEEE1394_CIP_FN_MASK            0x0000c000
  288 #define IEEE1394_CIP_FN_OFFS            14
  289 #define IEEE1394_CIP_QPC_MASK           0x00003800
  290 #define IEEE1394_CIP_QPC_OFFS           11
  291 #define IEEE1394_CIP_SPH_MASK           0x00000400
  292 #define IEEE1394_CIP_SPH_OFFS           10
  293 #define IEEE1394_CIP_DBC_MASK           0x000000ff
  294 #define IEEE1394_CIP_DBC_OFFS           0
  295 #define IEEE1394_CIP_FMT_MASK           0x3f000000
  296 #define IEEE1394_CIP_FMT_OFFS           24
  297 #define IEEE1394_CIP_FDF_MASK           0x00ffffff
  298 
  299 #define IEEE1394_CIP_FDF_SYT_MASK       0x0000ffff
  300 #define IEEE1394_CIP_FDF_SYT_OFFS       0
  301 
  302 #define IEEE1394_CIP_FDF_DV_FR          0x00800000
  303 #define IEEE1394_CIP_FDF_DV_FR_60       0x00800000
  304 #define IEEE1394_CIP_FDF_DV_FR_50       0x00000000
  305 #define IEEE1394_CIP_FDF_DV_STYPE       0x007c0000
  306 
  307 #define IEEE1394_CIP_FMT_DV             0
  308 #define IEEE1394_CIP_FMT_MPEG2TS        0x20000000
  309 #define IEEE1394_CIP_FMT_AUDIO          0x10000000
  310 
  311 #define IEEE1394_CIP_SET(reg, val)                                      \
  312         (IEEE1394_CIP_##reg##_MASK & ((val) << IEEE1394_CIP_##reg##_OFFS))
  313 
  314 #endif  /* _DEV_IEEE1394_IEEE1394REG_H_ */

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