Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ieee488/upd7210.h
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1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 * Locating an actual µPD7210 data book has proven quite impossible for me. 29 * There are a fair number of newer chips which are supersets of the µPD7210 30 * but they are particular eager to comprehensively mark what the extensions 31 * are and what is in the base set. Some even give the registers and their 32 * bits new names. 33 * 34 * The following information is based on a description of the µPD7210 found 35 * in an old manual for a VME board which used the chip. 36 */ 37 38 #ifndef _DEV_IEEE488_UPD7210_H_ 39 #define _DEV_IEEE488_UPD7210_H_ 40 #ifdef _KERNEL 41 42 struct upd7210; 43 struct ibfoo; 44 45 /* upd7210 interface definitions for HW drivers */ 46 47 typedef int upd7210_irq_t(struct upd7210 *, int); 48 49 struct upd7210 { 50 bus_space_handle_t reg_handle[8]; 51 bus_space_tag_t reg_tag[8]; 52 u_int reg_offset[8]; 53 int dmachan; 54 55 /* private stuff */ 56 struct mtx mutex; 57 uint8_t rreg[8]; 58 uint8_t wreg[8 + 8]; 59 60 upd7210_irq_t *irq; 61 62 int busy; 63 u_char *buf; 64 size_t bufsize; 65 u_int buf_wp; 66 u_int buf_rp; 67 struct cdev *cdev; 68 69 struct ibfoo *ibfoo; 70 }; 71 72 #ifdef UPD7210_HW_DRIVER 73 void upd7210intr(void *); 74 void upd7210attach(struct upd7210 *); 75 #endif 76 77 #ifdef UPD7210_SW_DRIVER 78 79 /* upd7210 hardware definitions. */ 80 81 /* Write registers */ 82 enum upd7210_wreg { 83 CDOR = 0, /* Command/Data Out Register */ 84 IMR1 = 1, /* Interrupt Mask Register 1 */ 85 IMR2 = 2, /* Interrupt Mask Register 2 */ 86 SPMR = 3, /* Serial Poll Mode Register */ 87 ADMR = 4, /* ADdress Mode Register */ 88 AUXMR = 5, /* AUXilliary Mode Register */ 89 ICR = 5, /* Internal Counter Register */ 90 PPR = 5, /* Parallel Poll Register */ 91 AUXRA = 5, /* AUXilliary Register A */ 92 AUXRB = 5, /* AUXilliary Register B */ 93 AUXRE = 5, /* AUXilliary Register E */ 94 ADR = 6, /* ADdress Register */ 95 EOSR = 7, /* End-Of-String Register */ 96 }; 97 98 /* Read registers */ 99 enum upd7210_rreg { 100 DIR = 0, /* Data In Register */ 101 ISR1 = 1, /* Interrupt Status Register 1 */ 102 ISR2 = 2, /* Interrupt Status Register 2 */ 103 SPSR = 3, /* Serial Poll Status Register */ 104 ADSR = 4, /* ADdress Status Register */ 105 CPTR = 5, /* Command Pass Though Register */ 106 ADR0 = 6, /* ADdress Register 0 */ 107 ADR1 = 7, /* ADdress Register 1 */ 108 }; 109 110 /* Bits for ISR1 and IMR1 */ 111 #define IXR1_DI (1 << 0) /* Data In */ 112 #define IXR1_DO (1 << 1) /* Data Out */ 113 #define IXR1_ERR (1 << 2) /* Error */ 114 #define IXR1_DEC (1 << 3) /* Device Clear */ 115 #define IXR1_ENDRX (1 << 4) /* End Received */ 116 #define IXR1_DET (1 << 5) /* Device Execute Trigger */ 117 #define IXR1_APT (1 << 6) /* Address Pass-Through */ 118 #define IXR1_CPT (1 << 7) /* Command Pass-Through */ 119 120 /* Bits for ISR2 and IMR2 */ 121 #define IXR2_ADSC (1 << 0) /* Addressed Status Change */ 122 #define IXR2_REMC (1 << 1) /* Remote Change */ 123 #define IXR2_LOKC (1 << 2) /* Lockout Change */ 124 #define IXR2_CO (1 << 3) /* Command Out */ 125 #define ISR2_REM (1 << 4) /* Remove */ 126 #define IMR2_DMAI (1 << 4) /* DMA In Enable */ 127 #define ISR2_LOK (1 << 5) /* Lockout */ 128 #define IMR2_DMAO (1 << 5) /* DMA Out Enable */ 129 #define IXR2_SRQI (1 << 6) /* Service Request Input */ 130 #define ISR2_INT (1 << 7) /* Interrupt */ 131 132 #define SPSR_PEND (1 << 6) /* Pending */ 133 #define SPMR_RSV (1 << 6) /* Request SerVice */ 134 135 #define ADSR_MJMN (1 << 0) /* MaJor MiNor */ 136 #define ADSR_TA (1 << 1) /* Talker Active */ 137 #define ADSR_LA (1 << 2) /* Listener Active */ 138 #define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */ 139 #define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */ 140 #define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */ 141 #define ADSR_ATN (1 << 6) /* Attention */ 142 #define ADSR_CIC (1 << 7) /* Controller In Charge */ 143 144 #define ADMR_ADM0 (1 << 0) /* Address Mode 0 */ 145 #define ADMR_ADM1 (1 << 1) /* Address Mode 1 */ 146 #define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */ 147 #define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */ 148 #define ADMR_LON (1 << 6) /* Listen Only */ 149 #define ADMR_TON (1 << 7) /* Talk Only */ 150 151 /* Constant part of overloaded write registers */ 152 #define C_ICR 0x20 153 #define C_PPR 0x60 154 #define C_AUXA 0x80 155 #define C_AUXB 0xa0 156 #define C_AUXE 0xc0 157 158 #define AUXMR_PON 0x00 /* Immediate Execute pon */ 159 #define AUXMR_CPP 0x01 /* Clear Parallel Poll */ 160 #define AUXMR_CRST 0x02 /* Chip Reset */ 161 #define AUXMR_RFD 0x03 /* Finish Handshake */ 162 #define AUXMR_TRIG 0x04 /* Trigger */ 163 #define AUXMR_RTL 0x05 /* Return to local */ 164 #define AUXMR_SEOI 0x06 /* Send EOI */ 165 #define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */ 166 /* 0x08 undefined/unknown */ 167 #define AUXMR_SPP 0x09 /* Set Parallel Poll */ 168 /* 0x0a undefined/unknown */ 169 /* 0x0b undefined/unknown */ 170 /* 0x0c undefined/unknown */ 171 /* 0x0d undefined/unknown */ 172 /* 0x0e undefined/unknown */ 173 #define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */ 174 #define AUXMR_GTS 0x10 /* Go to Standby */ 175 #define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */ 176 #define AUXMR_TCS 0x12 /* Take Control Synchronously */ 177 #define AUXMR_LISTEN 0x13 /* Listen */ 178 #define AUXMR_DSC 0x14 /* Disable System Control */ 179 /* 0x15 undefined/unknown */ 180 #define AUXMR_SIFC 0x16 /* Set IFC */ 181 #define AUXMR_CREN 0x17 /* Clear REN */ 182 /* 0x18 undefined/unknown */ 183 /* 0x19 undefined/unknown */ 184 #define AUXMR_TCSE 0x1a /* Take Control Sync on End */ 185 #define AUXMR_LCM 0x1b /* Listen Continuously Mode */ 186 #define AUXMR_LUNL 0x1c /* Local Unlisten */ 187 #define AUXMR_EPP 0x1d /* Execute Parallel Poll */ 188 #define AUXMR_CIFC 0x1e /* Clear IFC */ 189 #define AUXMR_SREN 0x1f /* Set REN */ 190 191 #define PPR_U (1 << 4) /* Unconfigure */ 192 #define PPR_S (1 << 3) /* Status Polarity */ 193 194 #define AUXA_HLDA (1 << 0) /* Holdoff on All */ 195 #define AUXA_HLDE (1 << 1) /* Holdoff on END */ 196 #define AUXA_REOS (1 << 2) /* End on EOS received */ 197 #define AUXA_XEOS (1 << 3) /* Transmit END with EOS */ 198 #define AUXA_BIN (1 << 4) /* Binary */ 199 200 #define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */ 201 #define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */ 202 #define AUXB_TRI (1 << 2) /* Three-State Timing */ 203 #define AUXB_INV (1 << 3) /* Invert */ 204 #define AUXB_ISS (1 << 4) /* Individual Status Select */ 205 206 #define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */ 207 #define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */ 208 209 #define ADR0_DL0 (1 << 5) /* Disable Listener 0 */ 210 #define ADR0_DT0 (1 << 6) /* Disable Talker 0 */ 211 212 #define ADR_DL (1 << 5) /* Disable Listener */ 213 #define ADR_DT (1 << 6) /* Disable Talker */ 214 #define ADR_ARS (1 << 7) /* Address Register Select */ 215 216 #define ADR1_DL1 (1 << 5) /* Disable Listener 1 */ 217 #define ADR1_DT1 (1 << 6) /* Disable Talker 1 */ 218 #define ADR1_EOI (1 << 7) /* End or Identify */ 219 220 /* Stuff from software drivers */ 221 extern struct cdevsw gpib_l_cdevsw; 222 extern struct cdevsw gpib_ib_cdevsw; 223 224 /* Stuff from upd7210.c */ 225 void upd7210_print_isr(u_int isr1, u_int isr2); 226 u_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg); 227 void upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val); 228 int upd7210_take_ctrl_async(struct upd7210 *u); 229 int upd7210_goto_standby(struct upd7210 *u); 230 231 #endif /* UPD7210_SW_DRIVER */ 232 233 #endif /* _KERNEL */ 234 #endif /* _DEV_IEEE488_UPD7210_H_ */
Cache object: 3298a024246e574cd1862971234208f4
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