fxr.watson.org: sys/dev/igc/if

FreeBSD/Linux Kernel Cross Reference
sys/dev/igc/if_igc.c

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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "if_igc.h" 34 #include <sys/sbuf.h> 35 #include <machine/_inttypes.h> 36 37 #ifdef RSS 38 #include <net/rss_config.h> 39 #include <netinet/in_rss.h> 40 #endif 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last entry must be all 0s 47 * 48 * { Vendor ID, Device ID, String } 49 *********************************************************************/ 50 51 static pci_vendor_info_t igc_vendor_info_array[] = 52 { 53 /* Intel(R) PRO/1000 Network Connection - igc */ 54 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 55 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 56 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 57 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 58 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 59 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 60 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 61 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 62 PVID(0x8086, IGC_DEV_ID_I226_LMVP, "Intel(R) Ethernet Controller I226-LMvP"), 63 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 64 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 65 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 66 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 67 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 68 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 69 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 70 /* required last entry */ 71 PVID_END 72 }; 73 74 /********************************************************************* 75 * Function prototypes 76 *********************************************************************/ 77 static void *igc_register(device_t dev); 78 static int igc_if_attach_pre(if_ctx_t ctx); 79 static int igc_if_attach_post(if_ctx_t ctx); 80 static int igc_if_detach(if_ctx_t ctx); 81 static int igc_if_shutdown(if_ctx_t ctx); 82 static int igc_if_suspend(if_ctx_t ctx); 83 static int igc_if_resume(if_ctx_t ctx); 84 85 static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 86 static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 87 static void igc_if_queues_free(if_ctx_t ctx); 88 89 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 90 static void igc_if_init(if_ctx_t ctx); 91 static void igc_if_stop(if_ctx_t ctx); 92 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 93 static int igc_if_media_change(if_ctx_t ctx); 94 static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 95 static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 96 static void igc_if_watchdog_reset(if_ctx_t ctx); 97 static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 98 99 static void igc_identify_hardware(if_ctx_t ctx); 100 static int igc_allocate_pci_resources(if_ctx_t ctx); 101 static void igc_free_pci_resources(if_ctx_t ctx); 102 static void igc_reset(if_ctx_t ctx); 103 static int igc_setup_interface(if_ctx_t ctx); 104 static int igc_setup_msix(if_ctx_t ctx); 105 106 static void igc_initialize_transmit_unit(if_ctx_t ctx); 107 static void igc_initialize_receive_unit(if_ctx_t ctx); 108 109 static void igc_if_intr_enable(if_ctx_t ctx); 110 static void igc_if_intr_disable(if_ctx_t ctx); 111 static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 112 static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 113 static void igc_if_multi_set(if_ctx_t ctx); 114 static void igc_if_update_admin_status(if_ctx_t ctx); 115 static void igc_if_debug(if_ctx_t ctx); 116 static void igc_update_stats_counters(struct igc_adapter *); 117 static void igc_add_hw_stats(struct igc_adapter *adapter); 118 static int igc_if_set_promisc(if_ctx_t ctx, int flags); 119 static void igc_setup_vlan_hw_support(if_ctx_t ctx); 120 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 121 static void igc_print_nvm_info(struct igc_adapter *); 122 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 123 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 124 static void igc_print_debug_info(struct igc_adapter *); 125 static int igc_is_valid_ether_addr(u8 *); 126 static int igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 127 static void igc_add_int_delay_sysctl(struct igc_adapter *, const char *, 128 const char *, struct igc_int_delay_info *, int, int); 129 /* Management and WOL Support */ 130 static void igc_get_hw_control(struct igc_adapter *); 131 static void igc_release_hw_control(struct igc_adapter *); 132 static void igc_get_wakeup(if_ctx_t ctx); 133 static void igc_enable_wakeup(if_ctx_t ctx); 134 135 int igc_intr(void *arg); 136 137 /* MSI-X handlers */ 138 static int igc_if_msix_intr_assign(if_ctx_t, int); 139 static int igc_msix_link(void *); 140 static void igc_handle_link(void *context); 141 142 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 143 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 144 145 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 146 147 static void igc_configure_queues(struct igc_adapter *adapter); 148 149 150 /********************************************************************* 151 * FreeBSD Device Interface Entry Points 152 *********************************************************************/ 153 static device_method_t igc_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_register, igc_register), 156 DEVMETHOD(device_probe, iflib_device_probe), 157 DEVMETHOD(device_attach, iflib_device_attach), 158 DEVMETHOD(device_detach, iflib_device_detach), 159 DEVMETHOD(device_shutdown, iflib_device_shutdown), 160 DEVMETHOD(device_suspend, iflib_device_suspend), 161 DEVMETHOD(device_resume, iflib_device_resume), 162 DEVMETHOD_END 163 }; 164 165 static driver_t igc_driver = { 166 "igc", igc_methods, sizeof(struct igc_adapter), 167 }; 168 169 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 170 171 MODULE_DEPEND(igc, pci, 1, 1, 1); 172 MODULE_DEPEND(igc, ether, 1, 1, 1); 173 MODULE_DEPEND(igc, iflib, 1, 1, 1); 174 175 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 176 177 static device_method_t igc_if_methods[] = { 178 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 179 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 180 DEVMETHOD(ifdi_detach, igc_if_detach), 181 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 182 DEVMETHOD(ifdi_suspend, igc_if_suspend), 183 DEVMETHOD(ifdi_resume, igc_if_resume), 184 DEVMETHOD(ifdi_init, igc_if_init), 185 DEVMETHOD(ifdi_stop, igc_if_stop), 186 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 187 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 188 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 189 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 190 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 191 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 192 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 193 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 194 DEVMETHOD(ifdi_media_status, igc_if_media_status), 195 DEVMETHOD(ifdi_media_change, igc_if_media_change), 196 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 197 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 198 DEVMETHOD(ifdi_timer, igc_if_timer), 199 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 200 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 201 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 202 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 203 DEVMETHOD(ifdi_debug, igc_if_debug), 204 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 205 DEVMETHOD_END 206 }; 207 208 static driver_t igc_if_driver = { 209 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 210 }; 211 212 /********************************************************************* 213 * Tunable default values. 214 *********************************************************************/ 215 216 #define IGC_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 217 #define IGC_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 218 219 #define MAX_INTS_PER_SEC 8000 220 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 221 222 /* Allow common code without TSO */ 223 #ifndef CSUM_TSO 224 #define CSUM_TSO 0 225 #endif 226 227 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 228 "igc driver parameters"); 229 230 static int igc_disable_crc_stripping = 0; 231 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 232 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 233 234 static int igc_tx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TIDV_VAL); 235 static int igc_rx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RDTR_VAL); 236 SYSCTL_INT(_hw_igc, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &igc_tx_int_delay_dflt, 237 0, "Default transmit interrupt delay in usecs"); 238 SYSCTL_INT(_hw_igc, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &igc_rx_int_delay_dflt, 239 0, "Default receive interrupt delay in usecs"); 240 241 static int igc_tx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TADV_VAL); 242 static int igc_rx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RADV_VAL); 243 SYSCTL_INT(_hw_igc, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 244 &igc_tx_abs_int_delay_dflt, 0, 245 "Default transmit interrupt delay limit in usecs"); 246 SYSCTL_INT(_hw_igc, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 247 &igc_rx_abs_int_delay_dflt, 0, 248 "Default receive interrupt delay limit in usecs"); 249 250 static int igc_smart_pwr_down = false; 251 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 252 0, "Set to true to leave smart power down enabled on newer adapters"); 253 254 /* Controls whether promiscuous also shows bad packets */ 255 static int igc_debug_sbp = true; 256 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 257 "Show bad packets in promiscuous mode"); 258 259 /* How many packets rxeof tries to clean at a time */ 260 static int igc_rx_process_limit = 100; 261 SYSCTL_INT(_hw_igc, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 262 &igc_rx_process_limit, 0, 263 "Maximum number of received packets to process " 264 "at a time, -1 means unlimited"); 265 266 /* Energy efficient ethernet - default to OFF */ 267 static int igc_eee_setting = 1; 268 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 269 "Enable Energy Efficient Ethernet"); 270 271 /* 272 ** Tuneable Interrupt rate 273 */ 274 static int igc_max_interrupt_rate = 8000; 275 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 276 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 277 278 extern struct if_txrx igc_txrx; 279 280 static struct if_shared_ctx igc_sctx_init = { 281 .isc_magic = IFLIB_MAGIC, 282 .isc_q_align = PAGE_SIZE, 283 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 284 .isc_tx_maxsegsize = PAGE_SIZE, 285 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 286 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 287 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 288 .isc_rx_nsegments = 1, 289 .isc_rx_maxsegsize = MJUM9BYTES, 290 .isc_nfl = 1, 291 .isc_nrxqs = 1, 292 .isc_ntxqs = 1, 293 .isc_admin_intrcnt = 1, 294 .isc_vendor_info = igc_vendor_info_array, 295 .isc_driver_version = "1", 296 .isc_driver = &igc_if_driver, 297 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 298 299 .isc_nrxd_min = {IGC_MIN_RXD}, 300 .isc_ntxd_min = {IGC_MIN_TXD}, 301 .isc_nrxd_max = {IGC_MAX_RXD}, 302 .isc_ntxd_max = {IGC_MAX_TXD}, 303 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 304 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 305 }; 306 307 /***************************************************************** 308 * 309 * Dump Registers 310 * 311 ****************************************************************/ 312 #define IGC_REGS_LEN 739 313 314 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 315 { 316 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 317 struct igc_hw *hw = &adapter->hw; 318 struct sbuf *sb; 319 u32 *regs_buff; 320 int rc; 321 322 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 323 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 324 325 rc = sysctl_wire_old_buffer(req, 0); 326 MPASS(rc == 0); 327 if (rc != 0) { 328 free(regs_buff, M_DEVBUF); 329 return (rc); 330 } 331 332 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 333 MPASS(sb != NULL); 334 if (sb == NULL) { 335 free(regs_buff, M_DEVBUF); 336 return (ENOMEM); 337 } 338 339 /* General Registers */ 340 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 341 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 342 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 343 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 344 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 345 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 346 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 347 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 348 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 349 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 350 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 351 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 352 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 353 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 354 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 355 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 356 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 357 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 358 359 sbuf_printf(sb, "General Registers\n"); 360 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 361 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 362 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 363 364 sbuf_printf(sb, "Interrupt Registers\n"); 365 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 366 367 sbuf_printf(sb, "RX Registers\n"); 368 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 369 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 370 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 371 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 372 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 373 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 374 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 375 376 sbuf_printf(sb, "TX Registers\n"); 377 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 378 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 379 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 380 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 381 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 382 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 383 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 384 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 385 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 386 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 387 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 388 389 free(regs_buff, M_DEVBUF); 390 391 #ifdef DUMP_DESCS 392 { 393 if_softc_ctx_t scctx = adapter->shared; 394 struct rx_ring *rxr = &rx_que->rxr; 395 struct tx_ring *txr = &tx_que->txr; 396 int ntxd = scctx->isc_ntxd[0]; 397 int nrxd = scctx->isc_nrxd[0]; 398 int j; 399 400 for (j = 0; j < nrxd; j++) { 401 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 402 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 403 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 404 } 405 406 for (j = 0; j < min(ntxd, 256); j++) { 407 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 408 409 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 410 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 411 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 412 413 } 414 } 415 #endif 416 417 rc = sbuf_finish(sb); 418 sbuf_delete(sb); 419 return(rc); 420 } 421 422 static void * 423 igc_register(device_t dev) 424 { 425 return (&igc_sctx_init); 426 } 427 428 static int 429 igc_set_num_queues(if_ctx_t ctx) 430 { 431 int maxqueues; 432 433 maxqueues = 4; 434 435 return (maxqueues); 436 } 437 438 #define IGC_CAPS \ 439 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 440 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \ 441 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 442 443 /********************************************************************* 444 * Device initialization routine 445 * 446 * The attach entry point is called when the driver is being loaded. 447 * This routine identifies the type of hardware, allocates all resources 448 * and initializes the hardware. 449 * 450 * return 0 on success, positive on failure 451 *********************************************************************/ 452 static int 453 igc_if_attach_pre(if_ctx_t ctx) 454 { 455 struct igc_adapter *adapter; 456 if_softc_ctx_t scctx; 457 device_t dev; 458 struct igc_hw *hw; 459 int error = 0; 460 461 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 462 dev = iflib_get_dev(ctx); 463 adapter = iflib_get_softc(ctx); 464 465 adapter->ctx = adapter->osdep.ctx = ctx; 466 adapter->dev = adapter->osdep.dev = dev; 467 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 468 adapter->media = iflib_get_media(ctx); 469 hw = &adapter->hw; 470 471 adapter->tx_process_limit = scctx->isc_ntxd[0]; 472 473 /* SYSCTL stuff */ 474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 476 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 477 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 478 479 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 480 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 481 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 482 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 483 484 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 485 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 486 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 487 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 488 489 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 490 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 491 OID_AUTO, "reg_dump", 492 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 493 igc_get_regs, "A", "Dump Registers"); 494 495 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 496 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 497 OID_AUTO, "rs_dump", 498 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 499 igc_get_rs, "I", "Dump RS indexes"); 500 501 /* Determine hardware and mac info */ 502 igc_identify_hardware(ctx); 503 504 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 505 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 506 if (bootverbose) 507 device_printf(dev, "attach_pre capping queues at %d\n", 508 scctx->isc_ntxqsets_max); 509 510 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 511 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 512 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 513 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 514 scctx->isc_txrx = &igc_txrx; 515 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 516 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 517 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 518 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 519 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 520 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 521 522 /* 523 ** Some new devices, as with ixgbe, now may 524 ** use a different BAR, so we need to keep 525 ** track of which is used. 526 */ 527 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 528 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 529 scctx->isc_msix_bar += 4; 530 531 /* Setup PCI resources */ 532 if (igc_allocate_pci_resources(ctx)) { 533 device_printf(dev, "Allocation of PCI resources failed\n"); 534 error = ENXIO; 535 goto err_pci; 536 } 537 538 /* Do Shared Code initialization */ 539 error = igc_setup_init_funcs(hw, true); 540 if (error) { 541 device_printf(dev, "Setup of Shared code failed, error %d\n", 542 error); 543 error = ENXIO; 544 goto err_pci; 545 } 546 547 igc_setup_msix(ctx); 548 igc_get_bus_info(hw); 549 550 /* Set up some sysctls for the tunable interrupt delays */ 551 igc_add_int_delay_sysctl(adapter, "rx_int_delay", 552 "receive interrupt delay in usecs", &adapter->rx_int_delay, 553 IGC_REGISTER(hw, IGC_RDTR), igc_rx_int_delay_dflt); 554 igc_add_int_delay_sysctl(adapter, "tx_int_delay", 555 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 556 IGC_REGISTER(hw, IGC_TIDV), igc_tx_int_delay_dflt); 557 igc_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 558 "receive interrupt delay limit in usecs", 559 &adapter->rx_abs_int_delay, 560 IGC_REGISTER(hw, IGC_RADV), 561 igc_rx_abs_int_delay_dflt); 562 igc_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 563 "transmit interrupt delay limit in usecs", 564 &adapter->tx_abs_int_delay, 565 IGC_REGISTER(hw, IGC_TADV), 566 igc_tx_abs_int_delay_dflt); 567 igc_add_int_delay_sysctl(adapter, "itr", 568 "interrupt delay limit in usecs/4", 569 &adapter->tx_itr, 570 IGC_REGISTER(hw, IGC_ITR), 571 DEFAULT_ITR); 572 573 hw->mac.autoneg = DO_AUTO_NEG; 574 hw->phy.autoneg_wait_to_complete = false; 575 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 576 577 /* Copper options */ 578 if (hw->phy.media_type == igc_media_type_copper) { 579 hw->phy.mdix = AUTO_ALL_MODES; 580 } 581 582 /* 583 * Set the frame limits assuming 584 * standard ethernet sized frames. 585 */ 586 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 587 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 588 589 /* Allocate multicast array memory. */ 590 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 591 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 592 if (adapter->mta == NULL) { 593 device_printf(dev, "Can not allocate multicast setup array\n"); 594 error = ENOMEM; 595 goto err_late; 596 } 597 598 /* Check SOL/IDER usage */ 599 if (igc_check_reset_block(hw)) 600 device_printf(dev, "PHY reset is blocked" 601 " due to SOL/IDER session.\n"); 602 603 /* Sysctl for setting Energy Efficient Ethernet */ 604 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 605 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 606 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 607 OID_AUTO, "eee_control", 608 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 609 adapter, 0, igc_sysctl_eee, "I", 610 "Disable Energy Efficient Ethernet"); 611 612 /* 613 ** Start from a known state, this is 614 ** important in reading the nvm and 615 ** mac from that. 616 */ 617 igc_reset_hw(hw); 618 619 /* Make sure we have a good EEPROM before we read from it */ 620 if (igc_validate_nvm_checksum(hw) < 0) { 621 /* 622 ** Some PCI-E parts fail the first check due to 623 ** the link being in sleep state, call it again, 624 ** if it fails a second time its a real issue. 625 */ 626 if (igc_validate_nvm_checksum(hw) < 0) { 627 device_printf(dev, 628 "The EEPROM Checksum Is Not Valid\n"); 629 error = EIO; 630 goto err_late; 631 } 632 } 633 634 /* Copy the permanent MAC address out of the EEPROM */ 635 if (igc_read_mac_addr(hw) < 0) { 636 device_printf(dev, "EEPROM read error while reading MAC" 637 " address\n"); 638 error = EIO; 639 goto err_late; 640 } 641 642 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 643 device_printf(dev, "Invalid MAC address\n"); 644 error = EIO; 645 goto err_late; 646 } 647 648 /* 649 * Get Wake-on-Lan and Management info for later use 650 */ 651 igc_get_wakeup(ctx); 652 653 /* Enable only WOL MAGIC by default */ 654 scctx->isc_capenable &= ~IFCAP_WOL; 655 if (adapter->wol != 0) 656 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 657 658 iflib_set_mac(ctx, hw->mac.addr); 659 660 return (0); 661 662 err_late: 663 igc_release_hw_control(adapter); 664 err_pci: 665 igc_free_pci_resources(ctx); 666 free(adapter->mta, M_DEVBUF); 667 668 return (error); 669 } 670 671 static int 672 igc_if_attach_post(if_ctx_t ctx) 673 { 674 struct igc_adapter *adapter = iflib_get_softc(ctx); 675 struct igc_hw *hw = &adapter->hw; 676 int error = 0; 677 678 /* Setup OS specific network interface */ 679 error = igc_setup_interface(ctx); 680 if (error != 0) { 681 goto err_late; 682 } 683 684 igc_reset(ctx); 685 686 /* Initialize statistics */ 687 igc_update_stats_counters(adapter); 688 hw->mac.get_link_status = true; 689 igc_if_update_admin_status(ctx); 690 igc_add_hw_stats(adapter); 691 692 /* the driver can now take control from firmware */ 693 igc_get_hw_control(adapter); 694 695 INIT_DEBUGOUT("igc_if_attach_post: end"); 696 697 return (error); 698 699 err_late: 700 igc_release_hw_control(adapter); 701 igc_free_pci_resources(ctx); 702 igc_if_queues_free(ctx); 703 free(adapter->mta, M_DEVBUF); 704 705 return (error); 706 } 707 708 /********************************************************************* 709 * Device removal routine 710 * 711 * The detach entry point is called when the driver is being removed. 712 * This routine stops the adapter and deallocates all the resources 713 * that were allocated for driver operation. 714 * 715 * return 0 on success, positive on failure 716 *********************************************************************/ 717 static int 718 igc_if_detach(if_ctx_t ctx) 719 { 720 struct igc_adapter *adapter = iflib_get_softc(ctx); 721 722 INIT_DEBUGOUT("igc_if_detach: begin"); 723 724 igc_phy_hw_reset(&adapter->hw); 725 726 igc_release_hw_control(adapter); 727 igc_free_pci_resources(ctx); 728 729 return (0); 730 } 731 732 /********************************************************************* 733 * 734 * Shutdown entry point 735 * 736 **********************************************************************/ 737 738 static int 739 igc_if_shutdown(if_ctx_t ctx) 740 { 741 return igc_if_suspend(ctx); 742 } 743 744 /* 745 * Suspend/resume device methods. 746 */ 747 static int 748 igc_if_suspend(if_ctx_t ctx) 749 { 750 struct igc_adapter *adapter = iflib_get_softc(ctx); 751 752 igc_release_hw_control(adapter); 753 igc_enable_wakeup(ctx); 754 return (0); 755 } 756 757 static int 758 igc_if_resume(if_ctx_t ctx) 759 { 760 igc_if_init(ctx); 761 762 return(0); 763 } 764 765 static int 766 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 767 { 768 int max_frame_size; 769 struct igc_adapter *adapter = iflib_get_softc(ctx); 770 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 771 772 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 773 774 /* 9K Jumbo Frame size */ 775 max_frame_size = 9234; 776 777 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 778 return (EINVAL); 779 } 780 781 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 782 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 783 return (0); 784 } 785 786 /********************************************************************* 787 * Init entry point 788 * 789 * This routine is used in two ways. It is used by the stack as 790 * init entry point in network interface structure. It is also used 791 * by the driver as a hw/sw initialization routine to get to a 792 * consistent state. 793 * 794 **********************************************************************/ 795 static void 796 igc_if_init(if_ctx_t ctx) 797 { 798 struct igc_adapter *adapter = iflib_get_softc(ctx); 799 if_softc_ctx_t scctx = adapter->shared; 800 if_t ifp = iflib_get_ifp(ctx); 801 struct igc_tx_queue *tx_que; 802 int i; 803 804 INIT_DEBUGOUT("igc_if_init: begin"); 805 806 /* Get the latest mac address, User can use a LAA */ 807 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 808 ETHER_ADDR_LEN); 809 810 /* Put the address into the Receive Address Array */ 811 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 812 813 /* Initialize the hardware */ 814 igc_reset(ctx); 815 igc_if_update_admin_status(ctx); 816 817 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 818 struct tx_ring *txr = &tx_que->txr; 819 820 txr->tx_rs_cidx = txr->tx_rs_pidx; 821 822 /* Initialize the last processed descriptor to be the end of 823 * the ring, rather than the start, so that we avoid an 824 * off-by-one error when calculating how many descriptors are 825 * done in the credits_update function. 826 */ 827 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 828 } 829 830 /* Setup VLAN support, basic and offload if available */ 831 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 832 833 /* Prepare transmit descriptors and buffers */ 834 igc_initialize_transmit_unit(ctx); 835 836 /* Setup Multicast table */ 837 igc_if_multi_set(ctx); 838 839 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 840 igc_initialize_receive_unit(ctx); 841 842 /* Set up VLAN support */ 843 igc_setup_vlan_hw_support(ctx); 844 845 /* Don't lose promiscuous settings */ 846 igc_if_set_promisc(ctx, if_getflags(ifp)); 847 igc_clear_hw_cntrs_base_generic(&adapter->hw); 848 849 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 850 igc_configure_queues(adapter); 851 852 /* this clears any pending interrupts */ 853 IGC_READ_REG(&adapter->hw, IGC_ICR); 854 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 855 856 /* the driver can now take control from firmware */ 857 igc_get_hw_control(adapter); 858 859 /* Set Energy Efficient Ethernet */ 860 igc_set_eee_i225(&adapter->hw, true, true, true); 861 } 862 863 /********************************************************************* 864 * 865 * Fast Legacy/MSI Combined Interrupt Service routine 866 * 867 *********************************************************************/ 868 int 869 igc_intr(void *arg) 870 { 871 struct igc_adapter *adapter = arg; 872 if_ctx_t ctx = adapter->ctx; 873 u32 reg_icr; 874 875 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 876 877 /* Hot eject? */ 878 if (reg_icr == 0xffffffff) 879 return FILTER_STRAY; 880 881 /* Definitely not our interrupt. */ 882 if (reg_icr == 0x0) 883 return FILTER_STRAY; 884 885 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 886 return FILTER_STRAY; 887 888 /* 889 * Only MSI-X interrupts have one-shot behavior by taking advantage 890 * of the EIAC register. Thus, explicitly disable interrupts. This 891 * also works around the MSI message reordering errata on certain 892 * systems. 893 */ 894 IFDI_INTR_DISABLE(ctx); 895 896 /* Link status change */ 897 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 898 igc_handle_link(ctx); 899 900 if (reg_icr & IGC_ICR_RXO) 901 adapter->rx_overruns++; 902 903 return (FILTER_SCHEDULE_THREAD); 904 } 905 906 static int 907 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 908 { 909 struct igc_adapter *adapter = iflib_get_softc(ctx); 910 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 911 912 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 913 return (0); 914 } 915 916 static int 917 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 918 { 919 struct igc_adapter *adapter = iflib_get_softc(ctx); 920 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 921 922 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 923 return (0); 924 } 925 926 /********************************************************************* 927 * 928 * MSI-X RX Interrupt Service routine 929 * 930 **********************************************************************/ 931 static int 932 igc_msix_que(void *arg) 933 { 934 struct igc_rx_queue *que = arg; 935 936 ++que->irqs; 937 938 return (FILTER_SCHEDULE_THREAD); 939 } 940 941 /********************************************************************* 942 * 943 * MSI-X Link Fast Interrupt Service routine 944 * 945 **********************************************************************/ 946 static int 947 igc_msix_link(void *arg) 948 { 949 struct igc_adapter *adapter = arg; 950 u32 reg_icr; 951 952 ++adapter->link_irq; 953 MPASS(adapter->hw.back != NULL); 954 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 955 956 if (reg_icr & IGC_ICR_RXO) 957 adapter->rx_overruns++; 958 959 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 960 igc_handle_link(adapter->ctx); 961 } 962 963 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 964 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 965 966 return (FILTER_HANDLED); 967 } 968 969 static void 970 igc_handle_link(void *context) 971 { 972 if_ctx_t ctx = context; 973 struct igc_adapter *adapter = iflib_get_softc(ctx); 974 975 adapter->hw.mac.get_link_status = true; 976 iflib_admin_intr_deferred(ctx); 977 } 978 979 /********************************************************************* 980 * 981 * Media Ioctl callback 982 * 983 * This routine is called whenever the user queries the status of 984 * the interface using ifconfig. 985 * 986 **********************************************************************/ 987 static void 988 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 989 { 990 struct igc_adapter *adapter = iflib_get_softc(ctx); 991 992 INIT_DEBUGOUT("igc_if_media_status: begin"); 993 994 iflib_admin_intr_deferred(ctx); 995 996 ifmr->ifm_status = IFM_AVALID; 997 ifmr->ifm_active = IFM_ETHER; 998 999 if (!adapter->link_active) { 1000 return; 1001 } 1002 1003 ifmr->ifm_status |= IFM_ACTIVE; 1004 1005 switch (adapter->link_speed) { 1006 case 10: 1007 ifmr->ifm_active |= IFM_10_T; 1008 break; 1009 case 100: 1010 ifmr->ifm_active |= IFM_100_TX; 1011 break; 1012 case 1000: 1013 ifmr->ifm_active |= IFM_1000_T; 1014 break; 1015 case 2500: 1016 ifmr->ifm_active |= IFM_2500_T; 1017 break; 1018 } 1019 1020 if (adapter->link_duplex == FULL_DUPLEX) 1021 ifmr->ifm_active |= IFM_FDX; 1022 else 1023 ifmr->ifm_active |= IFM_HDX; 1024 } 1025 1026 /********************************************************************* 1027 * 1028 * Media Ioctl callback 1029 * 1030 * This routine is called when the user changes speed/duplex using 1031 * media/mediopt option with ifconfig. 1032 * 1033 **********************************************************************/ 1034 static int 1035 igc_if_media_change(if_ctx_t ctx) 1036 { 1037 struct igc_adapter *adapter = iflib_get_softc(ctx); 1038 struct ifmedia *ifm = iflib_get_media(ctx); 1039 1040 INIT_DEBUGOUT("igc_if_media_change: begin"); 1041 1042 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1043 return (EINVAL); 1044 1045 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1046 1047 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1048 case IFM_AUTO: 1049 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1050 break; 1051 case IFM_2500_T: 1052 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1053 break; 1054 case IFM_1000_T: 1055 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1056 break; 1057 case IFM_100_TX: 1058 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1059 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1060 else 1061 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1062 break; 1063 case IFM_10_T: 1064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1065 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1066 else 1067 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1068 break; 1069 default: 1070 device_printf(adapter->dev, "Unsupported media type\n"); 1071 } 1072 1073 igc_if_init(ctx); 1074 1075 return (0); 1076 } 1077 1078 static int 1079 igc_if_set_promisc(if_ctx_t ctx, int flags) 1080 { 1081 struct igc_adapter *adapter = iflib_get_softc(ctx); 1082 if_t ifp = iflib_get_ifp(ctx); 1083 u32 reg_rctl; 1084 int mcnt = 0; 1085 1086 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1087 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1088 if (flags & IFF_ALLMULTI) 1089 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1090 else 1091 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1092 1093 /* Don't disable if in MAX groups */ 1094 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1095 reg_rctl &= (~IGC_RCTL_MPE); 1096 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1097 1098 if (flags & IFF_PROMISC) { 1099 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1100 /* Turn this on if you want to see bad packets */ 1101 if (igc_debug_sbp) 1102 reg_rctl |= IGC_RCTL_SBP; 1103 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1104 } else if (flags & IFF_ALLMULTI) { 1105 reg_rctl |= IGC_RCTL_MPE; 1106 reg_rctl &= ~IGC_RCTL_UPE; 1107 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1108 } 1109 return (0); 1110 } 1111 1112 static u_int 1113 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1114 { 1115 u8 *mta = arg; 1116 1117 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1118 return (0); 1119 1120 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1121 1122 return (1); 1123 } 1124 1125 /********************************************************************* 1126 * Multicast Update 1127 * 1128 * This routine is called whenever multicast address list is updated. 1129 * 1130 **********************************************************************/ 1131 1132 static void 1133 igc_if_multi_set(if_ctx_t ctx) 1134 { 1135 struct igc_adapter *adapter = iflib_get_softc(ctx); 1136 if_t ifp = iflib_get_ifp(ctx); 1137 u8 *mta; /* Multicast array memory */ 1138 u32 reg_rctl = 0; 1139 int mcnt = 0; 1140 1141 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1142 1143 mta = adapter->mta; 1144 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1145 1146 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1147 1148 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1149 1150 if (if_getflags(ifp) & IFF_PROMISC) { 1151 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1152 /* Turn this on if you want to see bad packets */ 1153 if (igc_debug_sbp) 1154 reg_rctl |= IGC_RCTL_SBP; 1155 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1156 if_getflags(ifp) & IFF_ALLMULTI) { 1157 reg_rctl |= IGC_RCTL_MPE; 1158 reg_rctl &= ~IGC_RCTL_UPE; 1159 } else 1160 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1161 1162 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1163 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1164 1165 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1166 } 1167 1168 /********************************************************************* 1169 * Timer routine 1170 * 1171 * This routine schedules igc_if_update_admin_status() to check for 1172 * link status and to gather statistics as well as to perform some 1173 * controller-specific hardware patting. 1174 * 1175 **********************************************************************/ 1176 static void 1177 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1178 { 1179 1180 if (qid != 0) 1181 return; 1182 1183 iflib_admin_intr_deferred(ctx); 1184 } 1185 1186 static void 1187 igc_if_update_admin_status(if_ctx_t ctx) 1188 { 1189 struct igc_adapter *adapter = iflib_get_softc(ctx); 1190 struct igc_hw *hw = &adapter->hw; 1191 device_t dev = iflib_get_dev(ctx); 1192 u32 link_check, thstat, ctrl; 1193 1194 link_check = thstat = ctrl = 0; 1195 /* Get the cached link value or read phy for real */ 1196 switch (hw->phy.media_type) { 1197 case igc_media_type_copper: 1198 if (hw->mac.get_link_status == true) { 1199 /* Do the work to read phy */ 1200 igc_check_for_link(hw); 1201 link_check = !hw->mac.get_link_status; 1202 } else 1203 link_check = true; 1204 break; 1205 case igc_media_type_unknown: 1206 igc_check_for_link(hw); 1207 link_check = !hw->mac.get_link_status; 1208 /* FALLTHROUGH */ 1209 default: 1210 break; 1211 } 1212 1213 /* Now check for a transition */ 1214 if (link_check && (adapter->link_active == 0)) { 1215 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1216 &adapter->link_duplex); 1217 if (bootverbose) 1218 device_printf(dev, "Link is up %d Mbps %s\n", 1219 adapter->link_speed, 1220 ((adapter->link_duplex == FULL_DUPLEX) ? 1221 "Full Duplex" : "Half Duplex")); 1222 adapter->link_active = 1; 1223 iflib_link_state_change(ctx, LINK_STATE_UP, 1224 IF_Mbps(adapter->link_speed)); 1225 } else if (!link_check && (adapter->link_active == 1)) { 1226 adapter->link_speed = 0; 1227 adapter->link_duplex = 0; 1228 adapter->link_active = 0; 1229 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1230 } 1231 igc_update_stats_counters(adapter); 1232 } 1233 1234 static void 1235 igc_if_watchdog_reset(if_ctx_t ctx) 1236 { 1237 struct igc_adapter *adapter = iflib_get_softc(ctx); 1238 1239 /* 1240 * Just count the event; iflib(4) will already trigger a 1241 * sufficient reset of the controller. 1242 */ 1243 adapter->watchdog_events++; 1244 } 1245 1246 /********************************************************************* 1247 * 1248 * This routine disables all traffic on the adapter by issuing a 1249 * global reset on the MAC. 1250 * 1251 **********************************************************************/ 1252 static void 1253 igc_if_stop(if_ctx_t ctx) 1254 { 1255 struct igc_adapter *adapter = iflib_get_softc(ctx); 1256 1257 INIT_DEBUGOUT("igc_if_stop: begin"); 1258 1259 igc_reset_hw(&adapter->hw); 1260 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1261 } 1262 1263 /********************************************************************* 1264 * 1265 * Determine hardware revision. 1266 * 1267 **********************************************************************/ 1268 static void 1269 igc_identify_hardware(if_ctx_t ctx) 1270 { 1271 device_t dev = iflib_get_dev(ctx); 1272 struct igc_adapter *adapter = iflib_get_softc(ctx); 1273 1274 /* Make sure our PCI config space has the necessary stuff set */ 1275 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1276 1277 /* Save off the information about this board */ 1278 adapter->hw.vendor_id = pci_get_vendor(dev); 1279 adapter->hw.device_id = pci_get_device(dev); 1280 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1281 adapter->hw.subsystem_vendor_id = 1282 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1283 adapter->hw.subsystem_device_id = 1284 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1285 1286 /* Do Shared Code Init and Setup */ 1287 if (igc_set_mac_type(&adapter->hw)) { 1288 device_printf(dev, "Setup init failure\n"); 1289 return; 1290 } 1291 } 1292 1293 static int 1294 igc_allocate_pci_resources(if_ctx_t ctx) 1295 { 1296 struct igc_adapter *adapter = iflib_get_softc(ctx); 1297 device_t dev = iflib_get_dev(ctx); 1298 int rid; 1299 1300 rid = PCIR_BAR(0); 1301 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1302 &rid, RF_ACTIVE); 1303 if (adapter->memory == NULL) { 1304 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1305 return (ENXIO); 1306 } 1307 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1308 adapter->osdep.mem_bus_space_handle = 1309 rman_get_bushandle(adapter->memory); 1310 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1311 1312 adapter->hw.back = &adapter->osdep; 1313 1314 return (0); 1315 } 1316 1317 /********************************************************************* 1318 * 1319 * Set up the MSI-X Interrupt handlers 1320 * 1321 **********************************************************************/ 1322 static int 1323 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1324 { 1325 struct igc_adapter *adapter = iflib_get_softc(ctx); 1326 struct igc_rx_queue *rx_que = adapter->rx_queues; 1327 struct igc_tx_queue *tx_que = adapter->tx_queues; 1328 int error, rid, i, vector = 0, rx_vectors; 1329 char buf[16]; 1330 1331 /* First set up ring resources */ 1332 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1333 rid = vector + 1; 1334 snprintf(buf, sizeof(buf), "rxq%d", i); 1335 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1336 if (error) { 1337 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1338 adapter->rx_num_queues = i + 1; 1339 goto fail; 1340 } 1341 1342 rx_que->msix = vector; 1343 1344 /* 1345 * Set the bit to enable interrupt 1346 * in IGC_IMS -- bits 20 and 21 1347 * are for RX0 and RX1, note this has 1348 * NOTHING to do with the MSI-X vector 1349 */ 1350 rx_que->eims = 1 << vector; 1351 } 1352 rx_vectors = vector; 1353 1354 vector = 0; 1355 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1356 snprintf(buf, sizeof(buf), "txq%d", i); 1357 tx_que = &adapter->tx_queues[i]; 1358 iflib_softirq_alloc_generic(ctx, 1359 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1360 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1361 1362 tx_que->msix = (vector % adapter->rx_num_queues); 1363 1364 /* 1365 * Set the bit to enable interrupt 1366 * in IGC_IMS -- bits 22 and 23 1367 * are for TX0 and TX1, note this has 1368 * NOTHING to do with the MSI-X vector 1369 */ 1370 tx_que->eims = 1 << i; 1371 } 1372 1373 /* Link interrupt */ 1374 rid = rx_vectors + 1; 1375 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1376 1377 if (error) { 1378 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1379 goto fail; 1380 } 1381 adapter->linkvec = rx_vectors; 1382 return (0); 1383 fail: 1384 iflib_irq_free(ctx, &adapter->irq); 1385 rx_que = adapter->rx_queues; 1386 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1387 iflib_irq_free(ctx, &rx_que->que_irq); 1388 return (error); 1389 } 1390 1391 static void 1392 igc_configure_queues(struct igc_adapter *adapter) 1393 { 1394 struct igc_hw *hw = &adapter->hw; 1395 struct igc_rx_queue *rx_que; 1396 struct igc_tx_queue *tx_que; 1397 u32 ivar = 0, newitr = 0; 1398 1399 /* First turn on RSS capability */ 1400 IGC_WRITE_REG(hw, IGC_GPIE, 1401 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1402 IGC_GPIE_NSICR); 1403 1404 /* Turn on MSI-X */ 1405 /* RX entries */ 1406 for (int i = 0; i < adapter->rx_num_queues; i++) { 1407 u32 index = i >> 1; 1408 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1409 rx_que = &adapter->rx_queues[i]; 1410 if (i & 1) { 1411 ivar &= 0xFF00FFFF; 1412 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1413 } else { 1414 ivar &= 0xFFFFFF00; 1415 ivar |= rx_que->msix | IGC_IVAR_VALID; 1416 } 1417 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1418 } 1419 /* TX entries */ 1420 for (int i = 0; i < adapter->tx_num_queues; i++) { 1421 u32 index = i >> 1; 1422 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1423 tx_que = &adapter->tx_queues[i]; 1424 if (i & 1) { 1425 ivar &= 0x00FFFFFF; 1426 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1427 } else { 1428 ivar &= 0xFFFF00FF; 1429 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1430 } 1431 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1432 adapter->que_mask |= tx_que->eims; 1433 } 1434 1435 /* And for the link interrupt */ 1436 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1437 adapter->link_mask = 1 << adapter->linkvec; 1438 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1439 1440 /* Set the starting interrupt rate */ 1441 if (igc_max_interrupt_rate > 0) 1442 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1443 1444 newitr |= IGC_EITR_CNT_IGNR; 1445 1446 for (int i = 0; i < adapter->rx_num_queues; i++) { 1447 rx_que = &adapter->rx_queues[i]; 1448 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1449 } 1450 1451 return; 1452 } 1453 1454 static void 1455 igc_free_pci_resources(if_ctx_t ctx) 1456 { 1457 struct igc_adapter *adapter = iflib_get_softc(ctx); 1458 struct igc_rx_queue *que = adapter->rx_queues; 1459 device_t dev = iflib_get_dev(ctx); 1460 1461 /* Release all MSI-X queue resources */ 1462 if (adapter->intr_type == IFLIB_INTR_MSIX) 1463 iflib_irq_free(ctx, &adapter->irq); 1464 1465 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1466 iflib_irq_free(ctx, &que->que_irq); 1467 } 1468 1469 if (adapter->memory != NULL) { 1470 bus_release_resource(dev, SYS_RES_MEMORY, 1471 rman_get_rid(adapter->memory), adapter->memory); 1472 adapter->memory = NULL; 1473 } 1474 1475 if (adapter->flash != NULL) { 1476 bus_release_resource(dev, SYS_RES_MEMORY, 1477 rman_get_rid(adapter->flash), adapter->flash); 1478 adapter->flash = NULL; 1479 } 1480 1481 if (adapter->ioport != NULL) { 1482 bus_release_resource(dev, SYS_RES_IOPORT, 1483 rman_get_rid(adapter->ioport), adapter->ioport); 1484 adapter->ioport = NULL; 1485 } 1486 } 1487 1488 /* Set up MSI or MSI-X */ 1489 static int 1490 igc_setup_msix(if_ctx_t ctx) 1491 { 1492 return (0); 1493 } 1494 1495 /********************************************************************* 1496 * 1497 * Initialize the DMA Coalescing feature 1498 * 1499 **********************************************************************/ 1500 static void 1501 igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1502 { 1503 device_t dev = adapter->dev; 1504 struct igc_hw *hw = &adapter->hw; 1505 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1506 u16 hwm; 1507 u16 max_frame_size; 1508 int status; 1509 1510 max_frame_size = adapter->shared->isc_max_frame_size; 1511 1512 if (adapter->dmac == 0) { /* Disabling it */ 1513 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1514 return; 1515 } else 1516 device_printf(dev, "DMA Coalescing enabled\n"); 1517 1518 /* Set starting threshold */ 1519 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1520 1521 hwm = 64 * pba - max_frame_size / 16; 1522 if (hwm < 64 * (pba - 6)) 1523 hwm = 64 * (pba - 6); 1524 reg = IGC_READ_REG(hw, IGC_FCRTC); 1525 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1526 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1527 & IGC_FCRTC_RTH_COAL_MASK); 1528 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1529 1530 dmac = pba - max_frame_size / 512; 1531 if (dmac < pba - 10) 1532 dmac = pba - 10; 1533 reg = IGC_READ_REG(hw, IGC_DMACR); 1534 reg &= ~IGC_DMACR_DMACTHR_MASK; 1535 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1536 & IGC_DMACR_DMACTHR_MASK); 1537 1538 /* transition to L0x or L1 if available..*/ 1539 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1540 1541 /* Check if status is 2.5Gb backplane connection 1542 * before configuration of watchdog timer, which is 1543 * in msec values in 12.8usec intervals 1544 * watchdog timer= msec values in 32usec intervals 1545 * for non 2.5Gb connection 1546 */ 1547 status = IGC_READ_REG(hw, IGC_STATUS); 1548 if ((status & IGC_STATUS_2P5_SKU) && 1549 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1550 reg |= ((adapter->dmac * 5) >> 6); 1551 else 1552 reg |= (adapter->dmac >> 5); 1553 1554 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1555 1556 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1557 1558 /* Set the interval before transition */ 1559 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1560 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1561 1562 /* 1563 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1564 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1565 */ 1566 status = IGC_READ_REG(hw, IGC_STATUS); 1567 if ((status & IGC_STATUS_2P5_SKU) && 1568 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1569 reg |= 0xA; 1570 else 1571 reg |= 0x4; 1572 1573 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1574 1575 /* free space in tx packet buffer to wake from DMA coal */ 1576 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1577 (2 * max_frame_size)) >> 6); 1578 1579 /* make low power state decision controlled by DMA coal */ 1580 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1581 reg &= ~IGC_PCIEMISC_LX_DECISION; 1582 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1583 } 1584 1585 /********************************************************************* 1586 * 1587 * Initialize the hardware to a configuration as specified by the 1588 * adapter structure. 1589 * 1590 **********************************************************************/ 1591 static void 1592 igc_reset(if_ctx_t ctx) 1593 { 1594 device_t dev = iflib_get_dev(ctx); 1595 struct igc_adapter *adapter = iflib_get_softc(ctx); 1596 struct igc_hw *hw = &adapter->hw; 1597 u32 rx_buffer_size; 1598 u32 pba; 1599 1600 INIT_DEBUGOUT("igc_reset: begin"); 1601 /* Let the firmware know the OS is in control */ 1602 igc_get_hw_control(adapter); 1603 1604 /* 1605 * Packet Buffer Allocation (PBA) 1606 * Writing PBA sets the receive portion of the buffer 1607 * the remainder is used for the transmit buffer. 1608 */ 1609 pba = IGC_PBA_34K; 1610 1611 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1612 1613 /* 1614 * These parameters control the automatic generation (Tx) and 1615 * response (Rx) to Ethernet PAUSE frames. 1616 * - High water mark should allow for at least two frames to be 1617 * received after sending an XOFF. 1618 * - Low water mark works best when it is very near the high water mark. 1619 * This allows the receiver to restart by sending XON when it has 1620 * drained a bit. Here we use an arbitrary value of 1500 which will 1621 * restart after one full frame is pulled from the buffer. There 1622 * could be several smaller frames in the buffer and if so they will 1623 * not trigger the XON until their total number reduces the buffer 1624 * by 1500. 1625 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1626 */ 1627 rx_buffer_size = (pba & 0xffff) << 10; 1628 hw->fc.high_water = rx_buffer_size - 1629 roundup2(adapter->hw.mac.max_frame_size, 1024); 1630 /* 16-byte granularity */ 1631 hw->fc.low_water = hw->fc.high_water - 16; 1632 1633 if (adapter->fc) /* locally set flow control value? */ 1634 hw->fc.requested_mode = adapter->fc; 1635 else 1636 hw->fc.requested_mode = igc_fc_full; 1637 1638 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1639 1640 hw->fc.send_xon = true; 1641 1642 /* Issue a global reset */ 1643 igc_reset_hw(hw); 1644 IGC_WRITE_REG(hw, IGC_WUC, 0); 1645 1646 /* and a re-init */ 1647 if (igc_init_hw(hw) < 0) { 1648 device_printf(dev, "Hardware Initialization Failed\n"); 1649 return; 1650 } 1651 1652 /* Setup DMA Coalescing */ 1653 igc_init_dmac(adapter, pba); 1654 1655 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1656 igc_get_phy_info(hw); 1657 igc_check_for_link(hw); 1658 } 1659 1660 /* 1661 * Initialise the RSS mapping for NICs that support multiple transmit/ 1662 * receive rings. 1663 */ 1664 1665 #define RSSKEYLEN 10 1666 static void 1667 igc_initialize_rss_mapping(struct igc_adapter *adapter) 1668 { 1669 struct igc_hw *hw = &adapter->hw; 1670 int i; 1671 int queue_id; 1672 u32 reta; 1673 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1674 1675 /* 1676 * The redirection table controls which destination 1677 * queue each bucket redirects traffic to. 1678 * Each DWORD represents four queues, with the LSB 1679 * being the first queue in the DWORD. 1680 * 1681 * This just allocates buckets to queues using round-robin 1682 * allocation. 1683 * 1684 * NOTE: It Just Happens to line up with the default 1685 * RSS allocation method. 1686 */ 1687 1688 /* Warning FM follows */ 1689 reta = 0; 1690 for (i = 0; i < 128; i++) { 1691 #ifdef RSS 1692 queue_id = rss_get_indirection_to_bucket(i); 1693 /* 1694 * If we have more queues than buckets, we'll 1695 * end up mapping buckets to a subset of the 1696 * queues. 1697 * 1698 * If we have more buckets than queues, we'll 1699 * end up instead assigning multiple buckets 1700 * to queues. 1701 * 1702 * Both are suboptimal, but we need to handle 1703 * the case so we don't go out of bounds 1704 * indexing arrays and such. 1705 */ 1706 queue_id = queue_id % adapter->rx_num_queues; 1707 #else 1708 queue_id = (i % adapter->rx_num_queues); 1709 #endif 1710 /* Adjust if required */ 1711 queue_id = queue_id << shift; 1712 1713 /* 1714 * The low 8 bits are for hash value (n+0); 1715 * The next 8 bits are for hash value (n+1), etc. 1716 */ 1717 reta = reta >> 8; 1718 reta = reta | ( ((uint32_t) queue_id) << 24); 1719 if ((i & 3) == 3) { 1720 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1721 reta = 0; 1722 } 1723 } 1724 1725 /* Now fill in hash table */ 1726 1727 /* 1728 * MRQC: Multiple Receive Queues Command 1729 * Set queuing to RSS control, number depends on the device. 1730 */ 1731 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1732 1733 #ifdef RSS 1734 /* XXX ew typecasting */ 1735 rss_getkey((uint8_t *) &rss_key); 1736 #else 1737 arc4rand(&rss_key, sizeof(rss_key), 0); 1738 #endif 1739 for (i = 0; i < RSSKEYLEN; i++) 1740 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1741 1742 /* 1743 * Configure the RSS fields to hash upon. 1744 */ 1745 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1746 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1747 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1748 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1749 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1750 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1751 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1752 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1753 1754 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1755 } 1756 1757 /********************************************************************* 1758 * 1759 * Setup networking device structure and register interface media. 1760 * 1761 **********************************************************************/ 1762 static int 1763 igc_setup_interface(if_ctx_t ctx) 1764 { 1765 if_t ifp = iflib_get_ifp(ctx); 1766 struct igc_adapter *adapter = iflib_get_softc(ctx); 1767 if_softc_ctx_t scctx = adapter->shared; 1768 1769 INIT_DEBUGOUT("igc_setup_interface: begin"); 1770 1771 /* Single Queue */ 1772 if (adapter->tx_num_queues == 1) { 1773 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1774 if_setsendqready(ifp); 1775 } 1776 1777 /* 1778 * Specify the media types supported by this adapter and register 1779 * callbacks to update media and link information 1780 */ 1781 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1782 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1783 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1784 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1785 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1786 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1787 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1788 1789 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1790 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1791 return (0); 1792 } 1793 1794 static int 1795 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1796 { 1797 struct igc_adapter *adapter = iflib_get_softc(ctx); 1798 if_softc_ctx_t scctx = adapter->shared; 1799 int error = IGC_SUCCESS; 1800 struct igc_tx_queue *que; 1801 int i, j; 1802 1803 MPASS(adapter->tx_num_queues > 0); 1804 MPASS(adapter->tx_num_queues == ntxqsets); 1805 1806 /* First allocate the top level queue structs */ 1807 if (!(adapter->tx_queues = 1808 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1809 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1810 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1811 return(ENOMEM); 1812 } 1813 1814 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1815 /* Set up some basics */ 1816 1817 struct tx_ring *txr = &que->txr; 1818 txr->adapter = que->adapter = adapter; 1819 que->me = txr->me = i; 1820 1821 /* Allocate report status array */ 1822 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1823 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1824 error = ENOMEM; 1825 goto fail; 1826 } 1827 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1828 txr->tx_rsq[j] = QIDX_INVALID; 1829 /* get the virtual and physical address of the hardware queues */ 1830 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1831 txr->tx_paddr = paddrs[i*ntxqs]; 1832 } 1833 1834 if (bootverbose) 1835 device_printf(iflib_get_dev(ctx), 1836 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1837 return (0); 1838 fail: 1839 igc_if_queues_free(ctx); 1840 return (error); 1841 } 1842 1843 static int 1844 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1845 { 1846 struct igc_adapter *adapter = iflib_get_softc(ctx); 1847 int error = IGC_SUCCESS; 1848 struct igc_rx_queue *que; 1849 int i; 1850 1851 MPASS(adapter->rx_num_queues > 0); 1852 MPASS(adapter->rx_num_queues == nrxqsets); 1853 1854 /* First allocate the top level queue structs */ 1855 if (!(adapter->rx_queues = 1856 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1857 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1858 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1859 error = ENOMEM; 1860 goto fail; 1861 } 1862 1863 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1864 /* Set up some basics */ 1865 struct rx_ring *rxr = &que->rxr; 1866 rxr->adapter = que->adapter = adapter; 1867 rxr->que = que; 1868 que->me = rxr->me = i; 1869 1870 /* get the virtual and physical address of the hardware queues */ 1871 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1872 rxr->rx_paddr = paddrs[i*nrxqs]; 1873 } 1874 1875 if (bootverbose) 1876 device_printf(iflib_get_dev(ctx), 1877 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1878 1879 return (0); 1880 fail: 1881 igc_if_queues_free(ctx); 1882 return (error); 1883 } 1884 1885 static void 1886 igc_if_queues_free(if_ctx_t ctx) 1887 { 1888 struct igc_adapter *adapter = iflib_get_softc(ctx); 1889 struct igc_tx_queue *tx_que = adapter->tx_queues; 1890 struct igc_rx_queue *rx_que = adapter->rx_queues; 1891 1892 if (tx_que != NULL) { 1893 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1894 struct tx_ring *txr = &tx_que->txr; 1895 if (txr->tx_rsq == NULL) 1896 break; 1897 1898 free(txr->tx_rsq, M_DEVBUF); 1899 txr->tx_rsq = NULL; 1900 } 1901 free(adapter->tx_queues, M_DEVBUF); 1902 adapter->tx_queues = NULL; 1903 } 1904 1905 if (rx_que != NULL) { 1906 free(adapter->rx_queues, M_DEVBUF); 1907 adapter->rx_queues = NULL; 1908 } 1909 1910 igc_release_hw_control(adapter); 1911 1912 if (adapter->mta != NULL) { 1913 free(adapter->mta, M_DEVBUF); 1914 } 1915 } 1916 1917 /********************************************************************* 1918 * 1919 * Enable transmit unit. 1920 * 1921 **********************************************************************/ 1922 static void 1923 igc_initialize_transmit_unit(if_ctx_t ctx) 1924 { 1925 struct igc_adapter *adapter = iflib_get_softc(ctx); 1926 if_softc_ctx_t scctx = adapter->shared; 1927 struct igc_tx_queue *que; 1928 struct tx_ring *txr; 1929 struct igc_hw *hw = &adapter->hw; 1930 u32 tctl, txdctl = 0; 1931 1932 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1933 1934 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1935 u64 bus_addr; 1936 caddr_t offp, endp; 1937 1938 que = &adapter->tx_queues[i]; 1939 txr = &que->txr; 1940 bus_addr = txr->tx_paddr; 1941 1942 /* Clear checksum offload context. */ 1943 offp = (caddr_t)&txr->csum_flags; 1944 endp = (caddr_t)(txr + 1); 1945 bzero(offp, endp - offp); 1946 1947 /* Base and Len of TX Ring */ 1948 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1949 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1950 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1951 (u32)(bus_addr >> 32)); 1952 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1953 (u32)bus_addr); 1954 /* Init the HEAD/TAIL indices */ 1955 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1956 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1957 1958 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1959 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1960 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1961 1962 txdctl = 0; /* clear txdctl */ 1963 txdctl |= 0x1f; /* PTHRESH */ 1964 txdctl |= 1 << 8; /* HTHRESH */ 1965 txdctl |= 1 << 16;/* WTHRESH */ 1966 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1967 txdctl |= IGC_TXDCTL_GRAN; 1968 txdctl |= 1 << 25; /* LWTHRESH */ 1969 1970 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1971 } 1972 1973 /* Program the Transmit Control Register */ 1974 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1975 tctl &= ~IGC_TCTL_CT; 1976 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1977 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1978 1979 /* This write will effectively turn on the transmit unit. */ 1980 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1981 } 1982 1983 /********************************************************************* 1984 * 1985 * Enable receive unit. 1986 * 1987 **********************************************************************/ 1988 1989 static void 1990 igc_initialize_receive_unit(if_ctx_t ctx) 1991 { 1992 struct igc_adapter *adapter = iflib_get_softc(ctx); 1993 if_softc_ctx_t scctx = adapter->shared; 1994 if_t ifp = iflib_get_ifp(ctx); 1995 struct igc_hw *hw = &adapter->hw; 1996 struct igc_rx_queue *que; 1997 int i; 1998 u32 psize, rctl, rxcsum, srrctl = 0; 1999 2000 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 2001 2002 /* 2003 * Make sure receives are disabled while setting 2004 * up the descriptor ring 2005 */ 2006 rctl = IGC_READ_REG(hw, IGC_RCTL); 2007 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2008 2009 /* Setup the Receive Control Register */ 2010 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2011 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2012 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2013 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2014 2015 /* Do not store bad packets */ 2016 rctl &= ~IGC_RCTL_SBP; 2017 2018 /* Enable Long Packet receive */ 2019 if (if_getmtu(ifp) > ETHERMTU) 2020 rctl |= IGC_RCTL_LPE; 2021 else 2022 rctl &= ~IGC_RCTL_LPE; 2023 2024 /* Strip the CRC */ 2025 if (!igc_disable_crc_stripping) 2026 rctl |= IGC_RCTL_SECRC; 2027 2028 /* 2029 * Set the interrupt throttling rate. Value is calculated 2030 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2031 */ 2032 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2033 2034 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2035 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2036 rxcsum |= IGC_RXCSUM_CRCOFL; 2037 if (adapter->tx_num_queues > 1) 2038 rxcsum |= IGC_RXCSUM_PCSD; 2039 else 2040 rxcsum |= IGC_RXCSUM_IPPCSE; 2041 } else { 2042 if (adapter->tx_num_queues > 1) 2043 rxcsum |= IGC_RXCSUM_PCSD; 2044 else 2045 rxcsum &= ~IGC_RXCSUM_TUOFL; 2046 } 2047 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2048 2049 if (adapter->rx_num_queues > 1) 2050 igc_initialize_rss_mapping(adapter); 2051 2052 if (if_getmtu(ifp) > ETHERMTU) { 2053 /* Set maximum packet len */ 2054 if (adapter->rx_mbuf_sz <= 4096) { 2055 srrctl |= 4096 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2056 rctl |= IGC_RCTL_SZ_4096 | IGC_RCTL_BSEX; 2057 } else if (adapter->rx_mbuf_sz > 4096) { 2058 srrctl |= 8192 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2059 rctl |= IGC_RCTL_SZ_8192 | IGC_RCTL_BSEX; 2060 } 2061 psize = scctx->isc_max_frame_size; 2062 /* are we on a vlan? */ 2063 if (if_vlantrunkinuse(ifp)) 2064 psize += VLAN_TAG_SIZE; 2065 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 2066 } else { 2067 srrctl |= 2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2068 rctl |= IGC_RCTL_SZ_2048; 2069 } 2070 2071 /* 2072 * If TX flow control is disabled and there's >1 queue defined, 2073 * enable DROP. 2074 * 2075 * This drops frames rather than hanging the RX MAC for all queues. 2076 */ 2077 if ((adapter->rx_num_queues > 1) && 2078 (adapter->fc == igc_fc_none || 2079 adapter->fc == igc_fc_rx_pause)) { 2080 srrctl |= IGC_SRRCTL_DROP_EN; 2081 } 2082 2083 /* Setup the Base and Length of the Rx Descriptor Rings */ 2084 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2085 struct rx_ring *rxr = &que->rxr; 2086 u64 bus_addr = rxr->rx_paddr; 2087 u32 rxdctl; 2088 2089 #ifdef notyet 2090 /* Configure for header split? -- ignore for now */ 2091 rxr->hdr_split = igc_header_split; 2092 #else 2093 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2094 #endif 2095 2096 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2097 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2098 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2099 (uint32_t)(bus_addr >> 32)); 2100 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2101 (uint32_t)bus_addr); 2102 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2103 /* Setup the Head and Tail Descriptor Pointers */ 2104 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2105 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2106 /* Enable this Queue */ 2107 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2108 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2109 rxdctl &= 0xFFF00000; 2110 rxdctl |= IGC_RX_PTHRESH; 2111 rxdctl |= IGC_RX_HTHRESH << 8; 2112 rxdctl |= IGC_RX_WTHRESH << 16; 2113 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2114 } 2115 2116 /* Make sure VLAN Filters are off */ 2117 rctl &= ~IGC_RCTL_VFE; 2118 2119 /* Write out the settings */ 2120 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2121 2122 return; 2123 } 2124 2125 static void 2126 igc_setup_vlan_hw_support(if_ctx_t ctx) 2127 { 2128 struct igc_adapter *adapter = iflib_get_softc(ctx); 2129 struct igc_hw *hw = &adapter->hw; 2130 struct ifnet *ifp = iflib_get_ifp(ctx); 2131 u32 reg; 2132 2133 /* igc hardware doesn't seem to implement VFTA for HWFILTER */ 2134 2135 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2136 !igc_disable_crc_stripping) { 2137 reg = IGC_READ_REG(hw, IGC_CTRL); 2138 reg |= IGC_CTRL_VME; 2139 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2140 } else { 2141 reg = IGC_READ_REG(hw, IGC_CTRL); 2142 reg &= ~IGC_CTRL_VME; 2143 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2144 } 2145 } 2146 2147 static void 2148 igc_if_intr_enable(if_ctx_t ctx) 2149 { 2150 struct igc_adapter *adapter = iflib_get_softc(ctx); 2151 struct igc_hw *hw = &adapter->hw; 2152 u32 mask; 2153 2154 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2155 mask = (adapter->que_mask | adapter->link_mask); 2156 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2157 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2158 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2159 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2160 } else 2161 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2162 IGC_WRITE_FLUSH(hw); 2163 } 2164 2165 static void 2166 igc_if_intr_disable(if_ctx_t ctx) 2167 { 2168 struct igc_adapter *adapter = iflib_get_softc(ctx); 2169 struct igc_hw *hw = &adapter->hw; 2170 2171 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2172 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2173 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2174 } 2175 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2176 IGC_WRITE_FLUSH(hw); 2177 } 2178 2179 /* 2180 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2181 * For ASF and Pass Through versions of f/w this means 2182 * that the driver is loaded. For AMT version type f/w 2183 * this means that the network i/f is open. 2184 */ 2185 static void 2186 igc_get_hw_control(struct igc_adapter *adapter) 2187 { 2188 u32 ctrl_ext; 2189 2190 if (adapter->vf_ifp) 2191 return; 2192 2193 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2194 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2195 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2196 } 2197 2198 /* 2199 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2200 * For ASF and Pass Through versions of f/w this means that 2201 * the driver is no longer loaded. For AMT versions of the 2202 * f/w this means that the network i/f is closed. 2203 */ 2204 static void 2205 igc_release_hw_control(struct igc_adapter *adapter) 2206 { 2207 u32 ctrl_ext; 2208 2209 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2210 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2211 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2212 return; 2213 } 2214 2215 static int 2216 igc_is_valid_ether_addr(u8 *addr) 2217 { 2218 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2219 2220 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2221 return (false); 2222 } 2223 2224 return (true); 2225 } 2226 2227 /* 2228 ** Parse the interface capabilities with regard 2229 ** to both system management and wake-on-lan for 2230 ** later use. 2231 */ 2232 static void 2233 igc_get_wakeup(if_ctx_t ctx) 2234 { 2235 struct igc_adapter *adapter = iflib_get_softc(ctx); 2236 u16 eeprom_data = 0, apme_mask; 2237 2238 apme_mask = IGC_WUC_APME; 2239 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2240 2241 if (eeprom_data & apme_mask) 2242 adapter->wol = IGC_WUFC_LNKC; 2243 } 2244 2245 2246 /* 2247 * Enable PCI Wake On Lan capability 2248 */ 2249 static void 2250 igc_enable_wakeup(if_ctx_t ctx) 2251 { 2252 struct igc_adapter *adapter = iflib_get_softc(ctx); 2253 device_t dev = iflib_get_dev(ctx); 2254 if_t ifp = iflib_get_ifp(ctx); 2255 int error = 0; 2256 u32 pmc, ctrl, rctl; 2257 u16 status; 2258 2259 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2260 return; 2261 2262 /* 2263 * Determine type of Wakeup: note that wol 2264 * is set with all bits on by default. 2265 */ 2266 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2267 adapter->wol &= ~IGC_WUFC_MAG; 2268 2269 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2270 adapter->wol &= ~IGC_WUFC_EX; 2271 2272 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2273 adapter->wol &= ~IGC_WUFC_MC; 2274 else { 2275 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2276 rctl |= IGC_RCTL_MPE; 2277 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2278 } 2279 2280 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2281 goto pme; 2282 2283 /* Advertise the wakeup capability */ 2284 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2285 ctrl |= IGC_CTRL_ADVD3WUC; 2286 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2287 2288 /* Enable wakeup by the MAC */ 2289 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2290 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2291 2292 pme: 2293 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2294 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2295 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2296 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2297 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2298 2299 return; 2300 } 2301 2302 /********************************************************************** 2303 * 2304 * Update the board statistics counters. 2305 * 2306 **********************************************************************/ 2307 static void 2308 igc_update_stats_counters(struct igc_adapter *adapter) 2309 { 2310 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2311 2312 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2313 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2314 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2315 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2316 2317 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2318 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2319 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2320 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2321 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2322 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2323 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2324 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2325 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2326 /* 2327 * For watchdog management we need to know if we have been 2328 * paused during the last interval, so capture that here. 2329 */ 2330 if (adapter->stats.xoffrxc != prev_xoffrxc) 2331 adapter->shared->isc_pause_frames = 1; 2332 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2333 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2334 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2335 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2336 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2337 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2338 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2339 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2340 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2341 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2342 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2343 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2344 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2345 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2346 2347 /* For the 64-bit byte counters the low dword must be read first. */ 2348 /* Both registers clear on the read of the high dword */ 2349 2350 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2351 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2352 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2353 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2354 2355 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2356 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2357 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2358 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2359 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2360 2361 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2362 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2363 2364 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2365 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2366 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2367 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2368 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2369 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2370 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2371 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2372 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2373 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2374 2375 /* Interrupt Counts */ 2376 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2377 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2378 2379 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2380 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2381 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2382 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2383 } 2384 2385 static uint64_t 2386 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2387 { 2388 struct igc_adapter *adapter = iflib_get_softc(ctx); 2389 if_t ifp = iflib_get_ifp(ctx); 2390 2391 switch (cnt) { 2392 case IFCOUNTER_COLLISIONS: 2393 return (adapter->stats.colc); 2394 case IFCOUNTER_IERRORS: 2395 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2396 adapter->stats.crcerrs + adapter->stats.algnerrc + 2397 adapter->stats.ruc + adapter->stats.roc + 2398 adapter->stats.mpc + adapter->stats.htdpmc); 2399 case IFCOUNTER_OERRORS: 2400 return (adapter->stats.ecol + adapter->stats.latecol + 2401 adapter->watchdog_events); 2402 default: 2403 return (if_get_counter_default(ifp, cnt)); 2404 } 2405 } 2406 2407 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2408 * @ctx: iflib context 2409 * @event: event code to check 2410 * 2411 * Defaults to returning true for unknown events. 2412 * 2413 * @returns true if iflib needs to reinit the interface 2414 */ 2415 static bool 2416 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2417 { 2418 switch (event) { 2419 case IFLIB_RESTART_VLAN_CONFIG: 2420 return (false); 2421 default: 2422 return (true); 2423 } 2424 } 2425 2426 /* Export a single 32-bit register via a read-only sysctl. */ 2427 static int 2428 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2429 { 2430 struct igc_adapter *adapter; 2431 u_int val; 2432 2433 adapter = oidp->oid_arg1; 2434 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2435 return (sysctl_handle_int(oidp, &val, 0, req)); 2436 } 2437 2438 /* 2439 * Add sysctl variables, one per statistic, to the system. 2440 */ 2441 static void 2442 igc_add_hw_stats(struct igc_adapter *adapter) 2443 { 2444 device_t dev = iflib_get_dev(adapter->ctx); 2445 struct igc_tx_queue *tx_que = adapter->tx_queues; 2446 struct igc_rx_queue *rx_que = adapter->rx_queues; 2447 2448 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2449 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2450 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2451 struct igc_hw_stats *stats = &adapter->stats; 2452 2453 struct sysctl_oid *stat_node, *queue_node, *int_node; 2454 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2455 2456 #define QUEUE_NAME_LEN 32 2457 char namebuf[QUEUE_NAME_LEN]; 2458 2459 /* Driver Statistics */ 2460 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2461 CTLFLAG_RD, &adapter->dropped_pkts, 2462 "Driver dropped packets"); 2463 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2464 CTLFLAG_RD, &adapter->link_irq, 2465 "Link MSI-X IRQ Handled"); 2466 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2467 CTLFLAG_RD, &adapter->rx_overruns, 2468 "RX overruns"); 2469 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2470 CTLFLAG_RD, &adapter->watchdog_events, 2471 "Watchdog timeouts"); 2472 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2473 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2474 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2475 "Device Control Register"); 2476 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2477 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2478 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2479 "Receiver Control Register"); 2480 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2481 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2482 "Flow Control High Watermark"); 2483 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2484 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2485 "Flow Control Low Watermark"); 2486 2487 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2488 struct tx_ring *txr = &tx_que->txr; 2489 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2490 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2491 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2492 queue_list = SYSCTL_CHILDREN(queue_node); 2493 2494 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2495 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2496 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2497 "Transmit Descriptor Head"); 2498 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2499 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2500 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2501 "Transmit Descriptor Tail"); 2502 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2503 CTLFLAG_RD, &txr->tx_irq, 2504 "Queue MSI-X Transmit Interrupts"); 2505 } 2506 2507 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2508 struct rx_ring *rxr = &rx_que->rxr; 2509 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2510 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2511 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2512 queue_list = SYSCTL_CHILDREN(queue_node); 2513 2514 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2515 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2516 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2517 "Receive Descriptor Head"); 2518 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2519 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2520 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2521 "Receive Descriptor Tail"); 2522 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2523 CTLFLAG_RD, &rxr->rx_irq, 2524 "Queue MSI-X Receive Interrupts"); 2525 } 2526 2527 /* MAC stats get their own sub node */ 2528 2529 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2530 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2531 stat_list = SYSCTL_CHILDREN(stat_node); 2532 2533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2534 CTLFLAG_RD, &stats->ecol, 2535 "Excessive collisions"); 2536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2537 CTLFLAG_RD, &stats->scc, 2538 "Single collisions"); 2539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2540 CTLFLAG_RD, &stats->mcc, 2541 "Multiple collisions"); 2542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2543 CTLFLAG_RD, &stats->latecol, 2544 "Late collisions"); 2545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2546 CTLFLAG_RD, &stats->colc, 2547 "Collision Count"); 2548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2549 CTLFLAG_RD, &adapter->stats.symerrs, 2550 "Symbol Errors"); 2551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2552 CTLFLAG_RD, &adapter->stats.sec, 2553 "Sequence Errors"); 2554 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2555 CTLFLAG_RD, &adapter->stats.dc, 2556 "Defer Count"); 2557 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2558 CTLFLAG_RD, &adapter->stats.mpc, 2559 "Missed Packets"); 2560 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2561 CTLFLAG_RD, &adapter->stats.rnbc, 2562 "Receive No Buffers"); 2563 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2564 CTLFLAG_RD, &adapter->stats.ruc, 2565 "Receive Undersize"); 2566 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2567 CTLFLAG_RD, &adapter->stats.rfc, 2568 "Fragmented Packets Received "); 2569 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2570 CTLFLAG_RD, &adapter->stats.roc, 2571 "Oversized Packets Received"); 2572 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2573 CTLFLAG_RD, &adapter->stats.rjc, 2574 "Recevied Jabber"); 2575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2576 CTLFLAG_RD, &adapter->stats.rxerrc, 2577 "Receive Errors"); 2578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2579 CTLFLAG_RD, &adapter->stats.crcerrs, 2580 "CRC errors"); 2581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2582 CTLFLAG_RD, &adapter->stats.algnerrc, 2583 "Alignment Errors"); 2584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2585 CTLFLAG_RD, &adapter->stats.xonrxc, 2586 "XON Received"); 2587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2588 CTLFLAG_RD, &adapter->stats.xontxc, 2589 "XON Transmitted"); 2590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2591 CTLFLAG_RD, &adapter->stats.xoffrxc, 2592 "XOFF Received"); 2593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2594 CTLFLAG_RD, &adapter->stats.xofftxc, 2595 "XOFF Transmitted"); 2596 2597 /* Packet Reception Stats */ 2598 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2599 CTLFLAG_RD, &adapter->stats.tpr, 2600 "Total Packets Received "); 2601 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2602 CTLFLAG_RD, &adapter->stats.gprc, 2603 "Good Packets Received"); 2604 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2605 CTLFLAG_RD, &adapter->stats.bprc, 2606 "Broadcast Packets Received"); 2607 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2608 CTLFLAG_RD, &adapter->stats.mprc, 2609 "Multicast Packets Received"); 2610 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2611 CTLFLAG_RD, &adapter->stats.prc64, 2612 "64 byte frames received "); 2613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2614 CTLFLAG_RD, &adapter->stats.prc127, 2615 "65-127 byte frames received"); 2616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2617 CTLFLAG_RD, &adapter->stats.prc255, 2618 "128-255 byte frames received"); 2619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2620 CTLFLAG_RD, &adapter->stats.prc511, 2621 "256-511 byte frames received"); 2622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2623 CTLFLAG_RD, &adapter->stats.prc1023, 2624 "512-1023 byte frames received"); 2625 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2626 CTLFLAG_RD, &adapter->stats.prc1522, 2627 "1023-1522 byte frames received"); 2628 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2629 CTLFLAG_RD, &adapter->stats.gorc, 2630 "Good Octets Received"); 2631 2632 /* Packet Transmission Stats */ 2633 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2634 CTLFLAG_RD, &adapter->stats.gotc, 2635 "Good Octets Transmitted"); 2636 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2637 CTLFLAG_RD, &adapter->stats.tpt, 2638 "Total Packets Transmitted"); 2639 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2640 CTLFLAG_RD, &adapter->stats.gptc, 2641 "Good Packets Transmitted"); 2642 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2643 CTLFLAG_RD, &adapter->stats.bptc, 2644 "Broadcast Packets Transmitted"); 2645 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2646 CTLFLAG_RD, &adapter->stats.mptc, 2647 "Multicast Packets Transmitted"); 2648 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2649 CTLFLAG_RD, &adapter->stats.ptc64, 2650 "64 byte frames transmitted "); 2651 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2652 CTLFLAG_RD, &adapter->stats.ptc127, 2653 "65-127 byte frames transmitted"); 2654 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2655 CTLFLAG_RD, &adapter->stats.ptc255, 2656 "128-255 byte frames transmitted"); 2657 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2658 CTLFLAG_RD, &adapter->stats.ptc511, 2659 "256-511 byte frames transmitted"); 2660 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2661 CTLFLAG_RD, &adapter->stats.ptc1023, 2662 "512-1023 byte frames transmitted"); 2663 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2664 CTLFLAG_RD, &adapter->stats.ptc1522, 2665 "1024-1522 byte frames transmitted"); 2666 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2667 CTLFLAG_RD, &adapter->stats.tsctc, 2668 "TSO Contexts Transmitted"); 2669 2670 /* Interrupt Stats */ 2671 2672 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2673 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2674 int_list = SYSCTL_CHILDREN(int_node); 2675 2676 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2677 CTLFLAG_RD, &adapter->stats.iac, 2678 "Interrupt Assertion Count"); 2679 2680 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2681 CTLFLAG_RD, &adapter->stats.rxdmtc, 2682 "Rx Desc Min Thresh Count"); 2683 } 2684 2685 /********************************************************************** 2686 * 2687 * This routine provides a way to dump out the adapter eeprom, 2688 * often a useful debug/service tool. This only dumps the first 2689 * 32 words, stuff that matters is in that extent. 2690 * 2691 **********************************************************************/ 2692 static int 2693 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2694 { 2695 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2696 int error; 2697 int result; 2698 2699 result = -1; 2700 error = sysctl_handle_int(oidp, &result, 0, req); 2701 2702 if (error || !req->newptr) 2703 return (error); 2704 2705 /* 2706 * This value will cause a hex dump of the 2707 * first 32 16-bit words of the EEPROM to 2708 * the screen. 2709 */ 2710 if (result == 1) 2711 igc_print_nvm_info(adapter); 2712 2713 return (error); 2714 } 2715 2716 static void 2717 igc_print_nvm_info(struct igc_adapter *adapter) 2718 { 2719 u16 eeprom_data; 2720 int i, j, row = 0; 2721 2722 /* Its a bit crude, but it gets the job done */ 2723 printf("\nInterface EEPROM Dump:\n"); 2724 printf("Offset\n0x0000 "); 2725 for (i = 0, j = 0; i < 32; i++, j++) { 2726 if (j == 8) { /* Make the offset block */ 2727 j = 0; ++row; 2728 printf("\n0x00%x0 ",row); 2729 } 2730 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2731 printf("%04x ", eeprom_data); 2732 } 2733 printf("\n"); 2734 } 2735 2736 static int 2737 igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 2738 { 2739 struct igc_int_delay_info *info; 2740 struct igc_adapter *adapter; 2741 u32 regval; 2742 int error, usecs, ticks; 2743 2744 info = (struct igc_int_delay_info *) arg1; 2745 usecs = info->value; 2746 error = sysctl_handle_int(oidp, &usecs, 0, req); 2747 if (error != 0 || req->newptr == NULL) 2748 return (error); 2749 if (usecs < 0 || usecs > IGC_TICKS_TO_USECS(65535)) 2750 return (EINVAL); 2751 info->value = usecs; 2752 ticks = IGC_USECS_TO_TICKS(usecs); 2753 if (info->offset == IGC_ITR) /* units are 256ns here */ 2754 ticks *= 4; 2755 2756 adapter = info->adapter; 2757 2758 regval = IGC_READ_OFFSET(&adapter->hw, info->offset); 2759 regval = (regval & ~0xffff) | (ticks & 0xffff); 2760 /* Handle a few special cases. */ 2761 switch (info->offset) { 2762 case IGC_RDTR: 2763 break; 2764 case IGC_TIDV: 2765 if (ticks == 0) { 2766 adapter->txd_cmd &= ~IGC_TXD_CMD_IDE; 2767 /* Don't write 0 into the TIDV register. */ 2768 regval++; 2769 } else 2770 adapter->txd_cmd |= IGC_TXD_CMD_IDE; 2771 break; 2772 } 2773 IGC_WRITE_OFFSET(&adapter->hw, info->offset, regval); 2774 return (0); 2775 } 2776 2777 static void 2778 igc_add_int_delay_sysctl(struct igc_adapter *adapter, const char *name, 2779 const char *description, struct igc_int_delay_info *info, 2780 int offset, int value) 2781 { 2782 info->adapter = adapter; 2783 info->offset = offset; 2784 info->value = value; 2785 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 2786 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 2787 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2788 info, 0, igc_sysctl_int_delay, "I", description); 2789 } 2790 2791 /* 2792 * Set flow control using sysctl: 2793 * Flow control values: 2794 * 0 - off 2795 * 1 - rx pause 2796 * 2 - tx pause 2797 * 3 - full 2798 */ 2799 static int 2800 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2801 { 2802 int error; 2803 static int input = 3; /* default is full */ 2804 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2805 2806 error = sysctl_handle_int(oidp, &input, 0, req); 2807 2808 if ((error) || (req->newptr == NULL)) 2809 return (error); 2810 2811 if (input == adapter->fc) /* no change? */ 2812 return (error); 2813 2814 switch (input) { 2815 case igc_fc_rx_pause: 2816 case igc_fc_tx_pause: 2817 case igc_fc_full: 2818 case igc_fc_none: 2819 adapter->hw.fc.requested_mode = input; 2820 adapter->fc = input; 2821 break; 2822 default: 2823 /* Do nothing */ 2824 return (error); 2825 } 2826 2827 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2828 igc_force_mac_fc(&adapter->hw); 2829 return (error); 2830 } 2831 2832 /* 2833 * Manage Energy Efficient Ethernet: 2834 * Control values: 2835 * 0/1 - enabled/disabled 2836 */ 2837 static int 2838 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2839 { 2840 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2841 int error, value; 2842 2843 value = adapter->hw.dev_spec._i225.eee_disable; 2844 error = sysctl_handle_int(oidp, &value, 0, req); 2845 if (error || req->newptr == NULL) 2846 return (error); 2847 2848 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2849 igc_if_init(adapter->ctx); 2850 2851 return (0); 2852 } 2853 2854 static int 2855 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2856 { 2857 struct igc_adapter *adapter; 2858 int error; 2859 int result; 2860 2861 result = -1; 2862 error = sysctl_handle_int(oidp, &result, 0, req); 2863 2864 if (error || !req->newptr) 2865 return (error); 2866 2867 if (result == 1) { 2868 adapter = (struct igc_adapter *) arg1; 2869 igc_print_debug_info(adapter); 2870 } 2871 2872 return (error); 2873 } 2874 2875 static int 2876 igc_get_rs(SYSCTL_HANDLER_ARGS) 2877 { 2878 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2879 int error; 2880 int result; 2881 2882 result = 0; 2883 error = sysctl_handle_int(oidp, &result, 0, req); 2884 2885 if (error || !req->newptr || result != 1) 2886 return (error); 2887 igc_dump_rs(adapter); 2888 2889 return (error); 2890 } 2891 2892 static void 2893 igc_if_debug(if_ctx_t ctx) 2894 { 2895 igc_dump_rs(iflib_get_softc(ctx)); 2896 } 2897 2898 /* 2899 * This routine is meant to be fluid, add whatever is 2900 * needed for debugging a problem. -jfv 2901 */ 2902 static void 2903 igc_print_debug_info(struct igc_adapter *adapter) 2904 { 2905 device_t dev = iflib_get_dev(adapter->ctx); 2906 if_t ifp = iflib_get_ifp(adapter->ctx); 2907 struct tx_ring *txr = &adapter->tx_queues->txr; 2908 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2909 2910 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2911 printf("Interface is RUNNING "); 2912 else 2913 printf("Interface is NOT RUNNING\n"); 2914 2915 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2916 printf("and INACTIVE\n"); 2917 else 2918 printf("and ACTIVE\n"); 2919 2920 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2921 device_printf(dev, "TX Queue %d ------\n", i); 2922 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2923 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2924 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2925 2926 } 2927 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2928 device_printf(dev, "RX Queue %d ------\n", j); 2929 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2930 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2931 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2932 } 2933 }

Cache object: 598f088e887674c3db1cc8a6f675f32f

FreeBSD/Linux Kernel Cross Reference sys/dev/igc/if_igc.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/igc/if_igc.c