Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/igc/if_igc.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include "opt_ddb.h" 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_rss.h" 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #ifdef DDB 44 #include <sys/types.h> 45 #include <ddb/ddb.h> 46 #endif 47 #include <sys/buf_ring.h> 48 #include <sys/bus.h> 49 #include <sys/endian.h> 50 #include <sys/kernel.h> 51 #include <sys/kthread.h> 52 #include <sys/malloc.h> 53 #include <sys/mbuf.h> 54 #include <sys/module.h> 55 #include <sys/rman.h> 56 #include <sys/smp.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 #include <sys/taskqueue.h> 61 #include <sys/eventhandler.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 65 #include <net/bpf.h> 66 #include <net/ethernet.h> 67 #include <net/if.h> 68 #include <net/if_var.h> 69 #include <net/if_arp.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/iflib.h> 73 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <netinet/in_systm.h> 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #include <netinet/ip.h> 81 #include <netinet/ip6.h> 82 #include <netinet/tcp.h> 83 #include <netinet/udp.h> 84 85 #include <machine/in_cksum.h> 86 #include <dev/led/led.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcireg.h> 89 90 #include "igc_api.h" 91 #include "igc_i225.h" 92 #include "ifdi_if.h" 93 94 95 #ifndef _IGC_H_DEFINED_ 96 #define _IGC_H_DEFINED_ 97 98 99 /* Tunables */ 100 101 /* 102 * IGC_MAX_TXD: Maximum number of Transmit Descriptors 103 * Valid Range: 128-4096 104 * Default Value: 1024 105 * This value is the number of transmit descriptors allocated by the driver. 106 * Increasing this value allows the driver to queue more transmits. Each 107 * descriptor is 16 bytes. 108 * Since TDLEN should be multiple of 128bytes, the number of transmit 109 * desscriptors should meet the following condition. 110 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 111 */ 112 #define IGC_MIN_TXD 128 113 #define IGC_MAX_TXD 4096 114 #define IGC_DEFAULT_TXD 1024 115 #define IGC_DEFAULT_MULTI_TXD 4096 116 #define IGC_MAX_TXD 4096 117 118 /* 119 * IGC_MAX_RXD - Maximum number of receive Descriptors 120 * Valid Range: 128-4096 121 * Default Value: 1024 122 * This value is the number of receive descriptors allocated by the driver. 123 * Increasing this value allows the driver to buffer more incoming packets. 124 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 125 * descriptor. The maximum MTU size is 16110. 126 * Since TDLEN should be multiple of 128bytes, the number of transmit 127 * desscriptors should meet the following condition. 128 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 129 */ 130 #define IGC_MIN_RXD 128 131 #define IGC_MAX_RXD 4096 132 #define IGC_DEFAULT_RXD 1024 133 #define IGC_DEFAULT_MULTI_RXD 4096 134 #define IGC_MAX_RXD 4096 135 136 /* 137 * IGC_TIDV_VAL - Transmit Interrupt Delay Value 138 * Valid Range: 0-65535 (0=off) 139 * Default Value: 64 140 * This value delays the generation of transmit interrupts in units of 141 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 142 * efficiency if properly tuned for specific network traffic. If the 143 * system is reporting dropped transmits, this value may be set too high 144 * causing the driver to run out of available transmit descriptors. 145 */ 146 #define IGC_TIDV_VAL 64 147 148 /* 149 * IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value 150 * Valid Range: 0-65535 (0=off) 151 * Default Value: 64 152 * This value, in units of 1.024 microseconds, limits the delay in which a 153 * transmit interrupt is generated. Useful only if IGC_TIDV is non-zero, 154 * this value ensures that an interrupt is generated after the initial 155 * packet is sent on the wire within the set amount of time. Proper tuning, 156 * along with IGC_TIDV_VAL, may improve traffic throughput in specific 157 * network conditions. 158 */ 159 #define IGC_TADV_VAL 64 160 161 /* 162 * IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer) 163 * Valid Range: 0-65535 (0=off) 164 * Default Value: 0 165 * This value delays the generation of receive interrupts in units of 1.024 166 * microseconds. Receive interrupt reduction can improve CPU efficiency if 167 * properly tuned for specific network traffic. Increasing this value adds 168 * extra latency to frame reception and can end up decreasing the throughput 169 * of TCP traffic. If the system is reporting dropped receives, this value 170 * may be set too high, causing the driver to run out of available receive 171 * descriptors. 172 * 173 * CAUTION: When setting IGC_RDTR to a value other than 0, adapters 174 * may hang (stop transmitting) under certain network conditions. 175 * If this occurs a WATCHDOG message is logged in the system 176 * event log. In addition, the controller is automatically reset, 177 * restoring the network connection. To eliminate the potential 178 * for the hang ensure that IGC_RDTR is set to 0. 179 */ 180 #define IGC_RDTR_VAL 0 181 182 /* 183 * Receive Interrupt Absolute Delay Timer 184 * Valid Range: 0-65535 (0=off) 185 * Default Value: 64 186 * This value, in units of 1.024 microseconds, limits the delay in which a 187 * receive interrupt is generated. Useful only if IGC_RDTR is non-zero, 188 * this value ensures that an interrupt is generated after the initial 189 * packet is received within the set amount of time. Proper tuning, 190 * along with IGC_RDTR, may improve traffic throughput in specific network 191 * conditions. 192 */ 193 #define IGC_RADV_VAL 64 194 195 /* 196 * This parameter controls whether or not autonegotation is enabled. 197 * 0 - Disable autonegotiation 198 * 1 - Enable autonegotiation 199 */ 200 #define DO_AUTO_NEG true 201 202 /* Tunables -- End */ 203 204 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 205 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 206 ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 207 208 #define AUTO_ALL_MODES 0 209 210 /* 211 * Micellaneous constants 212 */ 213 #define MAX_NUM_MULTICAST_ADDRESSES 128 214 #define IGC_FC_PAUSE_TIME 0x0680 215 216 #define IGC_TXPBSIZE 20408 217 #define IGC_PKTTYPE_MASK 0x0000FFF0 218 #define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 219 220 #define IGC_RX_PTHRESH 8 221 #define IGC_RX_HTHRESH 8 222 #define IGC_RX_WTHRESH 4 223 224 #define IGC_TX_PTHRESH 8 225 #define IGC_TX_HTHRESH 1 226 227 /* 228 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 229 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 230 * also optimize cache line size effect. H/W supports up to cache line size 128. 231 */ 232 #define IGC_DBA_ALIGN 128 233 234 #define IGC_MSIX_BAR 3 235 236 /* Defines for printing debug information */ 237 #define DEBUG_INIT 0 238 #define DEBUG_IOCTL 0 239 #define DEBUG_HW 0 240 241 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 242 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 243 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 244 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 245 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 246 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 247 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 248 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 249 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 250 251 #define IGC_MAX_SCATTER 40 252 #define IGC_VFTA_SIZE 128 253 #define IGC_TSO_SIZE 65535 254 #define IGC_TSO_SEG_SIZE 4096 /* Max dma segment size */ 255 #define IGC_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 256 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 257 CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ 258 259 struct igc_adapter; 260 261 struct igc_int_delay_info { 262 struct igc_adapter *adapter; /* Back-pointer to the adapter struct */ 263 int offset; /* Register offset to read/write */ 264 int value; /* Current value in usecs */ 265 }; 266 267 /* 268 * The transmit ring, one per tx queue 269 */ 270 struct tx_ring { 271 struct igc_adapter *adapter; 272 struct igc_tx_desc *tx_base; 273 uint64_t tx_paddr; 274 qidx_t *tx_rsq; 275 uint8_t me; 276 qidx_t tx_rs_cidx; 277 qidx_t tx_rs_pidx; 278 qidx_t tx_cidx_processed; 279 /* Interrupt resources */ 280 void *tag; 281 struct resource *res; 282 unsigned long tx_irq; 283 284 /* Saved csum offloading context information */ 285 int csum_flags; 286 int csum_lhlen; 287 int csum_iphlen; 288 289 int csum_thlen; 290 int csum_mss; 291 int csum_pktlen; 292 293 uint32_t csum_txd_upper; 294 uint32_t csum_txd_lower; /* last field */ 295 }; 296 297 /* 298 * The Receive ring, one per rx queue 299 */ 300 struct rx_ring { 301 struct igc_adapter *adapter; 302 struct igc_rx_queue *que; 303 u32 me; 304 u32 payload; 305 union igc_rx_desc_extended *rx_base; 306 uint64_t rx_paddr; 307 308 /* Interrupt resources */ 309 void *tag; 310 struct resource *res; 311 312 /* Soft stats */ 313 unsigned long rx_irq; 314 unsigned long rx_discarded; 315 unsigned long rx_packets; 316 unsigned long rx_bytes; 317 }; 318 319 struct igc_tx_queue { 320 struct igc_adapter *adapter; 321 u32 msix; 322 u32 eims; /* This queue's EIMS bit */ 323 u32 me; 324 struct tx_ring txr; 325 }; 326 327 struct igc_rx_queue { 328 struct igc_adapter *adapter; 329 u32 me; 330 u32 msix; 331 u32 eims; 332 struct rx_ring rxr; 333 u64 irqs; 334 struct if_irq que_irq; 335 }; 336 337 /* Our adapter structure */ 338 struct igc_adapter { 339 if_t ifp; 340 struct igc_hw hw; 341 342 if_softc_ctx_t shared; 343 if_ctx_t ctx; 344 #define tx_num_queues shared->isc_ntxqsets 345 #define rx_num_queues shared->isc_nrxqsets 346 #define intr_type shared->isc_intr 347 /* FreeBSD operating-system-specific structures. */ 348 struct igc_osdep osdep; 349 device_t dev; 350 struct cdev *led_dev; 351 352 struct igc_tx_queue *tx_queues; 353 struct igc_rx_queue *rx_queues; 354 struct if_irq irq; 355 356 struct resource *memory; 357 struct resource *flash; 358 struct resource *ioport; 359 360 struct resource *res; 361 void *tag; 362 u32 linkvec; 363 u32 ivars; 364 365 struct ifmedia *media; 366 int msix; 367 int if_flags; 368 int igc_insert_vlan_header; 369 u32 ims; 370 371 u32 flags; 372 /* Task for FAST handling */ 373 struct grouptask link_task; 374 375 u32 txd_cmd; 376 377 u32 tx_process_limit; 378 u32 rx_process_limit; 379 u32 rx_mbuf_sz; 380 381 /* Management and WOL features */ 382 u32 wol; 383 384 /* Multicast array memory */ 385 u8 *mta; 386 387 /* Info about the interface */ 388 u16 link_active; 389 u16 fc; 390 u16 link_speed; 391 u16 link_duplex; 392 u32 smartspeed; 393 u32 dmac; 394 int link_mask; 395 396 u64 que_mask; 397 398 struct igc_int_delay_info tx_int_delay; 399 struct igc_int_delay_info tx_abs_int_delay; 400 struct igc_int_delay_info rx_int_delay; 401 struct igc_int_delay_info rx_abs_int_delay; 402 struct igc_int_delay_info tx_itr; 403 404 /* Misc stats maintained by the driver */ 405 unsigned long dropped_pkts; 406 unsigned long link_irq; 407 unsigned long rx_overruns; 408 unsigned long watchdog_events; 409 410 struct igc_hw_stats stats; 411 u16 vf_ifp; 412 }; 413 414 void igc_dump_rs(struct igc_adapter *); 415 416 #define IGC_RSSRK_SIZE 4 417 #define IGC_RSSRK_VAL(key, i) (key[(i) * IGC_RSSRK_SIZE] | \ 418 key[(i) * IGC_RSSRK_SIZE + 1] << 8 | \ 419 key[(i) * IGC_RSSRK_SIZE + 2] << 16 | \ 420 key[(i) * IGC_RSSRK_SIZE + 3] << 24) 421 #endif /* _IGC_H_DEFINED_ */
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