The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/iicbus/iicoc.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2003-2012 Broadcom Corporation
    5  * All Rights Reserved
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in
   15  *    the documentation and/or other materials provided with the
   16  *    distribution.
   17  * 
   18  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   20  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   25  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   26  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
   27  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
   28  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   29  *
   30  * $FreeBSD$
   31  */
   32 
   33 #ifndef __OPENCORE_I2C_H__
   34 #define __OPENCORE_I2C_H__
   35 
   36 /* I2C specific registers */
   37 #define OC_I2C_PRESCALE_LO_REG          0x00
   38 #define OC_I2C_PRESCALE_HI_REG          0x01
   39 #define OC_I2C_CTRL_REG                 0x02
   40 #define OC_I2C_TRANSMIT_REG             0x03  /* tx and rx - same reg */
   41 #define OC_I2C_RECV_REG                 0x03  /* tx and rx - same reg */
   42 #define OC_I2C_DATA_REG                 0x03  /* tx and rx - same reg */
   43 #define OC_I2C_CMD_REG                  0x04  /* cmd and status - same reg */
   44 #define OC_I2C_STATUS_REG               0x04  /* cmd and status - same reg */
   45 
   46 #define XLP_I2C_CLKFREQ                 133333333 /* XLP 133 MHz IO clock */
   47 #define XLP_I2C_FREQ                    100000  /* default 100kHz */
   48 #define I2C_TIMEOUT                     500000
   49 
   50 /*
   51  * These defines pertain to the OpenCores
   52  * I2C Master Host Controller used in XLP
   53  */
   54 
   55 #define OC_PRESCALER_LO                 0
   56 #define OC_PRESCALER_HI                 1
   57 
   58 #define OC_CONTROL                      2
   59 #define OC_CONTROL_EN                   0x80
   60 #define OC_CONTROL_IEN                  0x40
   61 
   62 #define OC_DATA                         3       /* Data TX & RX Reg */
   63 
   64 #define OC_COMMAND                      4
   65 #define OC_COMMAND_START                0x90
   66 #define OC_COMMAND_STOP                 0x40
   67 #define OC_COMMAND_READ                 0x20
   68 #define OC_COMMAND_WRITE                0x10
   69 #define OC_COMMAND_RDACK                0x20
   70 #define OC_COMMAND_RDNACK               0x28
   71 #define OC_COMMAND_IACK                 0x01    /* Not used */
   72 
   73 #define OC_STATUS                       4       /* Same as 'command' */
   74 #define OC_STATUS_NACK                  0x80    /* Did not get an ACK */
   75 #define OC_STATUS_BUSY                  0x40
   76 #define OC_STATUS_AL                    0x20    /* Arbitration Lost */
   77 #define OC_STATUS_TIP                   0x02    /* Transfer in Progress  */
   78 #define OC_STATUS_IF                    0x01    /* Intr. Pending Flag */
   79 
   80 struct iicoc_softc {
   81         device_t        dev;            /* Self */
   82         u_int           reg_shift;      /* Chip specific */
   83         u_int           clockfreq;
   84         u_int           i2cfreq;
   85         struct resource *mem_res;       /* Memory resource */
   86         int             mem_rid;
   87         int             sc_started;
   88         uint8_t         i2cdev_addr;
   89         device_t        iicbus;
   90         struct mtx      sc_mtx;
   91 };
   92 
   93 #endif
   94 
   95 int iicoc_iicbus_start(device_t dev, u_char slave, int timeout);
   96 int iicoc_iicbus_stop(device_t dev);
   97 int iicoc_iicbus_read(device_t dev, char *buf, int len, int *read, int last,
   98     int delay);
   99 int iicoc_iicbus_write(device_t dev, const char *buf, int len, int *sent,
  100     int timeout);
  101 int iicoc_iicbus_repeated_start(device_t dev, u_char slave, int timeout);
  102 int iicoc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr);
  103 
  104 int iicoc_init(device_t dev);

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