FreeBSD/Linux Kernel Cross Reference
sys/dev/iir/iir.h
1 /* $FreeBSD: releng/5.4/sys/dev/iir/iir.h 141016 2005-01-30 01:00:13Z imp $ */
2 /*-
3 * Copyright (c) 2000-04 ICP vortex GmbH
4 * Copyright (c) 2002-04 Intel Corporation
5 * Copyright (c) 2003-04 Adaptec Inc.
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33
34 /*
35 *
36 * iir.h: Definitions/Constants used by the Intel Integrated RAID driver
37 *
38 * Written by: Achim Leubner <achim_leubner@adaptec.com>
39 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
40 *
41 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
42 * FreeBSD.ORG; Great O/S to work on and for.
43 *
44 * $Id: iir.h 1.6 2004/03/30 10:19:44 achim Exp $"
45 */
46
47 #ifndef _IIR_H
48 #define _IIR_H
49
50 #define IIR_DRIVER_VERSION 1
51 #define IIR_DRIVER_SUBVERSION 5
52
53 /* OEM IDs */
54 #define OEM_ID_ICP 0x941c
55 #define OEM_ID_INTEL 0x8000
56
57 #define GDT_VENDOR_ID 0x1119
58 #define GDT_DEVICE_ID_MIN 0x100
59 #define GDT_DEVICE_ID_MAX 0x2ff
60 #define GDT_DEVICE_ID_NEWRX 0x300
61
62 #define INTEL_VENDOR_ID 0x8086
63 #define INTEL_DEVICE_ID_IIR 0x600
64
65 #define GDT_MAXBUS 6 /* XXX Why not 5? */
66 #define GDT_MAX_HDRIVES 100 /* max 100 host drives */
67 #define GDT_MAXID_FC 127 /* Fibre-channel IDs */
68 #define GDT_MAXID 16 /* SCSI IDs */
69 #define GDT_MAXOFFSETS 128
70 #define GDT_MAXSG 32 /* Max. s/g elements */
71 #define GDT_PROTOCOL_VERSION 1
72 #define GDT_LINUX_OS 8 /* Used for cache optimization */
73 #define GDT_SCATTER_GATHER 1 /* s/g feature */
74 #define GDT_SECS32 0x1f /* round capacity */
75 #define GDT_LOCALBOARD 0 /* Board node always 0 */
76 #define GDT_MAXCMDS 124
77 #define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
78 #define GDT_MAX_EVENTS 0x100 /* event buffer */
79
80 /* DPMEM constants */
81 #define GDT_MPR_MAGIC 0xc0ffee11
82 #define GDT_IC_HEADER_BYTES 48
83 #define GDT_IC_QUEUE_BYTES 4
84 #define GDT_DPMEM_COMMAND_OFFSET \
85 (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
86
87 /* geometry constants */
88 #define GDT_MAXCYLS 1024
89 #define GDT_HEADS 64
90 #define GDT_SECS 32 /* mapping 64*32 */
91 #define GDT_MEDHEADS 127
92 #define GDT_MEDSECS 63 /* mapping 127*63 */
93 #define GDT_BIGHEADS 255
94 #define GDT_BIGSECS 63 /* mapping 255*63 */
95
96 /* data direction raw service */
97 #define GDT_DATA_IN 0x01000000L
98 #define GDT_DATA_OUT 0x00000000L
99
100 /* Cache/raw service commands */
101 #define GDT_INIT 0 /* service initialization */
102 #define GDT_READ 1 /* read command */
103 #define GDT_WRITE 2 /* write command */
104 #define GDT_INFO 3 /* information about devices */
105 #define GDT_FLUSH 4 /* flush dirty cache buffers */
106 #define GDT_IOCTL 5 /* ioctl command */
107 #define GDT_DEVTYPE 9 /* additional information */
108 #define GDT_MOUNT 10 /* mount cache device */
109 #define GDT_UNMOUNT 11 /* unmount cache device */
110 #define GDT_SET_FEAT 12 /* set features (scatter/gather) */
111 #define GDT_GET_FEAT 13 /* get features */
112 #define GDT_WRITE_THR 16 /* write through */
113 #define GDT_READ_THR 17 /* read through */
114 #define GDT_EXT_INFO 18 /* extended info */
115 #define GDT_RESET 19 /* controller reset */
116 #define GDT_FREEZE_IO 25 /* freeze all IOs */
117 #define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
118
119 /* Additional raw service commands */
120 #define GDT_RESERVE 14 /* reserve device to raw service */
121 #define GDT_RELEASE 15 /* release device */
122 #define GDT_RESERVE_ALL 16 /* reserve all devices */
123 #define GDT_RELEASE_ALL 17 /* release all devices */
124 #define GDT_RESET_BUS 18 /* reset bus */
125 #define GDT_SCAN_START 19 /* start device scan */
126 #define GDT_SCAN_END 20 /* stop device scan */
127
128 /* IOCTL command defines */
129 #define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
130 #define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
131 #define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
132 #define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
133 #define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
134 #define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
135 #define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
136
137 #define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
138 #define GDT_ARRAY_INFO 0x12 /* array drive info */
139 #define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
140 #define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
141 #define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
142 #define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
143 #define GDT_CACHE_INFO 0x04 /* cache info */
144 #define GDT_CACHE_CONFIG 0x05 /* cache configuration */
145 #define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
146 #define GDT_BOARD_FEATURES 0x15 /* controller features */
147 #define GDT_BOARD_INFO 0x28 /* controller info */
148 #define GDT_OEM_STR_RECORD 0x84 /* OEM info */
149 #define GDT_HOST_GET 0x10001 /* get host drive list */
150 #define GDT_IO_CHANNEL 0x20000 /* default IO channel */
151 #define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
152
153 /* IOCTLs */
154 #define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
155 #define GDT_IOCTL_DRVERS _IOR('J', 1, int) /* get driver version */
156 #define GDT_IOCTL_CTRTYPE _IOWR('J', 2, gdt_ctrt_t) /* get ctr. type */
157 #define GDT_IOCTL_DRVERS_OLD _IOWR('J', 1, int) /* get driver version */
158 #define GDT_IOCTL_CTRTYPE_OLD _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
159 #define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
160 #define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
161 #define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
162 #define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
163
164 /* Service errors */
165 #define GDT_S_OK 1 /* no error */
166 #define GDT_S_BSY 7 /* controller busy */
167 #define GDT_S_RAW_SCSI 12 /* raw service: target error */
168 #define GDT_S_RAW_ILL 0xff /* raw service: illegal */
169 #define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
170
171 /* Controller services */
172 #define GDT_SCSIRAWSERVICE 3
173 #define GDT_CACHESERVICE 9
174 #define GDT_SCREENSERVICE 11
175
176 /* Scatter/gather element */
177 #define GDT_SG_PTR 0x00 /* u_int32_t, address */
178 #define GDT_SG_LEN 0x04 /* u_int32_t, length */
179 #define GDT_SG_SZ 0x08
180
181 /* Cache service command */
182 #define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
183 #define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
184 #define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
185 #define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
186 #define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
187 #define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
188 #define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
189
190 /* Ioctl command */
191 #define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
192 #define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
193 #define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
194 #define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
195 #define GDT_IOCTL_SZ 0x0e
196
197 /* Screen service defines */
198 #define GDT_MSG_INV_HANDLE -1 /* special message handle */
199 #define GDT_MSGLEN 16 /* size of message text */
200 #define GDT_MSG_SIZE 34 /* size of message structure */
201 #define GDT_MSG_REQUEST 0 /* async. event. message */
202
203 /* Screen service command */
204 #define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
205 #define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
206 #define GDT_SCREEN_SZ 0x0a
207
208 /* Screen service message */
209 #define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
210 #define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
211 #define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
212 #define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
213 #define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
214 #define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
215 #define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
216 #define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
217
218 /* Raw service command */
219 #define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
220 #define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
221 #define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
222 #define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
223 #define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
224 #define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
225 #define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
226 #define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
227 #define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
228 #define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
229 #define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
230 #define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
231 #define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
232 #define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
233 #define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
234 #define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
235
236 /* Command structure */
237 #define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
238 #define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
239 #define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
240 #define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
241 #define GDT_CMD_UNION_SZ GDT_RAW_SZ
242 #define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
243
244 /* Command queue entries */
245 #define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
246 #define GDT_SERV_ID 0x02 /* u_int16_t, service */
247 #define GDT_COMM_Q_SZ 0x04
248
249 /* Interface area */
250 #define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
251 #define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
252 #define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
253 #define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
254 #define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
255 #define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
256 #define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
257 #define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
258 #define GDT_COMM_QUEUE 0x28 /* command queue */
259 #define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
260 /* u_int8_t [], commands */
261
262 /* I/O channel header */
263 #define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
264 #define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
265 #define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
266 #define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
267 #define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
268 #define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
269 #define GDT_IOC_HDR_SZ 0x0c
270
271 #define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
272
273 /* Get I/O channel description */
274 #define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
275 #define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
276 #define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
277 #define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
278 #define GDT_IOC_SZ 0x08
279
280 /* Get raw I/O channel description */
281 #define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
282 #define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
283 #define GDT_RAWIOC_SZ 0x04
284
285 /* Get SCSI channel count */
286 #define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
287 #define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
288 #define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
289 #define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
290 #define GDT_GETCH_SZ 0x0a
291
292 /* Cache info/config IOCTL structures */
293 #define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
294 #define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
295 #define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
296 #define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
297 #define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
298 #define GDT_CPAR_SZ 0x0c
299
300 #define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
301 #define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
302 #define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
303 #define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
304 #define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
305 #define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
306 #define GDT_CSTAT_SZ 0x18
307
308 /* Get cache info */
309 #define GDT_CINFO_CPAR 0x00
310 #define GDT_CINFO_CSTAT GDT_CPAR_SZ
311 #define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
312
313 /* Get board info */
314 #define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
315 #define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
316 #define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
317 #define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
318 #define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
319 #define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
320 #define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
321 #define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
322 #define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
323 #define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
324 #define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
325 #define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
326 #define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
327 #define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
328 #define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
329 #define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
330 #define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
331 #define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
332 #define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
333 #define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
334 #define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
335 #define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
336 #define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
337 #define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
338 #define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
339 #define GDT_BINFO_SZ 0x54
340
341 /* Get board features */
342 #define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
343 #define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
344 #define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
345 #define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
346 #define GDT_BFEAT_SZ 0x04
347
348 /* Other defines */
349 #define GDT_ASYNCINDEX 0 /* command index asynchronous event */
350 #define GDT_SPEZINDEX 1 /* command index unknown service */
351
352 /* Debugging */
353 #ifdef GDT_DEBUG
354 #define GDT_D_INTR 0x01
355 #define GDT_D_MISC 0x02
356 #define GDT_D_CMD 0x04
357 #define GDT_D_QUEUE 0x08
358 #define GDT_D_TIMEOUT 0x10
359 #define GDT_D_INIT 0x20
360 #define GDT_D_INVALID 0x40
361 #define GDT_D_DEBUG 0x80
362 extern int gdt_debug;
363 #ifdef __SERIAL__
364 extern int ser_printf(const char *fmt, ...);
365 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
366 #else
367 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
368 #endif
369 #else
370 #define GDT_DPRINTF(mask, args)
371 #endif
372
373 /* Miscellaneous constants */
374 #define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
375 #define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
376 #define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
377 #define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
378 #define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
379
380 /* Map minor numbers to device identity */
381 #define LUN_MASK 0x0007
382 #define TARGET_MASK 0x03f8
383 #define BUS_MASK 0x1c00
384 #define HBA_MASK 0xe000
385
386 #define minor2lun(minor) ( minor & LUN_MASK )
387 #define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
388 #define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
389 #define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
390 #define hba2minor(hba) ( (hba << 13) & HBA_MASK )
391
392
393 /* struct for GDT_IOCTL_GENERAL */
394 #pragma pack(1)
395 typedef struct gdt_ucmd {
396 u_int16_t io_node;
397 u_int16_t service;
398 u_int32_t timeout;
399 u_int16_t status;
400 u_int32_t info;
401
402 u_int32_t BoardNode; /* board node (always 0) */
403 u_int32_t CommandIndex; /* command number */
404 u_int16_t OpCode; /* the command (READ,..) */
405 union {
406 struct {
407 u_int16_t DeviceNo; /* number of cache drive */
408 u_int32_t BlockNo; /* block number */
409 u_int32_t BlockCnt; /* block count */
410 void *DestAddr; /* data */
411 } cache; /* cache service cmd. str. */
412 struct {
413 u_int16_t param_size; /* size of p_param buffer */
414 u_int32_t subfunc; /* IOCTL function */
415 u_int32_t channel; /* device */
416 void *p_param; /* data */
417 } ioctl; /* IOCTL command structure */
418 struct {
419 u_int16_t reserved;
420 u_int32_t direction; /* data direction */
421 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
422 u_int32_t mcon_time; /* connect time(0: no to.) */
423 void *sdata; /* dest. addr. (if s/g: -1) */
424 u_int32_t sdlen; /* data length (bytes) */
425 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
426 u_int8_t cmd[12]; /* SCSI command */
427 u_int8_t target; /* target ID */
428 u_int8_t lun; /* LUN */
429 u_int8_t bus; /* SCSI bus number */
430 u_int8_t priority; /* only 0 used */
431 u_int32_t sense_len; /* sense data length */
432 void *sense_data; /* sense data addr. */
433 u_int32_t link_p; /* linked cmds (not supp.) */
434 } raw; /* raw service cmd. struct. */
435 } u;
436 u_int8_t data[GDT_SCRATCH_SZ];
437 int complete_flag;
438 TAILQ_ENTRY(gdt_ucmd) links;
439 } gdt_ucmd_t;
440
441 /* struct for GDT_IOCTL_CTRTYPE */
442 typedef struct gdt_ctrt {
443 u_int16_t io_node;
444 u_int16_t oem_id;
445 u_int16_t type;
446 u_int32_t info;
447 u_int8_t access;
448 u_int8_t remote;
449 u_int16_t ext_type;
450 u_int16_t device_id;
451 u_int16_t sub_device_id;
452 } gdt_ctrt_t;
453
454 /* struct for GDT_IOCTL_OSVERS */
455 typedef struct gdt_osv {
456 u_int8_t oscode;
457 u_int8_t version;
458 u_int8_t subversion;
459 u_int16_t revision;
460 char name[64];
461 } gdt_osv_t;
462
463 /* OEM */
464 #define GDT_OEM_VERSION 0x00
465 #define GDT_OEM_BUFSIZE 0x0c
466 typedef struct {
467 u_int32_t ctl_version;
468 u_int32_t file_major_version;
469 u_int32_t file_minor_version;
470 u_int32_t buffer_size;
471 u_int32_t cpy_count;
472 u_int32_t ext_error;
473 u_int32_t oem_id;
474 u_int32_t board_id;
475 } gdt_oem_param_t;
476
477 typedef struct {
478 char product_0_1_name[16];
479 char product_4_5_name[16];
480 char product_cluster_name[16];
481 char product_reserved[16];
482 char scsi_cluster_target_vendor_id[16];
483 char cluster_raid_fw_name[16];
484 char oem_brand_name[16];
485 char oem_raid_type[16];
486 char bios_type[13];
487 char bios_title[50];
488 char oem_company_name[37];
489 u_int32_t pci_id_1;
490 u_int32_t pci_id_2;
491 char validation_status[80];
492 char reserved_1[4];
493 char scsi_host_drive_inquiry_vendor_id[16];
494 char library_file_template[32];
495 char tool_name_1[32];
496 char tool_name_2[32];
497 char tool_name_3[32];
498 char oem_contact_1[84];
499 char oem_contact_2[84];
500 char oem_contact_3[84];
501 } gdt_oem_record_t;
502
503 typedef struct {
504 gdt_oem_param_t parameters;
505 gdt_oem_record_t text;
506 } gdt_oem_str_record_t;
507
508
509 /* controller event structure */
510 #define GDT_ES_ASYNC 1
511 #define GDT_ES_DRIVER 2
512 #define GDT_ES_TEST 3
513 #define GDT_ES_SYNC 4
514 typedef struct {
515 u_int16_t size; /* size of structure */
516 union {
517 char stream[16];
518 struct {
519 u_int16_t ionode;
520 u_int16_t service;
521 u_int32_t index;
522 } driver;
523 struct {
524 u_int16_t ionode;
525 u_int16_t service;
526 u_int16_t status;
527 u_int32_t info;
528 u_int8_t scsi_coord[3];
529 } async;
530 struct {
531 u_int16_t ionode;
532 u_int16_t service;
533 u_int16_t status;
534 u_int32_t info;
535 u_int16_t hostdrive;
536 u_int8_t scsi_coord[3];
537 u_int8_t sense_key;
538 } sync;
539 struct {
540 u_int32_t l1, l2, l3, l4;
541 } test;
542 } eu;
543 u_int32_t severity;
544 u_int8_t event_string[256];
545 } gdt_evt_data;
546
547 /* dvrevt structure */
548 typedef struct {
549 u_int32_t first_stamp;
550 u_int32_t last_stamp;
551 u_int16_t same_count;
552 u_int16_t event_source;
553 u_int16_t event_idx;
554 u_int8_t application;
555 u_int8_t reserved;
556 gdt_evt_data event_data;
557 } gdt_evt_str;
558
559 /* struct for GDT_IOCTL_EVENT */
560 typedef struct gdt_event {
561 int erase;
562 int handle;
563 gdt_evt_str dvr;
564 } gdt_event_t;
565
566 /* struct for GDT_IOCTL_STATIST */
567 typedef struct gdt_statist {
568 u_int16_t io_count_act;
569 u_int16_t io_count_max;
570 u_int16_t req_queue_act;
571 u_int16_t req_queue_max;
572 u_int16_t cmd_index_act;
573 u_int16_t cmd_index_max;
574 u_int16_t sg_count_act;
575 u_int16_t sg_count_max;
576 } gdt_statist_t;
577
578 #pragma pack()
579
580 /* Context structure for interrupt services */
581 struct gdt_intr_ctx {
582 u_int32_t info, info2;
583 u_int16_t cmd_status, service;
584 u_int8_t istatus;
585 };
586
587 /* softc structure */
588 struct gdt_softc {
589 int sc_hanum;
590 int sc_class; /* Controller class */
591 #define GDT_MPR 0x05
592 #define GDT_CLASS_MASK 0x07
593 #define GDT_FC 0x10
594 #define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
595 int sc_bus, sc_slot;
596 u_int16_t sc_vendor;
597 u_int16_t sc_device, sc_subdevice;
598 u_int16_t sc_fw_vers;
599 int sc_init_level;
600 int sc_state;
601 #define GDT_NORMAL 0x00
602 #define GDT_POLLING 0x01
603 #define GDT_SHUTDOWN 0x02
604 #define GDT_POLL_WAIT 0x80
605 struct cdev *sc_dev;
606 bus_space_tag_t sc_dpmemt;
607 bus_space_handle_t sc_dpmemh;
608 bus_addr_t sc_dpmembase;
609 bus_dma_tag_t sc_parent_dmat;
610 bus_dma_tag_t sc_buffer_dmat;
611 bus_dma_tag_t sc_gccb_dmat;
612 bus_dmamap_t sc_gccb_dmamap;
613 bus_addr_t sc_gccb_busbase;
614
615 struct gdt_ccb *sc_gccbs;
616 SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
617 TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
618 TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
619
620 u_int16_t sc_ic_all_size;
621 u_int16_t sc_cmd_len;
622 u_int16_t sc_cmd_off;
623 u_int16_t sc_cmd_cnt;
624 u_int8_t sc_cmd[GDT_CMD_SZ];
625
626 u_int32_t sc_info;
627 u_int32_t sc_info2;
628 u_int16_t sc_status;
629 u_int16_t sc_service;
630
631 u_int8_t sc_bus_cnt;
632 u_int8_t sc_virt_bus;
633 u_int8_t sc_bus_id[GDT_MAXBUS];
634 u_int8_t sc_more_proc;
635
636 struct {
637 u_int8_t hd_present;
638 u_int8_t hd_is_logdrv;
639 u_int8_t hd_is_arraydrv;
640 u_int8_t hd_is_master;
641 u_int8_t hd_is_parity;
642 u_int8_t hd_is_hotfix;
643 u_int8_t hd_master_no;
644 u_int8_t hd_lock;
645 u_int8_t hd_heads;
646 u_int8_t hd_secs;
647 u_int16_t hd_devtype;
648 u_int32_t hd_size;
649 u_int8_t hd_ldr_no;
650 u_int8_t hd_rw_attribs;
651 u_int32_t hd_start_sec;
652 } sc_hdr[GDT_MAX_HDRIVES];
653
654 u_int16_t sc_raw_feat;
655 u_int16_t sc_cache_feat;
656
657 gdt_evt_data sc_dvr;
658 char oem_name[8];
659
660 struct cam_sim *sims[GDT_MAXBUS];
661 struct cam_path *paths[GDT_MAXBUS];
662
663 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
664 u_int8_t (*sc_get_status)(struct gdt_softc *);
665 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
666 void (*sc_release_event)(struct gdt_softc *);
667 void (*sc_set_sema0)(struct gdt_softc *);
668 int (*sc_test_busy)(struct gdt_softc *);
669
670 TAILQ_ENTRY(gdt_softc) links;
671 };
672
673 /*
674 * A command control block, one for each corresponding command index of the
675 * controller.
676 */
677 struct gdt_ccb {
678 u_int8_t gc_scratch[GDT_SCRATCH_SZ];
679 union ccb *gc_ccb;
680 gdt_ucmd_t *gc_ucmd;
681 bus_dmamap_t gc_dmamap;
682 int gc_map_flag;
683 int gc_timeout;
684 int gc_state;
685 u_int8_t gc_service;
686 u_int8_t gc_cmd_index;
687 u_int8_t gc_flags;
688 #define GDT_GCF_UNUSED 0
689 #define GDT_GCF_INTERNAL 1
690 #define GDT_GCF_SCREEN 2
691 #define GDT_GCF_SCSI 3
692 #define GDT_GCF_IOCTL 4
693 SLIST_ENTRY(gdt_ccb) sle;
694 };
695
696
697 int iir_init(struct gdt_softc *);
698 void iir_free(struct gdt_softc *);
699 void iir_attach(struct gdt_softc *);
700 void iir_intr(void *arg);
701
702 #if defined( __GNUC__) || defined(__INTEL_COMPILER)
703 /* These all require correctly aligned buffers */
704 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
705 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
706 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
707 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
708
709 static __inline__ void
710 gdt_enc16(addr, value)
711 u_int8_t *addr;
712 u_int16_t value;
713 {
714 *(u_int16_t *)addr = htole16(value);
715 }
716
717 static __inline__ void
718 gdt_enc32(addr, value)
719 u_int8_t *addr;
720 u_int32_t value;
721 {
722 *(u_int32_t *)addr = htole32(value);
723 }
724
725 static __inline__ u_int16_t
726 gdt_dec16(addr)
727 u_int8_t *addr;
728 {
729 return le16toh(*(u_int16_t *)addr);
730 }
731
732 static __inline__ u_int32_t
733 gdt_dec32(addr)
734 u_int8_t *addr;
735 {
736 return le32toh(*(u_int32_t *)addr);
737 }
738 #endif
739
740 #if defined(__alpha__)
741 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
742 #undef vtophys
743 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
744 #endif
745
746 extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
747 extern u_int8_t gdt_polling;
748
749 struct cdev *gdt_make_dev(int unit);
750 void gdt_destroy_dev(struct cdev *dev);
751 void gdt_next(struct gdt_softc *gdt);
752 void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
753
754 gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
755 gdt_evt_data *evt);
756 int gdt_read_event(int handle, gdt_evt_str *estr);
757 void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
758 void gdt_clear_events(void);
759
760 #endif
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