The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/iir/iir_pci.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  *       Copyright (c) 2000-03 ICP vortex GmbH
    5  *       Copyright (c) 2002-03 Intel Corporation
    6  *       Copyright (c) 2003    Adaptec Inc.
    7  *       All Rights Reserved
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions, and the following disclaimer,
   14  *    without modification, immediately at the beginning of the file.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. The name of the author may not be used to endorse or promote products
   19  *    derived from this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: stable/12/sys/dev/iir/iir_pci.c 371093 2021-11-25 17:42:43Z emaste $");
   36 
   37 /*
   38  *  iir_pci.c:  PCI Bus Attachment for Intel Integrated RAID Controller driver
   39  *
   40  *  Written by: Achim Leubner <achim.leubner@intel.com>
   41  *  Written by: Achim Leubner <achim_leubner@adaptec.com>
   42  *  Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
   43  *
   44  *  TODO:
   45  */
   46 
   47 /* #include "opt_iir.h" */
   48 
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/endian.h>
   52 #include <sys/kernel.h>
   53 #include <sys/lock.h>
   54 #include <sys/mutex.h>
   55 #include <sys/module.h>
   56 #include <sys/bus.h> 
   57 
   58 #include <machine/bus.h> 
   59 #include <machine/resource.h>
   60 #include <sys/rman.h>
   61 
   62 #include <dev/pci/pcireg.h>
   63 #include <dev/pci/pcivar.h>
   64 
   65 #include <cam/scsi/scsi_all.h>
   66 
   67 #include <dev/iir/iir.h>
   68 
   69 /* Mapping registers for various areas */
   70 #define PCI_DPMEM       PCIR_BAR(0)
   71 
   72 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
   73 #define GDT_PCI_PRODUCT_FC      0x200
   74 
   75 /* PCI SRAM structure */
   76 #define GDT_MAGIC       0x00    /* u_int32_t, controller ID from BIOS */
   77 #define GDT_NEED_DEINIT 0x04    /* u_int16_t, switch between BIOS/driver */
   78 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
   79 #define GDT_OS_USED     0x10    /* u_int8_t [16], OS code per service */
   80 #define GDT_FW_MAGIC    0x3c    /* u_int8_t, controller ID from firmware */
   81 #define GDT_SRAM_SZ     0x40
   82 
   83 /* DPRAM PCI controllers */
   84 #define GDT_DPR_IF      0x00    /* interface area */
   85 #define GDT_6SR         (0xff0 - GDT_SRAM_SZ)
   86 #define GDT_SEMA1       0xff1   /* volatile u_int8_t, command semaphore */
   87 #define GDT_IRQEN       0xff5   /* u_int8_t, board interrupts enable */
   88 #define GDT_EVENT       0xff8   /* u_int8_t, release event */
   89 #define GDT_IRQDEL      0xffc   /* u_int8_t, acknowledge board interrupt */
   90 #define GDT_DPRAM_SZ    0x1000
   91 
   92 /* PLX register structure (new PCI controllers) */
   93 #define GDT_CFG_REG     0x00    /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
   94 #define GDT_SEMA0_REG   0x40    /* volatile u_int8_t, command semaphore */
   95 #define GDT_SEMA1_REG   0x41    /* volatile u_int8_t, status semaphore */
   96 #define GDT_PLX_STATUS  0x44    /* volatile u_int16_t, command status */
   97 #define GDT_PLX_SERVICE 0x46    /* u_int16_t, service */
   98 #define GDT_PLX_INFO    0x48    /* u_int32_t [2], additional info */
   99 #define GDT_LDOOR_REG   0x60    /* u_int8_t, PCI to local doorbell */
  100 #define GDT_EDOOR_REG   0x64    /* volatile u_int8_t, local to PCI doorbell */
  101 #define GDT_CONTROL0    0x68    /* u_int8_t, control0 register (unused) */
  102 #define GDT_CONTROL1    0x69    /* u_int8_t, board interrupts enable */
  103 #define GDT_PLX_SZ      0x80
  104 
  105 /* DPRAM new PCI controllers */
  106 #define GDT_IC          0x00    /* interface */
  107 #define GDT_PCINEW_6SR  (0x4000 - GDT_SRAM_SZ)
  108                                 /* SRAM structure */
  109 #define GDT_PCINEW_SZ   0x4000
  110 
  111 /* i960 register structure (PCI MPR controllers) */
  112 #define GDT_MPR_SEMA0   0x10    /* volatile u_int8_t, command semaphore */
  113 #define GDT_MPR_SEMA1   0x12    /* volatile u_int8_t, status semaphore */
  114 #define GDT_MPR_STATUS  0x14    /* volatile u_int16_t, command status */
  115 #define GDT_MPR_SERVICE 0x16    /* u_int16_t, service */
  116 #define GDT_MPR_INFO    0x18    /* u_int32_t [2], additional info */
  117 #define GDT_MPR_LDOOR   0x20    /* u_int8_t, PCI to local doorbell */
  118 #define GDT_MPR_EDOOR   0x2c    /* volatile u_int8_t, locl to PCI doorbell */
  119 #define GDT_EDOOR_EN    0x34    /* u_int8_t, board interrupts enable */
  120 #define GDT_SEVERITY    0xefc   /* u_int8_t, event severity */
  121 #define GDT_EVT_BUF     0xf00   /* u_int8_t [256], event buffer */
  122 #define GDT_I960_SZ     0x1000
  123 
  124 /* DPRAM PCI MPR controllers */
  125 #define GDT_I960R       0x00    /* 4KB i960 registers */
  126 #define GDT_MPR_IC      GDT_I960_SZ
  127                                 /* i960 register area */
  128 #define GDT_MPR_6SR     (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
  129                                 /* DPRAM struct. */
  130 #define GDT_MPR_SZ      (0x3000 - GDT_SRAM_SZ)
  131 
  132 static int      iir_pci_probe(device_t dev);
  133 static int      iir_pci_attach(device_t dev);
  134 
  135 void            gdt_pci_enable_intr(struct gdt_softc *);
  136 
  137 void            gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
  138 u_int8_t        gdt_mpr_get_status(struct gdt_softc *);
  139 void            gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
  140 void            gdt_mpr_release_event(struct gdt_softc *);
  141 void            gdt_mpr_set_sema0(struct gdt_softc *);
  142 int             gdt_mpr_test_busy(struct gdt_softc *);
  143 
  144 static device_method_t iir_pci_methods[] = {
  145         /* Device interface */
  146         DEVMETHOD(device_probe,         iir_pci_probe),
  147         DEVMETHOD(device_attach,        iir_pci_attach),
  148         { 0, 0}
  149 };
  150 
  151 
  152 static  driver_t iir_pci_driver =
  153 {
  154         "iir",
  155         iir_pci_methods,
  156         sizeof(struct gdt_softc)
  157 };
  158 
  159 static devclass_t iir_devclass;
  160 
  161 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
  162 MODULE_DEPEND(iir, pci, 1, 1, 1);
  163 MODULE_DEPEND(iir, cam, 1, 1, 1);
  164 
  165 static int
  166 iir_pci_probe(device_t dev)
  167 {
  168     if (pci_get_vendor(dev) == INTEL_VENDOR_ID_IIR &&
  169         pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
  170         device_set_desc(dev, "Intel Integrated RAID Controller");
  171         return (BUS_PROBE_DEFAULT);
  172     }
  173     if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
  174         ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
  175         pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
  176         pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
  177         device_set_desc(dev, "ICP Disk Array Controller");
  178         return (BUS_PROBE_DEFAULT);
  179     }
  180     return (ENXIO);
  181 }
  182 
  183 
  184 static int
  185 iir_pci_attach(device_t dev)
  186 {
  187     struct gdt_softc    *gdt;
  188     struct resource     *irq = NULL;
  189     int                 retries, rid, error = 0;
  190     void                *ih;
  191     u_int8_t            protocol;  
  192 
  193     gdt = device_get_softc(dev);
  194     mtx_init(&gdt->sc_lock, "iir", NULL, MTX_DEF);
  195 
  196     /* map DPMEM */
  197     rid = PCI_DPMEM;
  198     gdt->sc_dpmem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  199     if (gdt->sc_dpmem == NULL) {
  200         device_printf(dev, "can't allocate register resources\n");
  201         error = ENOMEM;
  202         goto err;
  203     }
  204 
  205     /* get IRQ */
  206     rid = 0;
  207     irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  208                                  RF_ACTIVE | RF_SHAREABLE);
  209     if (irq == NULL) {
  210         device_printf(dev, "can't find IRQ value\n");
  211         error = ENOMEM;
  212         goto err;
  213     }
  214 
  215     gdt->sc_devnode = dev;
  216     gdt->sc_init_level = 0;
  217     gdt->sc_hanum = device_get_unit(dev);
  218     gdt->sc_bus = pci_get_bus(dev);
  219     gdt->sc_slot = pci_get_slot(dev);
  220     gdt->sc_vendor = pci_get_vendor(dev);
  221     gdt->sc_device = pci_get_device(dev);
  222     gdt->sc_subdevice = pci_get_subdevice(dev);
  223     gdt->sc_class = GDT_MPR;
  224 /* no FC ctr.
  225     if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
  226         gdt->sc_class |= GDT_FC;
  227 */
  228 
  229     /* initialize RP controller */
  230     /* check and reset interface area */
  231     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC, htole32(GDT_MPR_MAGIC));
  232     if (bus_read_4(gdt->sc_dpmem, GDT_MPR_IC) != htole32(GDT_MPR_MAGIC)) {
  233         device_printf(dev, "cannot access DPMEM at 0x%jx (shadowed?)\n",
  234             rman_get_start(gdt->sc_dpmem));
  235         error = ENXIO;
  236         goto err;
  237     }
  238     bus_set_region_4(gdt->sc_dpmem, GDT_I960_SZ, htole32(0), GDT_MPR_SZ >> 2);
  239 
  240     /* Disable everything */
  241     bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
  242         bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) | 4);
  243     bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
  244     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
  245     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_CMD_INDEX, 0);
  246 
  247     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO,
  248         htole32(rman_get_start(gdt->sc_dpmem)));
  249     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xff);
  250     bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
  251 
  252     DELAY(20);
  253     retries = GDT_RETRIES;
  254     while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
  255         if (--retries == 0) {
  256             device_printf(dev, "DEINIT failed\n");
  257             error = ENXIO;
  258             goto err;
  259         }
  260         DELAY(1);
  261     }
  262 
  263     protocol = (uint8_t)le32toh(bus_read_4(gdt->sc_dpmem,
  264             GDT_MPR_IC + GDT_S_INFO));
  265     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
  266     if (protocol != GDT_PROTOCOL_VERSION) {
  267         device_printf(dev, "unsupported protocol %d\n", protocol);
  268         error = ENXIO;
  269         goto err;
  270     }
  271     
  272     /* special command to controller BIOS */
  273     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO, htole32(0));
  274     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t),
  275         htole32(0));
  276     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
  277         htole32(1));
  278     bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
  279         htole32(0));
  280     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xfe);
  281     bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
  282 
  283     DELAY(20);
  284     retries = GDT_RETRIES;
  285     while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
  286         if (--retries == 0) {
  287             device_printf(dev, "initialization error\n");
  288             error = ENXIO;
  289             goto err;
  290         }
  291         DELAY(1);
  292     }
  293 
  294     bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
  295 
  296     gdt->sc_ic_all_size = GDT_MPR_SZ;
  297     
  298     gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
  299     gdt->sc_get_status = gdt_mpr_get_status;
  300     gdt->sc_intr = gdt_mpr_intr;
  301     gdt->sc_release_event = gdt_mpr_release_event;
  302     gdt->sc_set_sema0 = gdt_mpr_set_sema0;
  303     gdt->sc_test_busy = gdt_mpr_test_busy;
  304 
  305     /* Allocate a dmatag representing the capabilities of this attachment */
  306     if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
  307                            /*alignemnt*/1, /*boundary*/0,
  308                            /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  309                            /*highaddr*/BUS_SPACE_MAXADDR,
  310                            /*filter*/NULL, /*filterarg*/NULL,
  311                            /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
  312                            /*nsegments*/BUS_SPACE_UNRESTRICTED,
  313                            /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  314                            /*flags*/0, /*lockfunc*/busdma_lock_mutex,
  315                            /*lockarg*/&gdt->sc_lock, &gdt->sc_parent_dmat) != 0) {
  316         error = ENXIO;
  317         goto err;
  318     }
  319     gdt->sc_init_level++;
  320 
  321     if (iir_init(gdt) != 0) {
  322         iir_free(gdt);
  323         error = ENXIO;
  324         goto err;
  325     }
  326 
  327     /* Register with the XPT */
  328     iir_attach(gdt);
  329 
  330     /* associate interrupt handler */
  331     if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE, 
  332                         NULL, iir_intr, gdt, &ih )) {
  333         device_printf(dev, "Unable to register interrupt handler\n");
  334         error = ENXIO;
  335         goto err;
  336     }
  337 
  338     gdt_pci_enable_intr(gdt);
  339     gone_in_dev(dev, 14, "iir(4) removed");
  340     return (0);
  341     
  342 err:
  343     if (irq)
  344         bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
  345 
  346     if (gdt->sc_dpmem)
  347         bus_release_resource( dev, SYS_RES_MEMORY, rid, gdt->sc_dpmem );
  348     mtx_destroy(&gdt->sc_lock);
  349 
  350     return (error);
  351 }
  352 
  353 
  354 /* Enable interrupts */
  355 void
  356 gdt_pci_enable_intr(struct gdt_softc *gdt)
  357 {
  358     GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
  359 
  360     switch(GDT_CLASS(gdt)) {
  361       case GDT_MPR:
  362         bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
  363         bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
  364             bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) & ~4);
  365         break;
  366     }
  367 }
  368 
  369 
  370 /*
  371  * MPR PCI controller-specific functions
  372  */
  373 
  374 void
  375 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
  376 {
  377     u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
  378     u_int16_t dp_offset = gdt->sc_cmd_off;
  379     u_int16_t cmd_no = gdt->sc_cmd_cnt++;
  380 
  381     GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
  382 
  383     gdt->sc_cmd_off += cp_count;
  384 
  385     bus_write_region_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 
  386         (u_int32_t *)gccb->gc_cmd, cp_count >> 2);
  387     bus_write_2(gdt->sc_dpmem,
  388         GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
  389         htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
  390     bus_write_2(gdt->sc_dpmem,
  391         GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
  392         htole16(gccb->gc_service));
  393 }
  394 
  395 u_int8_t
  396 gdt_mpr_get_status(struct gdt_softc *gdt)
  397 {
  398     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
  399         
  400     return bus_read_1(gdt->sc_dpmem, GDT_MPR_EDOOR);
  401 }
  402 
  403 void
  404 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
  405 {
  406     int i;
  407 
  408     GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
  409 
  410     bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
  411 
  412     if (ctx->istatus & 0x80) {          /* error flag */
  413         ctx->istatus &= ~0x80;
  414         ctx->cmd_status = bus_read_2(gdt->sc_dpmem, GDT_MPR_STATUS);
  415     } else                                      /* no error */
  416         ctx->cmd_status = GDT_S_OK;
  417 
  418     ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO);
  419     ctx->service = bus_read_2(gdt->sc_dpmem, GDT_MPR_SERVICE);
  420     ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t));
  421 
  422     /* event string */
  423     if (ctx->istatus == GDT_ASYNCINDEX) {
  424         if (ctx->service != GDT_SCREENSERVICE && 
  425             (gdt->sc_fw_vers & 0xff) >= 0x1a) {
  426             gdt->sc_dvr.severity = bus_read_1(gdt->sc_dpmem, GDT_SEVERITY);
  427             for (i = 0; i < 256; ++i) {
  428                 gdt->sc_dvr.event_string[i] = bus_read_1(gdt->sc_dpmem,
  429                     GDT_EVT_BUF + i);
  430                 if (gdt->sc_dvr.event_string[i] == 0)
  431                     break;
  432             }
  433         }
  434     }
  435     bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA1, 0);
  436 }
  437 
  438 void
  439 gdt_mpr_release_event(struct gdt_softc *gdt)
  440 {
  441     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
  442     
  443     bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
  444 }
  445 
  446 void
  447 gdt_mpr_set_sema0(struct gdt_softc *gdt)
  448 {
  449     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
  450 
  451     bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA0, 1);
  452 }
  453 
  454 int
  455 gdt_mpr_test_busy(struct gdt_softc *gdt)
  456 {
  457     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
  458 
  459     return (bus_read_1(gdt->sc_dpmem, GDT_MPR_SEMA0) & 1);
  460 }

Cache object: 5c55bcf0b6d6bd84f4006f247e816560


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