FreeBSD/Linux Kernel Cross Reference
sys/dev/iir/iir_pci.c
1 /* $FreeBSD$ */
2 /*
3 * Copyright (c) 2000-01 Intel Corporation
4 * All Rights Reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 /*
33 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
34 *
35 * Written by: Achim Leubner <achim.leubner@intel.com>
36 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
37 *
38 * TODO:
39 */
40
41 #ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $"
42
43 /* #include "opt_iir.h" */
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/bus.h>
50
51 #include <machine/bus_memio.h>
52 #include <machine/bus_pio.h>
53 #include <machine/bus.h>
54 #include <machine/resource.h>
55 #include <machine/clock.h>
56 #include <sys/rman.h>
57
58 #include <pci/pcireg.h>
59 #include <pci/pcivar.h>
60
61 #include <cam/scsi/scsi_all.h>
62
63 #include <dev/iir/iir.h>
64
65 /* Mapping registers for various areas */
66 #define PCI_DPMEM PCIR_MAPS
67
68 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
69 #define GDT_PCI_PRODUCT_FC 0x200
70
71 /* PCI SRAM structure */
72 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
73 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
74 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
75 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
76 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
77 #define GDT_SRAM_SZ 0x40
78
79 /* DPRAM PCI controllers */
80 #define GDT_DPR_IF 0x00 /* interface area */
81 #define GDT_6SR (0xff0 - GDT_SRAM_SZ)
82 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
83 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
84 #define GDT_EVENT 0xff8 /* u_int8_t, release event */
85 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
86 #define GDT_DPRAM_SZ 0x1000
87
88 /* PLX register structure (new PCI controllers) */
89 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
90 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
91 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
92 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
93 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
94 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
95 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
96 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
97 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
98 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
99 #define GDT_PLX_SZ 0x80
100
101 /* DPRAM new PCI controllers */
102 #define GDT_IC 0x00 /* interface */
103 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
104 /* SRAM structure */
105 #define GDT_PCINEW_SZ 0x4000
106
107 /* i960 register structure (PCI MPR controllers) */
108 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
109 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
110 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
111 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
112 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
113 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
114 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
115 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
116 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
117 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
118 #define GDT_I960_SZ 0x1000
119
120 /* DPRAM PCI MPR controllers */
121 #define GDT_I960R 0x00 /* 4KB i960 registers */
122 #define GDT_MPR_IC GDT_I960_SZ
123 /* i960 register area */
124 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
125 /* DPRAM struct. */
126 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
127
128 static int iir_pci_probe(device_t dev);
129 static int iir_pci_attach(device_t dev);
130
131 void gdt_pci_enable_intr(struct gdt_softc *);
132
133 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
134 u_int8_t gdt_mpr_get_status(struct gdt_softc *);
135 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
136 void gdt_mpr_release_event(struct gdt_softc *);
137 void gdt_mpr_set_sema0(struct gdt_softc *);
138 int gdt_mpr_test_busy(struct gdt_softc *);
139
140 static device_method_t iir_pci_methods[] = {
141 /* Device interface */
142 DEVMETHOD(device_probe, iir_pci_probe),
143 DEVMETHOD(device_attach, iir_pci_attach),
144 { 0, 0}
145 };
146
147
148 static driver_t iir_pci_driver =
149 {
150 "iir",
151 iir_pci_methods,
152 sizeof(struct gdt_softc)
153 };
154
155 static devclass_t iir_devclass;
156
157 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
158
159 static int
160 iir_pci_probe(device_t dev)
161 {
162 if (pci_get_vendor(dev) == INTEL_VENDOR_ID &&
163 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
164 device_set_desc(dev, "Intel Integrated RAID Controller");
165 return (0);
166 }
167 if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
168 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
169 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
170 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
171 device_set_desc(dev, "ICP Disk Array Controller");
172 return (0);
173 }
174 return (ENXIO);
175 }
176
177
178 static int
179 iir_pci_attach(device_t dev)
180 {
181 struct gdt_softc *gdt;
182 struct resource *io = NULL, *irq = NULL;
183 int retries, rid, error = 0;
184 void *ih;
185 u_int8_t protocol;
186
187 /* map DPMEM */
188 rid = PCI_DPMEM;
189 io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE);
190 if (io == NULL) {
191 device_printf(dev, "can't allocate register resources\n");
192 error = ENOMEM;
193 goto err;
194 }
195
196 /* get IRQ */
197 rid = 0;
198 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
199 RF_ACTIVE | RF_SHAREABLE);
200 if (io == NULL) {
201 device_printf(dev, "can't find IRQ value\n");
202 error = ENOMEM;
203 goto err;
204 }
205
206 gdt = device_get_softc(dev);
207 bzero(gdt, sizeof(struct gdt_softc));
208 gdt->sc_init_level = 0;
209 gdt->sc_dpmemt = rman_get_bustag(io);
210 gdt->sc_dpmemh = rman_get_bushandle(io);
211 gdt->sc_dpmembase = rman_get_start(io);
212 gdt->sc_hanum = device_get_unit(dev);
213 gdt->sc_bus = pci_get_bus(dev);
214 gdt->sc_slot = pci_get_slot(dev);
215 gdt->sc_device = pci_get_device(dev);
216 gdt->sc_subdevice = pci_get_subdevice(dev);
217 gdt->sc_class = GDT_MPR;
218 /* no FC ctr.
219 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
220 gdt->sc_class |= GDT_FC;
221 */
222
223 /* initialize RP controller */
224 /* check and reset interface area */
225 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
226 htole32(GDT_MPR_MAGIC));
227 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
228 htole32(GDT_MPR_MAGIC)) {
229 printf("cannot access DPMEM at 0x%x (shadowed?)\n",
230 gdt->sc_dpmembase);
231 error = ENXIO;
232 goto err;
233 }
234 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
235 GDT_MPR_SZ >> 2);
236
237 /* Disable everything */
238 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
239 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
240 GDT_EDOOR_EN) | 4);
241 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
242 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
243 0);
244 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
245 0);
246
247 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
248 htole32(gdt->sc_dpmembase));
249 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
250 0xff);
251 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
252
253 DELAY(20);
254 retries = GDT_RETRIES;
255 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
256 GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
257 if (--retries == 0) {
258 printf("DEINIT failed\n");
259 error = ENXIO;
260 goto err;
261 }
262 DELAY(1);
263 }
264
265 protocol = (u_int8_t)letoh32(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
266 GDT_MPR_IC + GDT_S_INFO));
267 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
268 0);
269 if (protocol != GDT_PROTOCOL_VERSION) {
270 printf("unsupported protocol %d\n", protocol);
271 error = ENXIO;
272 goto err;
273 }
274
275 /* special commnd to controller BIOS */
276 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
277 htole32(0));
278 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
279 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
280 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
281 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
282 htole32(1));
283 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
284 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
285 htole32(0));
286 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
287 0xfe);
288 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
289
290 DELAY(20);
291 retries = GDT_RETRIES;
292 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
293 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
294 if (--retries == 0) {
295 printf("initialization error\n");
296 error = ENXIO;
297 goto err;
298 }
299 DELAY(1);
300 }
301
302 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
303 0);
304
305 gdt->sc_ic_all_size = GDT_MPR_SZ;
306
307 gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
308 gdt->sc_get_status = gdt_mpr_get_status;
309 gdt->sc_intr = gdt_mpr_intr;
310 gdt->sc_release_event = gdt_mpr_release_event;
311 gdt->sc_set_sema0 = gdt_mpr_set_sema0;
312 gdt->sc_test_busy = gdt_mpr_test_busy;
313
314 /* Allocate a dmatag representing the capabilities of this attachment */
315 /* XXX Should be a child of the PCI bus dma tag */
316 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
317 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
318 /*highaddr*/BUS_SPACE_MAXADDR,
319 /*filter*/NULL, /*filterarg*/NULL,
320 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
321 /*nsegments*/GDT_MAXSG,
322 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
323 /*flags*/0, &gdt->sc_parent_dmat) != 0) {
324 error = ENXIO;
325 goto err;
326 }
327 gdt->sc_init_level++;
328
329 if (iir_init(gdt) != 0) {
330 iir_free(gdt);
331 error = ENXIO;
332 goto err;
333 }
334
335 /* Register with the XPT */
336 iir_attach(gdt);
337
338 /* associate interrupt handler */
339 if (bus_setup_intr( dev, irq, INTR_TYPE_CAM,
340 iir_intr, gdt, &ih )) {
341 device_printf(dev, "Unable to register interrupt handler\n");
342 error = ENXIO;
343 goto err;
344 }
345
346 gdt_pci_enable_intr(gdt);
347 return (0);
348
349 err:
350 if (irq)
351 bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
352 /*
353 if (io)
354 bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
355 */
356 return (error);
357 }
358
359
360 /* Enable interrupts */
361 void
362 gdt_pci_enable_intr(struct gdt_softc *gdt)
363 {
364 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
365
366 switch(GDT_CLASS(gdt)) {
367 case GDT_MPR:
368 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
369 GDT_MPR_EDOOR, 0xff);
370 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
371 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
372 GDT_EDOOR_EN) & ~4);
373 break;
374 }
375 }
376
377
378 /*
379 * MPR PCI controller-specific functions
380 */
381
382 void
383 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb)
384 {
385 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t));
386 u_int16_t dp_offset = gdt->sc_cmd_off;
387 u_int16_t cmd_no = gdt->sc_cmd_cnt++;
388
389 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
390
391 gdt->sc_cmd_off += cp_count;
392
393 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
394 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
395 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
396 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
397 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
398 htole16(ccb->gc_service));
399 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
400 GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
401 (u_int32_t *)gdt->sc_cmd, cp_count >> 2);
402 }
403
404 u_int8_t
405 gdt_mpr_get_status(struct gdt_softc *gdt)
406 {
407 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
408
409 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
410 }
411
412 void
413 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
414 {
415 int i;
416
417 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
418
419 if (ctx->istatus & 0x80) { /* error flag */
420 ctx->istatus &= ~0x80;
421 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
422 gdt->sc_dpmemh, GDT_MPR_STATUS);
423 } else /* no error */
424 ctx->cmd_status = GDT_S_OK;
425
426 ctx->info =
427 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
428 ctx->service =
429 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
430 ctx->info2 =
431 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
432 GDT_MPR_INFO + sizeof (u_int32_t));
433
434 /* event string */
435 if (ctx->istatus == GDT_ASYNCINDEX) {
436 if (ctx->service != GDT_SCREENSERVICE &&
437 (gdt->sc_fw_vers & 0xff) >= 0x1a) {
438 gdt->sc_dvr.severity =
439 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
440 for (i = 0; i < 256; ++i) {
441 gdt->sc_dvr.event_string[i] =
442 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
443 GDT_EVT_BUF + i);
444 if (gdt->sc_dvr.event_string[i] == 0)
445 break;
446 }
447 }
448 }
449 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
450 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
451 }
452
453 void
454 gdt_mpr_release_event(struct gdt_softc *gdt)
455 {
456 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
457
458 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
459 }
460
461 void
462 gdt_mpr_set_sema0(struct gdt_softc *gdt)
463 {
464 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
465
466 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
467 }
468
469 int
470 gdt_mpr_test_busy(struct gdt_softc *gdt)
471 {
472 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
473
474 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
475 GDT_MPR_SEMA0) & 1);
476 }
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