FreeBSD/Linux Kernel Cross Reference
sys/dev/iir/iir_pci.c
1 /*-
2 * Copyright (c) 2000-03 ICP vortex GmbH
3 * Copyright (c) 2002-03 Intel Corporation
4 * Copyright (c) 2003 Adaptec Inc.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #ident "$Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $"
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/8.3/sys/dev/iir/iir_pci.c 192097 2009-05-14 13:32:33Z brueffer $");
35
36 /*
37 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
38 *
39 * Written by: Achim Leubner <achim.leubner@intel.com>
40 * Written by: Achim Leubner <achim_leubner@adaptec.com>
41 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
42 *
43 * TODO:
44 */
45
46 /* #include "opt_iir.h" */
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/endian.h>
51 #include <sys/kernel.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/module.h>
55 #include <sys/bus.h>
56
57 #include <machine/bus.h>
58 #include <machine/resource.h>
59 #include <sys/rman.h>
60
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63
64 #include <cam/scsi/scsi_all.h>
65
66 #include <dev/iir/iir.h>
67
68 /* Mapping registers for various areas */
69 #define PCI_DPMEM PCIR_BAR(0)
70
71 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
72 #define GDT_PCI_PRODUCT_FC 0x200
73
74 /* PCI SRAM structure */
75 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
76 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
77 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
78 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
79 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
80 #define GDT_SRAM_SZ 0x40
81
82 /* DPRAM PCI controllers */
83 #define GDT_DPR_IF 0x00 /* interface area */
84 #define GDT_6SR (0xff0 - GDT_SRAM_SZ)
85 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
86 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
87 #define GDT_EVENT 0xff8 /* u_int8_t, release event */
88 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
89 #define GDT_DPRAM_SZ 0x1000
90
91 /* PLX register structure (new PCI controllers) */
92 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
93 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
94 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
95 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
96 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
97 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
98 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
99 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
100 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
101 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
102 #define GDT_PLX_SZ 0x80
103
104 /* DPRAM new PCI controllers */
105 #define GDT_IC 0x00 /* interface */
106 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
107 /* SRAM structure */
108 #define GDT_PCINEW_SZ 0x4000
109
110 /* i960 register structure (PCI MPR controllers) */
111 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
112 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
113 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
114 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
115 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
116 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
117 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
118 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
119 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
120 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
121 #define GDT_I960_SZ 0x1000
122
123 /* DPRAM PCI MPR controllers */
124 #define GDT_I960R 0x00 /* 4KB i960 registers */
125 #define GDT_MPR_IC GDT_I960_SZ
126 /* i960 register area */
127 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
128 /* DPRAM struct. */
129 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
130
131 static int iir_pci_probe(device_t dev);
132 static int iir_pci_attach(device_t dev);
133
134 void gdt_pci_enable_intr(struct gdt_softc *);
135
136 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
137 u_int8_t gdt_mpr_get_status(struct gdt_softc *);
138 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
139 void gdt_mpr_release_event(struct gdt_softc *);
140 void gdt_mpr_set_sema0(struct gdt_softc *);
141 int gdt_mpr_test_busy(struct gdt_softc *);
142
143 static device_method_t iir_pci_methods[] = {
144 /* Device interface */
145 DEVMETHOD(device_probe, iir_pci_probe),
146 DEVMETHOD(device_attach, iir_pci_attach),
147 { 0, 0}
148 };
149
150
151 static driver_t iir_pci_driver =
152 {
153 "iir",
154 iir_pci_methods,
155 sizeof(struct gdt_softc)
156 };
157
158 static devclass_t iir_devclass;
159
160 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
161 MODULE_DEPEND(iir, pci, 1, 1, 1);
162 MODULE_DEPEND(iir, cam, 1, 1, 1);
163
164 static int
165 iir_pci_probe(device_t dev)
166 {
167 if (pci_get_vendor(dev) == INTEL_VENDOR_ID &&
168 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
169 device_set_desc(dev, "Intel Integrated RAID Controller");
170 return (BUS_PROBE_DEFAULT);
171 }
172 if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
173 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
174 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
175 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
176 device_set_desc(dev, "ICP Disk Array Controller");
177 return (BUS_PROBE_DEFAULT);
178 }
179 return (ENXIO);
180 }
181
182
183 static int
184 iir_pci_attach(device_t dev)
185 {
186 struct gdt_softc *gdt;
187 struct resource *io = NULL, *irq = NULL;
188 int retries, rid, error = 0;
189 void *ih;
190 u_int8_t protocol;
191
192 /* map DPMEM */
193 rid = PCI_DPMEM;
194 io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
195 if (io == NULL) {
196 device_printf(dev, "can't allocate register resources\n");
197 error = ENOMEM;
198 goto err;
199 }
200
201 /* get IRQ */
202 rid = 0;
203 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
204 RF_ACTIVE | RF_SHAREABLE);
205 if (irq == NULL) {
206 device_printf(dev, "can't find IRQ value\n");
207 error = ENOMEM;
208 goto err;
209 }
210
211 gdt = device_get_softc(dev);
212 gdt->sc_devnode = dev;
213 gdt->sc_init_level = 0;
214 gdt->sc_dpmemt = rman_get_bustag(io);
215 gdt->sc_dpmemh = rman_get_bushandle(io);
216 gdt->sc_dpmembase = rman_get_start(io);
217 gdt->sc_hanum = device_get_unit(dev);
218 gdt->sc_bus = pci_get_bus(dev);
219 gdt->sc_slot = pci_get_slot(dev);
220 gdt->sc_vendor = pci_get_vendor(dev);
221 gdt->sc_device = pci_get_device(dev);
222 gdt->sc_subdevice = pci_get_subdevice(dev);
223 gdt->sc_class = GDT_MPR;
224 /* no FC ctr.
225 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
226 gdt->sc_class |= GDT_FC;
227 */
228
229 /* initialize RP controller */
230 /* check and reset interface area */
231 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
232 htole32(GDT_MPR_MAGIC));
233 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
234 htole32(GDT_MPR_MAGIC)) {
235 printf("cannot access DPMEM at 0x%jx (shadowed?)\n",
236 (uintmax_t)gdt->sc_dpmembase);
237 error = ENXIO;
238 goto err;
239 }
240 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
241 GDT_MPR_SZ >> 2);
242
243 /* Disable everything */
244 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
245 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
246 GDT_EDOOR_EN) | 4);
247 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
248 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
249 0);
250 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
251 0);
252
253 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
254 htole32(gdt->sc_dpmembase));
255 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
256 0xff);
257 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
258
259 DELAY(20);
260 retries = GDT_RETRIES;
261 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
262 GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
263 if (--retries == 0) {
264 printf("DEINIT failed\n");
265 error = ENXIO;
266 goto err;
267 }
268 DELAY(1);
269 }
270
271 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
272 GDT_MPR_IC + GDT_S_INFO));
273 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
274 0);
275 if (protocol != GDT_PROTOCOL_VERSION) {
276 printf("unsupported protocol %d\n", protocol);
277 error = ENXIO;
278 goto err;
279 }
280
281 /* special commnd to controller BIOS */
282 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
283 htole32(0));
284 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
285 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
286 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
287 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
288 htole32(1));
289 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
290 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
291 htole32(0));
292 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
293 0xfe);
294 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
295
296 DELAY(20);
297 retries = GDT_RETRIES;
298 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
299 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
300 if (--retries == 0) {
301 printf("initialization error\n");
302 error = ENXIO;
303 goto err;
304 }
305 DELAY(1);
306 }
307
308 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
309 0);
310
311 gdt->sc_ic_all_size = GDT_MPR_SZ;
312
313 gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
314 gdt->sc_get_status = gdt_mpr_get_status;
315 gdt->sc_intr = gdt_mpr_intr;
316 gdt->sc_release_event = gdt_mpr_release_event;
317 gdt->sc_set_sema0 = gdt_mpr_set_sema0;
318 gdt->sc_test_busy = gdt_mpr_test_busy;
319
320 /* Allocate a dmatag representing the capabilities of this attachment */
321 /* XXX Should be a child of the PCI bus dma tag */
322 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
323 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
324 /*highaddr*/BUS_SPACE_MAXADDR,
325 /*filter*/NULL, /*filterarg*/NULL,
326 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
327 /*nsegments*/GDT_MAXSG,
328 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
329 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
330 /*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) {
331 error = ENXIO;
332 goto err;
333 }
334 gdt->sc_init_level++;
335
336 if (iir_init(gdt) != 0) {
337 iir_free(gdt);
338 error = ENXIO;
339 goto err;
340 }
341
342 /* Register with the XPT */
343 iir_attach(gdt);
344
345 /* associate interrupt handler */
346 if (bus_setup_intr( dev, irq, INTR_TYPE_CAM,
347 NULL, iir_intr, gdt, &ih )) {
348 device_printf(dev, "Unable to register interrupt handler\n");
349 error = ENXIO;
350 goto err;
351 }
352
353 gdt_pci_enable_intr(gdt);
354 return (0);
355
356 err:
357 if (irq)
358 bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
359 /*
360 if (io)
361 bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
362 */
363 return (error);
364 }
365
366
367 /* Enable interrupts */
368 void
369 gdt_pci_enable_intr(struct gdt_softc *gdt)
370 {
371 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
372
373 switch(GDT_CLASS(gdt)) {
374 case GDT_MPR:
375 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
376 GDT_MPR_EDOOR, 0xff);
377 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
378 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
379 GDT_EDOOR_EN) & ~4);
380 break;
381 }
382 }
383
384
385 /*
386 * MPR PCI controller-specific functions
387 */
388
389 void
390 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
391 {
392 u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
393 u_int16_t dp_offset = gdt->sc_cmd_off;
394 u_int16_t cmd_no = gdt->sc_cmd_cnt++;
395
396 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
397
398 gdt->sc_cmd_off += cp_count;
399
400 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
401 GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
402 (u_int32_t *)gccb->gc_cmd, cp_count >> 2);
403 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
404 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
405 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
406 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
407 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
408 htole16(gccb->gc_service));
409 }
410
411 u_int8_t
412 gdt_mpr_get_status(struct gdt_softc *gdt)
413 {
414 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
415
416 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
417 }
418
419 void
420 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
421 {
422 int i;
423
424 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
425
426 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
427
428 if (ctx->istatus & 0x80) { /* error flag */
429 ctx->istatus &= ~0x80;
430 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
431 gdt->sc_dpmemh, GDT_MPR_STATUS);
432 } else /* no error */
433 ctx->cmd_status = GDT_S_OK;
434
435 ctx->info =
436 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
437 ctx->service =
438 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
439 ctx->info2 =
440 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
441 GDT_MPR_INFO + sizeof (u_int32_t));
442
443 /* event string */
444 if (ctx->istatus == GDT_ASYNCINDEX) {
445 if (ctx->service != GDT_SCREENSERVICE &&
446 (gdt->sc_fw_vers & 0xff) >= 0x1a) {
447 gdt->sc_dvr.severity =
448 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
449 for (i = 0; i < 256; ++i) {
450 gdt->sc_dvr.event_string[i] =
451 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
452 GDT_EVT_BUF + i);
453 if (gdt->sc_dvr.event_string[i] == 0)
454 break;
455 }
456 }
457 }
458 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
459 }
460
461 void
462 gdt_mpr_release_event(struct gdt_softc *gdt)
463 {
464 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
465
466 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
467 }
468
469 void
470 gdt_mpr_set_sema0(struct gdt_softc *gdt)
471 {
472 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
473
474 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
475 }
476
477 int
478 gdt_mpr_test_busy(struct gdt_softc *gdt)
479 {
480 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
481
482 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
483 GDT_MPR_SEMA0) & 1);
484 }
Cache object: 83fa8eb5f01ea71cd58e538b9e72367d
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