The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/iir/iir_pci.c

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    1 /*-
    2  *       Copyright (c) 2000-03 ICP vortex GmbH
    3  *       Copyright (c) 2002-03 Intel Corporation
    4  *       Copyright (c) 2003    Adaptec Inc.
    5  *       All Rights Reserved
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions, and the following disclaimer,
   12  *    without modification, immediately at the beginning of the file.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. The name of the author may not be used to endorse or promote products
   17  *    derived from this software without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/9.0/sys/dev/iir/iir_pci.c 201821 2010-01-08 20:40:28Z trasz $");
   34 
   35 /*
   36  *  iir_pci.c:  PCI Bus Attachment for Intel Integrated RAID Controller driver
   37  *
   38  *  Written by: Achim Leubner <achim.leubner@intel.com>
   39  *  Written by: Achim Leubner <achim_leubner@adaptec.com>
   40  *  Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
   41  *
   42  *  TODO:
   43  */
   44 
   45 /* #include "opt_iir.h" */
   46 
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/endian.h>
   50 #include <sys/kernel.h>
   51 #include <sys/lock.h>
   52 #include <sys/mutex.h>
   53 #include <sys/module.h>
   54 #include <sys/bus.h> 
   55 
   56 #include <machine/bus.h> 
   57 #include <machine/resource.h>
   58 #include <sys/rman.h>
   59 
   60 #include <dev/pci/pcireg.h>
   61 #include <dev/pci/pcivar.h>
   62 
   63 #include <cam/scsi/scsi_all.h>
   64 
   65 #include <dev/iir/iir.h>
   66 
   67 /* Mapping registers for various areas */
   68 #define PCI_DPMEM       PCIR_BAR(0)
   69 
   70 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
   71 #define GDT_PCI_PRODUCT_FC      0x200
   72 
   73 /* PCI SRAM structure */
   74 #define GDT_MAGIC       0x00    /* u_int32_t, controller ID from BIOS */
   75 #define GDT_NEED_DEINIT 0x04    /* u_int16_t, switch between BIOS/driver */
   76 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
   77 #define GDT_OS_USED     0x10    /* u_int8_t [16], OS code per service */
   78 #define GDT_FW_MAGIC    0x3c    /* u_int8_t, controller ID from firmware */
   79 #define GDT_SRAM_SZ     0x40
   80 
   81 /* DPRAM PCI controllers */
   82 #define GDT_DPR_IF      0x00    /* interface area */
   83 #define GDT_6SR         (0xff0 - GDT_SRAM_SZ)
   84 #define GDT_SEMA1       0xff1   /* volatile u_int8_t, command semaphore */
   85 #define GDT_IRQEN       0xff5   /* u_int8_t, board interrupts enable */
   86 #define GDT_EVENT       0xff8   /* u_int8_t, release event */
   87 #define GDT_IRQDEL      0xffc   /* u_int8_t, acknowledge board interrupt */
   88 #define GDT_DPRAM_SZ    0x1000
   89 
   90 /* PLX register structure (new PCI controllers) */
   91 #define GDT_CFG_REG     0x00    /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
   92 #define GDT_SEMA0_REG   0x40    /* volatile u_int8_t, command semaphore */
   93 #define GDT_SEMA1_REG   0x41    /* volatile u_int8_t, status semaphore */
   94 #define GDT_PLX_STATUS  0x44    /* volatile u_int16_t, command status */
   95 #define GDT_PLX_SERVICE 0x46    /* u_int16_t, service */
   96 #define GDT_PLX_INFO    0x48    /* u_int32_t [2], additional info */
   97 #define GDT_LDOOR_REG   0x60    /* u_int8_t, PCI to local doorbell */
   98 #define GDT_EDOOR_REG   0x64    /* volatile u_int8_t, local to PCI doorbell */
   99 #define GDT_CONTROL0    0x68    /* u_int8_t, control0 register (unused) */
  100 #define GDT_CONTROL1    0x69    /* u_int8_t, board interrupts enable */
  101 #define GDT_PLX_SZ      0x80
  102 
  103 /* DPRAM new PCI controllers */
  104 #define GDT_IC          0x00    /* interface */
  105 #define GDT_PCINEW_6SR  (0x4000 - GDT_SRAM_SZ)
  106                                 /* SRAM structure */
  107 #define GDT_PCINEW_SZ   0x4000
  108 
  109 /* i960 register structure (PCI MPR controllers) */
  110 #define GDT_MPR_SEMA0   0x10    /* volatile u_int8_t, command semaphore */
  111 #define GDT_MPR_SEMA1   0x12    /* volatile u_int8_t, status semaphore */
  112 #define GDT_MPR_STATUS  0x14    /* volatile u_int16_t, command status */
  113 #define GDT_MPR_SERVICE 0x16    /* u_int16_t, service */
  114 #define GDT_MPR_INFO    0x18    /* u_int32_t [2], additional info */
  115 #define GDT_MPR_LDOOR   0x20    /* u_int8_t, PCI to local doorbell */
  116 #define GDT_MPR_EDOOR   0x2c    /* volatile u_int8_t, locl to PCI doorbell */
  117 #define GDT_EDOOR_EN    0x34    /* u_int8_t, board interrupts enable */
  118 #define GDT_SEVERITY    0xefc   /* u_int8_t, event severity */
  119 #define GDT_EVT_BUF     0xf00   /* u_int8_t [256], event buffer */
  120 #define GDT_I960_SZ     0x1000
  121 
  122 /* DPRAM PCI MPR controllers */
  123 #define GDT_I960R       0x00    /* 4KB i960 registers */
  124 #define GDT_MPR_IC      GDT_I960_SZ
  125                                 /* i960 register area */
  126 #define GDT_MPR_6SR     (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
  127                                 /* DPRAM struct. */
  128 #define GDT_MPR_SZ      (0x3000 - GDT_SRAM_SZ)
  129 
  130 static int      iir_pci_probe(device_t dev);
  131 static int      iir_pci_attach(device_t dev);
  132 
  133 void            gdt_pci_enable_intr(struct gdt_softc *);
  134 
  135 void            gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
  136 u_int8_t        gdt_mpr_get_status(struct gdt_softc *);
  137 void            gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
  138 void            gdt_mpr_release_event(struct gdt_softc *);
  139 void            gdt_mpr_set_sema0(struct gdt_softc *);
  140 int             gdt_mpr_test_busy(struct gdt_softc *);
  141 
  142 static device_method_t iir_pci_methods[] = {
  143         /* Device interface */
  144         DEVMETHOD(device_probe,         iir_pci_probe),
  145         DEVMETHOD(device_attach,        iir_pci_attach),
  146         { 0, 0}
  147 };
  148 
  149 
  150 static  driver_t iir_pci_driver =
  151 {
  152         "iir",
  153         iir_pci_methods,
  154         sizeof(struct gdt_softc)
  155 };
  156 
  157 static devclass_t iir_devclass;
  158 
  159 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
  160 MODULE_DEPEND(iir, pci, 1, 1, 1);
  161 MODULE_DEPEND(iir, cam, 1, 1, 1);
  162 
  163 static int
  164 iir_pci_probe(device_t dev)
  165 {
  166     if (pci_get_vendor(dev) == INTEL_VENDOR_ID &&
  167         pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
  168         device_set_desc(dev, "Intel Integrated RAID Controller");
  169         return (BUS_PROBE_DEFAULT);
  170     }
  171     if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
  172         ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
  173         pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
  174         pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
  175         device_set_desc(dev, "ICP Disk Array Controller");
  176         return (BUS_PROBE_DEFAULT);
  177     }
  178     return (ENXIO);
  179 }
  180 
  181 
  182 static int
  183 iir_pci_attach(device_t dev)
  184 {
  185     struct gdt_softc    *gdt;
  186     struct resource     *io = NULL, *irq = NULL;
  187     int                 retries, rid, error = 0;
  188     void                *ih;
  189     u_int8_t            protocol;  
  190  
  191     /* map DPMEM */
  192     rid = PCI_DPMEM;
  193     io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  194     if (io == NULL) {
  195         device_printf(dev, "can't allocate register resources\n");
  196         error = ENOMEM;
  197         goto err;
  198     }
  199 
  200     /* get IRQ */
  201     rid = 0;
  202     irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  203                                  RF_ACTIVE | RF_SHAREABLE);
  204     if (irq == NULL) {
  205         device_printf(dev, "can't find IRQ value\n");
  206         error = ENOMEM;
  207         goto err;
  208     }
  209 
  210     gdt = device_get_softc(dev);
  211     gdt->sc_devnode = dev;
  212     gdt->sc_init_level = 0;
  213     gdt->sc_dpmemt = rman_get_bustag(io);
  214     gdt->sc_dpmemh = rman_get_bushandle(io);
  215     gdt->sc_dpmembase = rman_get_start(io);
  216     gdt->sc_hanum = device_get_unit(dev);
  217     gdt->sc_bus = pci_get_bus(dev);
  218     gdt->sc_slot = pci_get_slot(dev);
  219     gdt->sc_vendor = pci_get_vendor(dev);
  220     gdt->sc_device = pci_get_device(dev);
  221     gdt->sc_subdevice = pci_get_subdevice(dev);
  222     gdt->sc_class = GDT_MPR;
  223 /* no FC ctr.
  224     if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
  225         gdt->sc_class |= GDT_FC;
  226 */
  227 
  228     /* initialize RP controller */
  229     /* check and reset interface area */
  230     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
  231                       htole32(GDT_MPR_MAGIC));
  232     if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
  233         htole32(GDT_MPR_MAGIC)) {
  234         printf("cannot access DPMEM at 0x%jx (shadowed?)\n",
  235                (uintmax_t)gdt->sc_dpmembase);
  236         error = ENXIO;
  237         goto err;
  238     }
  239     bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
  240                            GDT_MPR_SZ >> 2);
  241 
  242     /* Disable everything */
  243     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
  244                       bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 
  245                                        GDT_EDOOR_EN) | 4);
  246     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
  247     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  248                       0);
  249     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
  250                       0);
  251 
  252     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
  253                       htole32(gdt->sc_dpmembase));
  254     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
  255                       0xff);
  256     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
  257 
  258     DELAY(20);
  259     retries = GDT_RETRIES;
  260     while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  261                             GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
  262         if (--retries == 0) {
  263             printf("DEINIT failed\n");
  264             error = ENXIO;
  265             goto err;
  266         }
  267         DELAY(1);
  268     }
  269 
  270     protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
  271                                                   GDT_MPR_IC + GDT_S_INFO));
  272     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  273                       0);
  274     if (protocol != GDT_PROTOCOL_VERSION) {
  275         printf("unsupported protocol %d\n", protocol);
  276         error = ENXIO;
  277         goto err;
  278     }
  279     
  280     /* special commnd to controller BIOS */
  281     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
  282                       htole32(0));
  283     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
  284                       GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
  285     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
  286                       GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
  287                       htole32(1));
  288     bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
  289                       GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
  290                       htole32(0));
  291     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
  292                       0xfe);
  293     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
  294 
  295     DELAY(20);
  296     retries = GDT_RETRIES;
  297     while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  298                             GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
  299         if (--retries == 0) {
  300             printf("initialization error\n");
  301             error = ENXIO;
  302             goto err;
  303         }
  304         DELAY(1);
  305     }
  306 
  307     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  308                       0);
  309 
  310     gdt->sc_ic_all_size = GDT_MPR_SZ;
  311     
  312     gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
  313     gdt->sc_get_status = gdt_mpr_get_status;
  314     gdt->sc_intr = gdt_mpr_intr;
  315     gdt->sc_release_event = gdt_mpr_release_event;
  316     gdt->sc_set_sema0 = gdt_mpr_set_sema0;
  317     gdt->sc_test_busy = gdt_mpr_test_busy;
  318 
  319     /* Allocate a dmatag representing the capabilities of this attachment */
  320     /* XXX Should be a child of the PCI bus dma tag */
  321     if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
  322                            /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  323                            /*highaddr*/BUS_SPACE_MAXADDR,
  324                            /*filter*/NULL, /*filterarg*/NULL,
  325                            /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
  326                            /*nsegments*/GDT_MAXSG,
  327                            /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  328                            /*flags*/0, /*lockfunc*/busdma_lock_mutex,
  329                            /*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) {
  330         error = ENXIO;
  331         goto err;
  332     }
  333     gdt->sc_init_level++;
  334 
  335     if (iir_init(gdt) != 0) {
  336         iir_free(gdt);
  337         error = ENXIO;
  338         goto err;
  339     }
  340 
  341     /* Register with the XPT */
  342     iir_attach(gdt);
  343 
  344     /* associate interrupt handler */
  345     if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 
  346                         NULL, iir_intr, gdt, &ih )) {
  347         device_printf(dev, "Unable to register interrupt handler\n");
  348         error = ENXIO;
  349         goto err;
  350     }
  351 
  352     gdt_pci_enable_intr(gdt);
  353     return (0);
  354     
  355 err:
  356     if (irq)
  357         bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
  358 /*
  359     if (io)
  360         bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
  361 */
  362     return (error);
  363 }
  364 
  365 
  366 /* Enable interrupts */
  367 void
  368 gdt_pci_enable_intr(struct gdt_softc *gdt)
  369 {
  370     GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
  371 
  372     switch(GDT_CLASS(gdt)) {
  373       case GDT_MPR:
  374         bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  375                           GDT_MPR_EDOOR, 0xff);
  376         bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
  377                           bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  378                                            GDT_EDOOR_EN) & ~4);
  379         break;
  380     }
  381 }
  382 
  383 
  384 /*
  385  * MPR PCI controller-specific functions
  386  */
  387 
  388 void
  389 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
  390 {
  391     u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
  392     u_int16_t dp_offset = gdt->sc_cmd_off;
  393     u_int16_t cmd_no = gdt->sc_cmd_cnt++;
  394 
  395     GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
  396 
  397     gdt->sc_cmd_off += cp_count;
  398 
  399     bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
  400                              GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 
  401                              (u_int32_t *)gccb->gc_cmd, cp_count >> 2);
  402     bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
  403                       GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
  404                       htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
  405     bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
  406                       GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
  407                       htole16(gccb->gc_service));
  408 }
  409 
  410 u_int8_t
  411 gdt_mpr_get_status(struct gdt_softc *gdt)
  412 {
  413     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
  414         
  415     return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
  416 }
  417 
  418 void
  419 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
  420 {
  421     int i;
  422 
  423     GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
  424 
  425     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
  426 
  427     if (ctx->istatus & 0x80) {          /* error flag */
  428         ctx->istatus &= ~0x80;
  429         ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
  430                                            gdt->sc_dpmemh, GDT_MPR_STATUS);
  431     } else                                      /* no error */
  432         ctx->cmd_status = GDT_S_OK;
  433 
  434     ctx->info =
  435         bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
  436     ctx->service = 
  437         bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
  438     ctx->info2 = 
  439         bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 
  440                          GDT_MPR_INFO + sizeof (u_int32_t));
  441 
  442     /* event string */
  443     if (ctx->istatus == GDT_ASYNCINDEX) {
  444         if (ctx->service != GDT_SCREENSERVICE && 
  445             (gdt->sc_fw_vers & 0xff) >= 0x1a) {
  446             gdt->sc_dvr.severity = 
  447                 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
  448             for (i = 0; i < 256; ++i) {
  449                 gdt->sc_dvr.event_string[i] = 
  450                     bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  451                                      GDT_EVT_BUF + i);
  452                 if (gdt->sc_dvr.event_string[i] == 0)
  453                     break;
  454             }
  455         }
  456     }
  457     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
  458 }
  459 
  460 void
  461 gdt_mpr_release_event(struct gdt_softc *gdt)
  462 {
  463     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
  464     
  465     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
  466 }
  467 
  468 void
  469 gdt_mpr_set_sema0(struct gdt_softc *gdt)
  470 {
  471     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
  472 
  473     bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
  474 }
  475 
  476 int
  477 gdt_mpr_test_busy(struct gdt_softc *gdt)
  478 {
  479     GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
  480 
  481     return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
  482                              GDT_MPR_SEMA0) & 1);
  483 }

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