ioat_hw.h

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    1 /*-
    2  * Copyright (C) 2012 Intel Corporation
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 __FBSDID("$FreeBSD$");
   28 
   29 #ifndef __IOAT_HW_H__
   30 #define __IOAT_HW_H__
   31 
   32 #define IOAT_MAX_CHANNELS               32
   33 
   34 #define IOAT_CHANCNT_OFFSET             0x00
   35 
   36 #define IOAT_XFERCAP_OFFSET             0x01
   37 /* Only bits [4:0] are valid. */
   38 #define IOAT_XFERCAP_VALID_MASK         0x1f
   39 
   40 #define IOAT_GENCTRL_OFFSET             0x02
   41 
   42 #define IOAT_INTRCTRL_OFFSET            0x03
   43 #define IOAT_INTRCTRL_MASTER_INT_EN     0x01
   44 
   45 #define IOAT_ATTNSTATUS_OFFSET          0x04
   46 
   47 #define IOAT_CBVER_OFFSET               0x08
   48 
   49 #define IOAT_INTRDELAY_OFFSET           0x0C
   50 #define IOAT_INTRDELAY_SUPPORTED        (1 << 15)
   51 /* Reserved.                            (1 << 14) */
   52 /* [13:0] is the coalesce period, in microseconds. */
   53 #define IOAT_INTRDELAY_US_MASK          ((1 << 14) - 1)
   54 
   55 #define IOAT_CS_STATUS_OFFSET           0x0E
   56 
   57 #define IOAT_DMACAPABILITY_OFFSET       0x10
   58 
   59 /* DMA Channel Registers */
   60 #define IOAT_CHANCTRL_OFFSET                    0x80
   61 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK     0xF000
   62 #define IOAT_CHANCTRL_COMPL_DCA_EN              0x0200
   63 #define IOAT_CHANCTRL_CHANNEL_IN_USE            0x0100
   64 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL     0x0020
   65 #define IOAT_CHANCTRL_ERR_INT_EN                0x0010
   66 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN          0x0008
   67 #define IOAT_CHANCTRL_ERR_COMPLETION_EN         0x0004
   68 #define IOAT_CHANCTRL_INT_REARM                 0x0001
   69 #define IOAT_CHANCTRL_RUN                       (IOAT_CHANCTRL_INT_REARM |\
   70                                                  IOAT_CHANCTRL_ERR_COMPLETION_EN |\
   71                                                  IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\
   72                                                  IOAT_CHANCTRL_ERR_INT_EN)
   73 
   74 #define IOAT_CHANCMD_OFFSET             0x84
   75 #define IOAT_CHANCMD_RESET              0x20
   76 #define IOAT_CHANCMD_SUSPEND            0x04
   77 
   78 #define IOAT_DMACOUNT_OFFSET            0x86
   79 
   80 #define IOAT_CHANSTS_OFFSET_LOW         0x88
   81 #define IOAT_CHANSTS_OFFSET_HIGH        0x8C
   82 #define IOAT_CHANSTS_OFFSET             0x88
   83 
   84 #define IOAT_CHANSTS_STATUS             0x7ULL
   85 #define IOAT_CHANSTS_ACTIVE             0x0
   86 #define IOAT_CHANSTS_IDLE               0x1
   87 #define IOAT_CHANSTS_SUSPENDED          0x2
   88 #define IOAT_CHANSTS_HALTED             0x3
   89 #define IOAT_CHANSTS_ARMED              0x4
   90 
   91 #define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
   92 #define IOAT_CHANSTS_SOFT_ERROR         0x10ULL
   93 
   94 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK  (~0x3FULL)
   95 
   96 #define IOAT_CHAINADDR_OFFSET_LOW       0x90
   97 #define IOAT_CHAINADDR_OFFSET_HIGH      0x94
   98 
   99 #define IOAT_CHANCMP_OFFSET_LOW         0x98
  100 #define IOAT_CHANCMP_OFFSET_HIGH        0x9C
  101 
  102 #define IOAT_CHANERR_OFFSET             0xA8
  103 
  104 #define IOAT_CHANERR_XSADDERR           (1 << 0)
  105 #define IOAT_CHANERR_XDADDERR           (1 << 1)
  106 #define IOAT_CHANERR_NDADDERR           (1 << 2)
  107 #define IOAT_CHANERR_DERR               (1 << 3)
  108 #define IOAT_CHANERR_CHADDERR           (1 << 4)
  109 #define IOAT_CHANERR_CCMDERR            (1 << 5)
  110 #define IOAT_CHANERR_CUNCORERR          (1 << 6)
  111 #define IOAT_CHANERR_DUNCORERR          (1 << 7)
  112 #define IOAT_CHANERR_RDERR              (1 << 8)
  113 #define IOAT_CHANERR_WDERR              (1 << 9)
  114 #define IOAT_CHANERR_DCERR              (1 << 10)
  115 #define IOAT_CHANERR_DXSERR             (1 << 11)
  116 #define IOAT_CHANERR_CMPADDERR          (1 << 12)
  117 #define IOAT_CHANERR_INTCFGERR          (1 << 13)
  118 #define IOAT_CHANERR_SEDERR             (1 << 14)
  119 #define IOAT_CHANERR_UNAFFERR           (1 << 15)
  120 #define IOAT_CHANERR_CXPERR             (1 << 16)
  121 /* Reserved.                            (1 << 17) */
  122 #define IOAT_CHANERR_DCNTERR            (1 << 18)
  123 #define IOAT_CHANERR_DIFFERR            (1 << 19)
  124 #define IOAT_CHANERR_GTVERR             (1 << 20)
  125 #define IOAT_CHANERR_ATVERR             (1 << 21)
  126 #define IOAT_CHANERR_RTVERR             (1 << 22)
  127 #define IOAT_CHANERR_BBERR              (1 << 23)
  128 #define IOAT_CHANERR_RDIFFERR           (1 << 24)
  129 #define IOAT_CHANERR_RGTVERR            (1 << 25)
  130 #define IOAT_CHANERR_RATVERR            (1 << 26)
  131 #define IOAT_CHANERR_RRTVERR            (1 << 27)
  132 
  133 #define IOAT_CHANERR_STR \
  134     "\2\34RRTVERR\33RATVERR\32RGTVERR\31RDIFFERR\30BBERR\27RTVERR\26ATVERR" \
  135     "\25GTVERR\24DIFFERR\23DCNTERR\21CXPERR\20UNAFFERR\17SEDERR\16INTCFGERR" \
  136     "\15CMPADDERR\14DXSERR\13DCERR\12WDERR\11RDERR\10DUNCORERR\07CUNCORERR" \
  137     "\06CCMDERR\05CHADDERR\04DERR\03NDADDERR\02XDADDERR\01XSADDERR"
  138 
  139 
  140 #define IOAT_CFG_CHANERR_INT_OFFSET             0x180
  141 #define IOAT_CFG_CHANERRMASK_INT_OFFSET         0x184
  142 
  143 #define IOAT_MIN_ORDER                  4
  144 #define IOAT_MAX_ORDER                  16
  145 
  146 #endif /* __IOAT_HW_H__ */

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FreeBSD/Linux Kernel Cross Reference sys/dev/ioat/ioat_hw.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/ioat/ioat_hw.h