The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ips/ipsreg.h

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    1 /*-
    2  * Copyright (c) 2002 Adaptec Inc.
    3  * All rights reserved.
    4  *
    5  * Written by: David Jeffery
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD: releng/10.3/sys/dev/ips/ipsreg.h 163024 2006-10-05 07:28:43Z maxim $
   29  */
   30 
   31 #include <sys/param.h>
   32 
   33 /*
   34  *   IPS CONSTANTS
   35  */
   36 #define IPS_VENDOR_ID                   0x1014
   37 #define IPS_VENDOR_ID_ADAPTEC           0x9005
   38 #define IPS_MORPHEUS_DEVICE_ID          0x01BD
   39 #define IPS_COPPERHEAD_DEVICE_ID        0x002E
   40 #define IPS_MARCO_DEVICE_ID             0x0250
   41 #define IPS_CSL                         0xff
   42 #define IPS_POCL                        0x30
   43 
   44 /* amounts of memory to allocate for certain commands */
   45 #define IPS_ADAPTER_INFO_LEN            (sizeof(ips_adapter_info_t))
   46 #define IPS_DRIVE_INFO_LEN              (sizeof(ips_drive_info_t)) 
   47 #define IPS_COMMAND_LEN                 24
   48 #define IPS_MAX_SG_LEN                  (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS)
   49 #define IPS_NVRAM_PAGE_SIZE             128
   50 /* various flags */
   51 #define IPS_STATIC_FLAG                 0x01
   52 
   53 /* states for the card to be in */
   54 #define IPS_DEV_OPEN                    0x01
   55 #define IPS_TIMEOUT                     0x02 /* command time out, need reset */
   56 #define IPS_OFFLINE                     0x04 /* can't reset card/card failure */
   57 #define IPS_STATIC_BUSY                 0x08
   58 
   59 /* max number of commands set to something low for now */
   60 #define IPS_MAX_CMD_NUM                 128     
   61 #define IPS_MAX_NUM_DRIVES              8
   62 #define IPS_MAX_SG_ELEMENTS             32
   63 #define IPS_MAX_IOBUF_SIZE              (64 * 1024)
   64 #define IPS_BLKSIZE                     512
   65 #define IPS_MAX_LD                      8
   66 #define IPS_MAX_CHANNELS                4
   67 #define IPS_MAX_TARGETS                 15
   68 #define IPS_MAX_CHUNKS                  16
   69 
   70 /* logical drive states */
   71 
   72 #define IPS_LD_OFFLINE                  0x02
   73 #define IPS_LD_OKAY                     0x03
   74 #define IPS_LD_DEGRADED                 0x04
   75 #define IPS_LD_FREE                     0x00
   76 #define IPS_LD_SYS                      0x06
   77 #define IPS_LD_CRS                      0x24
   78 
   79 /* register offsets */
   80 #define MORPHEUS_REG_OMR0               0x0018 /* Outbound Msg. Reg. 0 */
   81 #define MORPHEUS_REG_OMR1               0x001C /* Outbound Msg. Reg. 1 */
   82 #define MORPHEUS_REG_IDR                0x0020 /* Inbound Doorbell Reg. */
   83 #define MORPHEUS_REG_IISR               0x0024 /* Inbound IRQ Status Reg. */
   84 #define MORPHEUS_REG_IIMR               0x0028 /* Inbound IRQ Mask Reg. */
   85 #define MORPHEUS_REG_OISR               0x0030 /* Outbound IRQ Status Reg. */
   86 #define MORPHEUS_REG_OIMR               0x0034 /* Outbound IRQ Mask Reg. */
   87 #define MORPHEUS_REG_IQPR               0x0040 /* Inbound Queue Port Reg. */
   88 #define MORPHEUS_REG_OQPR               0x0044 /* Outbound Queue Port Reg. */
   89 
   90 #define COPPER_REG_SCPR                 0x05    /* Subsystem Ctrl. Port Reg. */
   91 #define COPPER_REG_ISPR                 0x06    /* IRQ Status Port Reg. */
   92 #define COPPER_REG_CBSP                 0x07    /* ? Reg. */
   93 #define COPPER_REG_HISR                 0x08    /* Host IRQ Status Reg.    */
   94 #define COPPER_REG_CCSAR                0x10    /* Cmd. Channel Sys Addr Reg.*/
   95 #define COPPER_REG_CCCR                 0x14    /* Cmd. Channel Ctrl. Reg. */
   96 #define COPPER_REG_SQHR                 0x20    /* Status Queue Head Reg.  */
   97 #define COPPER_REG_SQTR                 0x24    /* Status Queue Tail Reg.  */
   98 #define COPPER_REG_SQER                 0x28    /* Status Queue End Reg.   */
   99 #define COPPER_REG_SQSR                 0x2C    /* Status Queue Start Reg. */
  100 
  101 /* bit definitions */
  102 #define MORPHEUS_BIT_POST1              0x01
  103 #define MORPHEUS_BIT_POST2              0x02
  104 #define MORPHEUS_BIT_CMD_IRQ            0x08
  105 
  106 #define COPPER_CMD_START                0x101A
  107 #define COPPER_SEM_BIT                  0x08
  108 #define COPPER_EI_BIT                   0x80
  109 #define COPPER_EBM_BIT                  0x02
  110 #define COPPER_RESET_BIT                0x80
  111 #define COPPER_GHI_BIT                  0x04
  112 #define COPPER_SCE_BIT                  0x01
  113 #define COPPER_OP_BIT                   0x01
  114 #define COPPER_ILE_BIT                  0x10
  115 
  116 /* status defines */
  117 #define IPS_POST1_OK                    0x8000
  118 #define IPS_POST2_OK                    0x000f
  119 
  120 /* command op codes */
  121 #define IPS_READ_CMD                    0x02
  122 #define IPS_WRITE_CMD                   0x03
  123 #define IPS_ADAPTER_INFO_CMD            0x05
  124 #define IPS_CACHE_FLUSH_CMD             0x0A
  125 #define IPS_REBUILD_STATUS_CMD          0x0C
  126 #define IPS_ERROR_TABLE_CMD             0x17
  127 #define IPS_DRIVE_INFO_CMD              0x19
  128 #define IPS_CMD_READ_CONF               0x38
  129 #define IPS_SUBSYS_PARAM_CMD            0x40
  130 #define IPS_CONFIG_SYNC_CMD             0x58
  131 #define IPS_SG_READ_CMD                 0x82
  132 #define IPS_SG_WRITE_CMD                0x83
  133 #define IPS_RW_NVRAM_CMD                0xBC
  134 #define IPS_FFDC_CMD                    0xD7
  135 
  136 /* basic_status information returned by the adapter */
  137 #define IPS_MIN_ERROR                   0x02
  138 #define IPS_BASIC_STATUS_MASK           0xFF
  139 #define IPS_GSC_STATUS_MASK             0x0F
  140 #define IPS_CMD_SUCCESS                 0x00
  141 #define IPS_CMD_RECOVERED_ERROR         0x01
  142 #define IPS_DRV_ERROR                   0x02    /* Driver supplied error */
  143 #define IPS_INVAL_OPCO                  0x03
  144 #define IPS_INVAL_CMD_BLK               0x04
  145 #define IPS_INVAL_PARM_BLK              0x05
  146 #define IPS_BUSY                        0x08
  147 #define IPS_CMD_CMPLT_WERROR            0x0C
  148 #define IPS_LD_ERROR                    0x0D
  149 #define IPS_CMD_TIMEOUT                 0x0E
  150 #define IPS_PHYS_DRV_ERROR              0x0F
  151 
  152 /* extended_status information returned by the adapter */
  153 #define IPS_ERR_SEL_TO                  0xF0
  154 #define IPS_ERR_OU_RUN                  0xF2
  155 #define IPS_ERR_HOST_RESET              0xF7
  156 #define IPS_ERR_DEV_RESET               0xF8
  157 #define IPS_ERR_RECOVERY                0xFC
  158 #define IPS_ERR_CKCOND                  0xFF
  159 
  160 #define IPS_OS_FREEBSD                  8
  161 #define IPS_VERSION_MAJOR               "0.90"
  162 #define IPS_VERSION_MINOR               ".10"
  163 
  164 /* Adapter Types */
  165 #define IPS_ADAPTER_COPPERHEAD          0x01
  166 #define IPS_ADAPTER_COPPERHEAD2         0x02
  167 #define IPS_ADAPTER_COPPERHEADOB1       0x03
  168 #define IPS_ADAPTER_COPPERHEADOB2       0x04
  169 #define IPS_ADAPTER_CLARINET            0x05
  170 #define IPS_ADAPTER_CLARINETLITE        0x06
  171 #define IPS_ADAPTER_TROMBONE            0x07
  172 #define IPS_ADAPTER_MORPHEUS            0x08
  173 #define IPS_ADAPTER_MORPHEUSLITE        0x09
  174 #define IPS_ADAPTER_NEO                 0x0A
  175 #define IPS_ADAPTER_NEOLITE             0x0B
  176 #define IPS_ADAPTER_SARASOTA2           0x0C
  177 #define IPS_ADAPTER_SARASOTA1           0x0D
  178 #define IPS_ADAPTER_MARCO               0x0E
  179 #define IPS_ADAPTER_SEBRING             0x0F
  180 #define IPS_ADAPTER_7T                  0x10
  181 #define IPS_ADAPTER_7K                  0x11
  182 #define IPS_ADAPTER_7M                  0x12
  183 #define IPS_ADAPTER_MAX_T               IPS_ADAPTER_7M
  184 
  185 /* values for ffdc_settime (from gmtime) */
  186 #define IPS_SECSPERMIN      60
  187 #define IPS_MINSPERHOUR     60
  188 #define IPS_HOURSPERDAY     24
  189 #define IPS_DAYSPERWEEK     7
  190 #define IPS_DAYSPERNYEAR    365
  191 #define IPS_DAYSPERLYEAR    366
  192 #define IPS_SECSPERHOUR     (IPS_SECSPERMIN * IPS_MINSPERHOUR)
  193 #define IPS_SECSPERDAY      ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY)
  194 #define IPS_MONSPERYEAR     12
  195 #define IPS_EPOCH_YEAR      1970
  196 #define IPS_LEAPS_THRU_END_OF(y)    ((y) / 4 - (y) / 100 + (y) / 400)
  197 #define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
  198 
  199 /*
  200  *   IPS STRUCTS
  201  */
  202 
  203 typedef struct{
  204         u_int8_t        command;
  205         u_int8_t        id;
  206         u_int8_t        drivenum;
  207         u_int8_t        reserve2;
  208         u_int32_t       lba;
  209         u_int32_t       buffaddr;
  210         u_int32_t       reserve3;
  211 } __attribute__ ((packed)) ips_generic_cmd;
  212 
  213 typedef struct{
  214         u_int8_t        command;
  215         u_int8_t        id;
  216         u_int8_t        drivenum;
  217         u_int8_t        segnum;
  218         u_int32_t       lba;
  219         u_int32_t       buffaddr;
  220         u_int16_t       length;
  221         u_int16_t       reserve1;
  222 } __attribute__ ((packed)) ips_io_cmd;
  223 
  224 typedef struct{
  225         u_int8_t        command;
  226         u_int8_t        id;
  227         u_int8_t        pagenum;
  228         u_int8_t        rw;
  229         u_int32_t       reserve1;
  230         u_int32_t       buffaddr;
  231         u_int32_t       reserve3;
  232 } __attribute__ ((packed)) ips_rw_nvram_cmd;
  233 
  234 typedef struct{
  235         u_int8_t        command;
  236         u_int8_t        id;
  237         u_int8_t        drivenum;
  238         u_int8_t        reserve1;
  239         u_int32_t       reserve2;
  240         u_int32_t       buffaddr;
  241         u_int32_t       reserve3;
  242 } __attribute__ ((packed)) ips_drive_cmd;
  243 
  244 typedef struct{
  245         u_int8_t        command;
  246         u_int8_t        id;
  247         u_int8_t        reserve1;
  248         u_int8_t        commandtype;
  249         u_int32_t       reserve2;
  250         u_int32_t       buffaddr;
  251         u_int32_t       reserve3;
  252 } __attribute__((packed)) ips_adapter_info_cmd;
  253 
  254 typedef struct{
  255         u_int8_t        command;
  256         u_int8_t        id;
  257         u_int8_t        reset_count;
  258         u_int8_t        reset_type;
  259         u_int8_t        second;
  260         u_int8_t        minute;
  261         u_int8_t        hour;
  262         u_int8_t        day;
  263         u_int8_t        reserve1[4];
  264         u_int8_t        month;
  265         u_int8_t        yearH;
  266         u_int8_t        yearL;
  267         u_int8_t        reserve2;
  268 } __attribute__((packed)) ips_adapter_ffdc_cmd;
  269 
  270 typedef union{
  271         ips_generic_cmd         generic_cmd;
  272         ips_drive_cmd           drive_cmd;
  273         ips_adapter_info_cmd    adapter_info_cmd;
  274 } ips_cmd_buff_t;
  275 
  276 typedef struct {
  277    u_int32_t  signature;
  278    u_int8_t   reserved;
  279    u_int8_t   adapter_slot;
  280    u_int16_t  adapter_type;
  281    u_int8_t   bios_high[4];
  282    u_int8_t   bios_low[4];
  283    u_int16_t  reserve2;
  284    u_int8_t   reserve3;
  285    u_int8_t   operating_system;
  286    u_int8_t   driver_high[4];
  287    u_int8_t   driver_low[4];
  288    u_int8_t   reserve4[100];
  289 }__attribute__((packed)) ips_nvram_page5;
  290 
  291 typedef struct{
  292         u_int32_t       addr;
  293         u_int32_t       len;
  294 } ips_sg_element_t;
  295 
  296 typedef struct{
  297         u_int8_t        drivenum;
  298         u_int8_t        merge_id;
  299         u_int8_t        raid_lvl;
  300         u_int8_t        state;
  301         u_int32_t       sector_count;
  302 } __attribute__((packed)) ips_drive_t;
  303 
  304 typedef struct{
  305         u_int8_t        drivecount;
  306         u_int8_t        reserve1;
  307         u_int16_t       reserve2;
  308         ips_drive_t drives[IPS_MAX_NUM_DRIVES];
  309 }__attribute__((packed)) ips_drive_info_t;
  310 
  311 typedef struct{
  312         u_int8_t        drivecount;
  313         u_int8_t        miscflags;
  314         u_int8_t        SLTflags;
  315         u_int8_t        BSTflags;
  316         u_int8_t        pwr_chg_count;
  317         u_int8_t        wrong_addr_count;
  318         u_int8_t        unident_count;
  319         u_int8_t        nvram_dev_chg_count;
  320         u_int8_t        codeblock_version[8];
  321         u_int8_t        bootblock_version[8];
  322         u_int32_t       drive_sector_count[IPS_MAX_NUM_DRIVES];
  323         u_int8_t        max_concurrent_cmds;
  324         u_int8_t        max_phys_devices;
  325         u_int16_t       flash_prog_count;
  326         u_int8_t        defunct_disks;
  327         u_int8_t        rebuildflags;
  328         u_int8_t        offline_drivecount;
  329         u_int8_t        critical_drivecount;
  330         u_int16_t       config_update_count;
  331         u_int8_t        blockedflags;
  332         u_int8_t        psdn_error;
  333         u_int16_t       addr_dead_disk[IPS_MAX_CHANNELS][IPS_MAX_TARGETS];
  334 }__attribute__((packed)) ips_adapter_info_t;
  335 
  336 typedef struct {
  337         u_int8_t        initiator;
  338         u_int8_t        parameters;
  339         u_int8_t        miscflag;
  340         u_int8_t        state;
  341         u_int32_t       blkcount;
  342         u_int8_t        deviceid[28];
  343 } __attribute__((packed)) ips_devstate_t;
  344 
  345 /*
  346  * The states that a physical drive can be in.  The 'present' value can be
  347  * OR'd with the other values.
  348  */
  349 #define IPS_DEVSTATE_PRESENT    0x81
  350 #define IPS_DEVSTATE_REBUILD    0x02
  351 #define IPS_DEVSTATE_SPARE      0x04
  352 #define IPS_DEVSTATE_MEMBER     0x08
  353 
  354 typedef struct {
  355         u_int8_t        channel;
  356         u_int8_t        target;
  357         u_int16_t       reserved;
  358         u_int32_t       startsectors;
  359         u_int32_t       numsectors;
  360 } __attribute__((packed)) ips_chunk_t;
  361 
  362 typedef struct {
  363         u_int16_t       userfield;
  364         u_int8_t        state;
  365         u_int8_t        raidcacheparam;
  366         u_int8_t        numchunkunits;
  367         u_int8_t        stripesize;
  368         u_int8_t        params;
  369         u_int8_t        reserved;
  370         u_int32_t       ldsize;
  371         ips_chunk_t     chunk[IPS_MAX_CHUNKS];
  372 } __attribute__((packed)) ips_ld_t;
  373 
  374 typedef struct {
  375         u_int8_t        boarddisc[8];
  376         u_int8_t        processor[8];
  377         u_int8_t        numchantype;
  378         u_int8_t        numhostinttype;
  379         u_int8_t        compression;
  380         u_int8_t        nvramtype;
  381         u_int32_t       nvramsize;
  382 } __attribute__((packed)) ips_hardware_t;
  383 
  384 typedef struct {
  385         u_int8_t        ldcount;
  386         u_int8_t        day;
  387         u_int8_t        month;
  388         u_int8_t        year;
  389         u_int8_t        initiatorid[4];
  390         u_int8_t        hostid[12];
  391         u_int8_t        timesign[8];
  392         u_int32_t       useropt;
  393         u_int16_t       userfield;
  394         u_int8_t        rebuildrate;
  395         u_int8_t        reserve;
  396         ips_hardware_t  hardwaredisc;
  397         ips_ld_t        ld[IPS_MAX_LD];
  398         ips_devstate_t  dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
  399         u_int8_t        reserved[512];
  400 } __attribute__((packed)) ips_conf_t;
  401 
  402 typedef union {
  403    struct {
  404       u_int8_t  reserved;
  405       u_int8_t  command_id;
  406       u_int8_t  basic_status;
  407       u_int8_t  extended_status;
  408    } fields;
  409    volatile u_int32_t    value;
  410 } ips_cmd_status_t;
  411 

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