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sys/dev/irdma/irdma_user.h
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1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_USER_H 37 #define IRDMA_USER_H 38 39 #define irdma_handle void * 40 #define irdma_adapter_handle irdma_handle 41 #define irdma_qp_handle irdma_handle 42 #define irdma_cq_handle irdma_handle 43 #define irdma_pd_id irdma_handle 44 #define irdma_stag_handle irdma_handle 45 #define irdma_stag_index u32 46 #define irdma_stag u32 47 #define irdma_stag_key u8 48 #define irdma_tagged_offset u64 49 #define irdma_access_privileges u32 50 #define irdma_physical_fragment u64 51 #define irdma_address_list u64 * 52 #define irdma_sgl struct irdma_sge * 53 54 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL 55 56 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 57 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 58 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 59 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05 60 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 61 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a 62 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10 63 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 64 #define IRDMA_ACCESS_FLAGS_ALL 0x3f 65 66 #define IRDMA_OP_TYPE_RDMA_WRITE 0x00 67 #define IRDMA_OP_TYPE_RDMA_READ 0x01 68 #define IRDMA_OP_TYPE_SEND 0x03 69 #define IRDMA_OP_TYPE_SEND_INV 0x04 70 #define IRDMA_OP_TYPE_SEND_SOL 0x05 71 #define IRDMA_OP_TYPE_SEND_SOL_INV 0x06 72 #define IRDMA_OP_TYPE_RDMA_WRITE_SOL 0x0d 73 #define IRDMA_OP_TYPE_BIND_MW 0x08 74 #define IRDMA_OP_TYPE_FAST_REG_NSMR 0x09 75 #define IRDMA_OP_TYPE_INV_STAG 0x0a 76 #define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b 77 #define IRDMA_OP_TYPE_NOP 0x0c 78 #define IRDMA_OP_TYPE_REC 0x3e 79 #define IRDMA_OP_TYPE_REC_IMM 0x3f 80 81 #define IRDMA_FLUSH_MAJOR_ERR 1 82 #define IRDMA_SRQFLUSH_RSVD_MAJOR_ERR 0xfffe 83 84 /* Async Events codes */ 85 #define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102 86 #define IRDMA_AE_AMP_INVALID_STAG 0x0103 87 #define IRDMA_AE_AMP_BAD_QP 0x0104 88 #define IRDMA_AE_AMP_BAD_PD 0x0105 89 #define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106 90 #define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107 91 #define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108 92 #define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109 93 #define IRDMA_AE_AMP_TO_WRAP 0x010a 94 #define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c 95 #define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d 96 #define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e 97 #define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 98 #define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111 99 #define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 100 #define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 101 #define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114 102 #define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115 103 #define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 104 #define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117 105 #define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 106 #define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 107 #define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a 108 #define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b 109 #define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c 110 #define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d 111 #define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e 112 #define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f 113 #define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120 114 #define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121 115 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132 116 #define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133 117 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134 118 #define IRDMA_AE_UDA_L4LEN_INVALID 0x0135 119 #define IRDMA_AE_BAD_CLOSE 0x0201 120 #define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 121 #define IRDMA_AE_CQ_OPERATION_ERROR 0x0203 122 #define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 123 #define IRDMA_AE_STAG_ZERO_INVALID 0x0206 124 #define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207 125 #define IRDMA_AE_IB_INVALID_REQUEST 0x0208 126 #define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a 127 #define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b 128 #define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c 129 #define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d 130 #define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e 131 #define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220 132 #define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 133 #define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 134 #define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 135 #define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305 136 #define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 137 #define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307 138 #define IRDMA_AE_DDP_NO_L_BIT 0x0308 139 #define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 140 #define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 141 #define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 142 #define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 143 #define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316 144 #define IRDMA_AE_ROCE_EMPTY_MCG 0x0380 145 #define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381 146 #define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382 147 #define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383 148 #define IRDMA_AE_INVALID_ARP_ENTRY 0x0401 149 #define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402 150 #define IRDMA_AE_STALE_ARP_ENTRY 0x0403 151 #define IRDMA_AE_INVALID_AH_ENTRY 0x0406 152 #define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501 153 #define IRDMA_AE_LLP_CONNECTION_RESET 0x0502 154 #define IRDMA_AE_LLP_FIN_RECEIVED 0x0503 155 #define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504 156 #define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 157 #define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507 158 #define IRDMA_AE_LLP_SYN_RECEIVED 0x0508 159 #define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509 160 #define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a 161 #define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b 162 #define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c 163 #define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e 164 #define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520 165 #define IRDMA_AE_RESET_SENT 0x0601 166 #define IRDMA_AE_TERMINATE_SENT 0x0602 167 #define IRDMA_AE_RESET_NOT_SENT 0x0603 168 #define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700 169 #define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 170 #define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702 171 #define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900 172 173 enum irdma_device_caps_const { 174 IRDMA_WQE_SIZE = 4, 175 IRDMA_CQP_WQE_SIZE = 8, 176 IRDMA_CQE_SIZE = 4, 177 IRDMA_EXTENDED_CQE_SIZE = 8, 178 IRDMA_AEQE_SIZE = 2, 179 IRDMA_CEQE_SIZE = 1, 180 IRDMA_CQP_CTX_SIZE = 8, 181 IRDMA_SHADOW_AREA_SIZE = 8, 182 IRDMA_GATHER_STATS_BUF_SIZE = 1024, 183 IRDMA_MIN_IW_QP_ID = 0, 184 IRDMA_QUERY_FPM_BUF_SIZE = 176, 185 IRDMA_COMMIT_FPM_BUF_SIZE = 176, 186 IRDMA_MAX_IW_QP_ID = 262143, 187 IRDMA_MIN_CEQID = 0, 188 IRDMA_MAX_CEQID = 1023, 189 IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, 190 IRDMA_MIN_CQID = 0, 191 IRDMA_MAX_CQID = 524287, 192 IRDMA_MIN_AEQ_ENTRIES = 1, 193 IRDMA_MAX_AEQ_ENTRIES = 524287, 194 IRDMA_MIN_CEQ_ENTRIES = 1, 195 IRDMA_MAX_CEQ_ENTRIES = 262143, 196 IRDMA_MIN_CQ_SIZE = 1, 197 IRDMA_MAX_CQ_SIZE = 1048575, 198 IRDMA_DB_ID_ZERO = 0, 199 /* 64K + 1 */ 200 IRDMA_MAX_OUTBOUND_MSG_SIZE = 65537, 201 /* 64K +1 */ 202 IRDMA_MAX_INBOUND_MSG_SIZE = 65537, 203 IRDMA_MAX_PUSH_PAGE_COUNT = 1024, 204 IRDMA_MAX_PE_ENA_VF_COUNT = 32, 205 IRDMA_MAX_VF_FPM_ID = 47, 206 IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, 207 IRDMA_MAX_INLINE_DATA_SIZE = 101, 208 IRDMA_MAX_WQ_ENTRIES = 32768, 209 IRDMA_Q2_BUF_SIZE = 256, 210 IRDMA_QP_CTX_SIZE = 256, 211 IRDMA_MAX_PDS = 262144, 212 IRDMA_MIN_WQ_SIZE_GEN2 = 8, 213 }; 214 215 enum irdma_addressing_type { 216 IRDMA_ADDR_TYPE_ZERO_BASED = 0, 217 IRDMA_ADDR_TYPE_VA_BASED = 1, 218 }; 219 220 enum irdma_flush_opcode { 221 FLUSH_INVALID = 0, 222 FLUSH_GENERAL_ERR, 223 FLUSH_PROT_ERR, 224 FLUSH_REM_ACCESS_ERR, 225 FLUSH_LOC_QP_OP_ERR, 226 FLUSH_REM_OP_ERR, 227 FLUSH_LOC_LEN_ERR, 228 FLUSH_FATAL_ERR, 229 FLUSH_RETRY_EXC_ERR, 230 FLUSH_MW_BIND_ERR, 231 FLUSH_REM_INV_REQ_ERR, 232 }; 233 234 enum irdma_qp_event_type { 235 IRDMA_QP_EVENT_CATASTROPHIC, 236 IRDMA_QP_EVENT_ACCESS_ERR, 237 IRDMA_QP_EVENT_REQ_ERR, 238 }; 239 240 enum irdma_cmpl_status { 241 IRDMA_COMPL_STATUS_SUCCESS = 0, 242 IRDMA_COMPL_STATUS_FLUSHED, 243 IRDMA_COMPL_STATUS_INVALID_WQE, 244 IRDMA_COMPL_STATUS_QP_CATASTROPHIC, 245 IRDMA_COMPL_STATUS_REMOTE_TERMINATION, 246 IRDMA_COMPL_STATUS_INVALID_STAG, 247 IRDMA_COMPL_STATUS_BASE_BOUND_VIOLATION, 248 IRDMA_COMPL_STATUS_ACCESS_VIOLATION, 249 IRDMA_COMPL_STATUS_INVALID_PD_ID, 250 IRDMA_COMPL_STATUS_WRAP_ERROR, 251 IRDMA_COMPL_STATUS_STAG_INVALID_PDID, 252 IRDMA_COMPL_STATUS_RDMA_READ_ZERO_ORD, 253 IRDMA_COMPL_STATUS_QP_NOT_PRIVLEDGED, 254 IRDMA_COMPL_STATUS_STAG_NOT_INVALID, 255 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_SIZE, 256 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_ENTRY, 257 IRDMA_COMPL_STATUS_INVALID_FBO, 258 IRDMA_COMPL_STATUS_INVALID_LEN, 259 IRDMA_COMPL_STATUS_INVALID_ACCESS, 260 IRDMA_COMPL_STATUS_PHYS_BUF_LIST_TOO_LONG, 261 IRDMA_COMPL_STATUS_INVALID_VIRT_ADDRESS, 262 IRDMA_COMPL_STATUS_INVALID_REGION, 263 IRDMA_COMPL_STATUS_INVALID_WINDOW, 264 IRDMA_COMPL_STATUS_INVALID_TOTAL_LEN, 265 IRDMA_COMPL_STATUS_UNKNOWN, 266 }; 267 268 enum irdma_cmpl_notify { 269 IRDMA_CQ_COMPL_EVENT = 0, 270 IRDMA_CQ_COMPL_SOLICITED = 1, 271 }; 272 273 enum irdma_qp_caps { 274 IRDMA_WRITE_WITH_IMM = 1, 275 IRDMA_SEND_WITH_IMM = 2, 276 IRDMA_ROCE = 4, 277 IRDMA_PUSH_MODE = 8, 278 }; 279 280 struct irdma_qp_uk; 281 struct irdma_cq_uk; 282 struct irdma_qp_uk_init_info; 283 struct irdma_cq_uk_init_info; 284 285 struct irdma_sge { 286 irdma_tagged_offset tag_off; 287 u32 len; 288 irdma_stag stag; 289 }; 290 291 struct irdma_ring { 292 volatile u32 head; 293 volatile u32 tail; /* effective tail */ 294 u32 size; 295 }; 296 297 struct irdma_cqe { 298 __le64 buf[IRDMA_CQE_SIZE]; 299 }; 300 301 struct irdma_extended_cqe { 302 __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; 303 }; 304 305 struct irdma_post_send { 306 irdma_sgl sg_list; 307 u32 num_sges; 308 u32 qkey; 309 u32 dest_qp; 310 u32 ah_id; 311 }; 312 313 struct irdma_post_rq_info { 314 u64 wr_id; 315 irdma_sgl sg_list; 316 u32 num_sges; 317 }; 318 319 struct irdma_rdma_write { 320 irdma_sgl lo_sg_list; 321 u32 num_lo_sges; 322 struct irdma_sge rem_addr; 323 }; 324 325 struct irdma_rdma_read { 326 irdma_sgl lo_sg_list; 327 u32 num_lo_sges; 328 struct irdma_sge rem_addr; 329 }; 330 331 struct irdma_bind_window { 332 irdma_stag mr_stag; 333 u64 bind_len; 334 void *va; 335 enum irdma_addressing_type addressing_type; 336 bool ena_reads:1; 337 bool ena_writes:1; 338 irdma_stag mw_stag; 339 bool mem_window_type_1:1; 340 }; 341 342 struct irdma_inv_local_stag { 343 irdma_stag target_stag; 344 }; 345 346 struct irdma_post_sq_info { 347 u64 wr_id; 348 u8 op_type; 349 u8 l4len; 350 bool signaled:1; 351 bool read_fence:1; 352 bool local_fence:1; 353 bool inline_data:1; 354 bool imm_data_valid:1; 355 bool push_wqe:1; 356 bool report_rtt:1; 357 bool udp_hdr:1; 358 bool defer_flag:1; 359 u32 imm_data; 360 u32 stag_to_inv; 361 union { 362 struct irdma_post_send send; 363 struct irdma_rdma_write rdma_write; 364 struct irdma_rdma_read rdma_read; 365 struct irdma_bind_window bind_window; 366 struct irdma_inv_local_stag inv_local_stag; 367 } op; 368 }; 369 370 struct irdma_cq_poll_info { 371 u64 wr_id; 372 irdma_qp_handle qp_handle; 373 u32 bytes_xfered; 374 u32 qp_id; 375 u32 ud_src_qpn; 376 u32 imm_data; 377 irdma_stag inv_stag; /* or L_R_Key */ 378 enum irdma_cmpl_status comp_status; 379 u16 major_err; 380 u16 minor_err; 381 u16 ud_vlan; 382 u8 ud_smac[6]; 383 u8 op_type; 384 u8 q_type; 385 bool stag_invalid_set:1; /* or L_R_Key set */ 386 bool push_dropped:1; 387 bool error:1; 388 bool solicited_event:1; 389 bool ipv4:1; 390 bool ud_vlan_valid:1; 391 bool ud_smac_valid:1; 392 bool imm_valid:1; 393 bool signaled:1; 394 union { 395 u32 tcp_sqn; 396 u32 roce_psn; 397 u32 rtt; 398 u32 raw; 399 } stat; 400 }; 401 402 struct qp_err_code { 403 enum irdma_flush_opcode flush_code; 404 enum irdma_qp_event_type event_type; 405 }; 406 407 int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 408 struct irdma_post_sq_info *info, bool post_sq); 409 int irdma_uk_inline_send(struct irdma_qp_uk *qp, 410 struct irdma_post_sq_info *info, bool post_sq); 411 int irdma_uk_mw_bind(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 412 bool post_sq); 413 int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, 414 bool post_sq); 415 int irdma_uk_post_receive(struct irdma_qp_uk *qp, 416 struct irdma_post_rq_info *info); 417 void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp); 418 int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 419 bool inv_stag, bool post_sq); 420 int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 421 bool post_sq); 422 int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 423 bool post_sq); 424 int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 425 struct irdma_post_sq_info *info, 426 bool post_sq); 427 428 struct irdma_wqe_uk_ops { 429 void (*iw_copy_inline_data)(u8 *dest, struct irdma_sge *sge_list, u32 num_sges, u8 polarity); 430 u16 (*iw_inline_data_size_to_quanta)(u32 data_size); 431 void (*iw_set_fragment)(__le64 *wqe, u32 offset, struct irdma_sge *sge, 432 u8 valid); 433 void (*iw_set_mw_bind_wqe)(__le64 *wqe, 434 struct irdma_bind_window *op_info); 435 }; 436 437 int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 438 struct irdma_cq_poll_info *info); 439 void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 440 enum irdma_cmpl_notify cq_notify); 441 void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int size); 442 void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt); 443 int irdma_uk_cq_init(struct irdma_cq_uk *cq, 444 struct irdma_cq_uk_init_info *info); 445 int irdma_uk_qp_init(struct irdma_qp_uk *qp, 446 struct irdma_qp_uk_init_info *info); 447 void irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, 448 u8 *rq_shift); 449 int irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, 450 u32 *sq_depth, u8 *sq_shift); 451 int irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, 452 u32 *rq_depth, u8 *rq_shift); 453 struct irdma_sq_uk_wr_trk_info { 454 u64 wrid; 455 u32 wr_len; 456 u16 quanta; 457 u8 signaled; 458 u8 reserved[1]; 459 }; 460 461 struct irdma_qp_quanta { 462 __le64 elem[IRDMA_WQE_SIZE]; 463 }; 464 465 struct irdma_qp_uk { 466 struct irdma_qp_quanta *sq_base; 467 struct irdma_qp_quanta *rq_base; 468 struct irdma_uk_attrs *uk_attrs; 469 u32 IOMEM *wqe_alloc_db; 470 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 471 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 472 u64 *rq_wrid_array; 473 __le64 *shadow_area; 474 __le32 *push_db; 475 __le64 *push_wqe; 476 struct irdma_ring sq_ring; 477 struct irdma_ring sq_sig_ring; 478 struct irdma_ring rq_ring; 479 struct irdma_ring initial_ring; 480 u32 qp_id; 481 u32 qp_caps; 482 u32 sq_size; 483 u32 rq_size; 484 u32 max_sq_frag_cnt; 485 u32 max_rq_frag_cnt; 486 u32 max_inline_data; 487 u32 last_rx_cmpl_idx; 488 u32 last_tx_cmpl_idx; 489 struct irdma_wqe_uk_ops wqe_ops; 490 u16 conn_wqes; 491 u8 qp_type; 492 u8 swqe_polarity; 493 u8 swqe_polarity_deferred; 494 u8 rwqe_polarity; 495 u8 rq_wqe_size; 496 u8 rq_wqe_size_multiplier; 497 bool deferred_flag:1; 498 bool push_mode:1; /* whether the last post wqe was pushed */ 499 bool push_dropped:1; 500 bool first_sq_wq:1; 501 bool sq_flush_complete:1; /* Indicates flush was seen and SQ was empty after the flush */ 502 bool rq_flush_complete:1; /* Indicates flush was seen and RQ was empty after the flush */ 503 bool destroy_pending:1; /* Indicates the QP is being destroyed */ 504 void *back_qp; 505 spinlock_t *lock; 506 u8 dbg_rq_flushed; 507 u16 ord_cnt; 508 u8 sq_flush_seen; 509 u8 rq_flush_seen; 510 u8 rd_fence_rate; 511 }; 512 513 struct irdma_cq_uk { 514 struct irdma_cqe *cq_base; 515 u32 IOMEM *cqe_alloc_db; 516 u32 IOMEM *cq_ack_db; 517 __le64 *shadow_area; 518 u32 cq_id; 519 u32 cq_size; 520 struct irdma_ring cq_ring; 521 u8 polarity; 522 bool armed:1; 523 bool avoid_mem_cflct:1; 524 }; 525 526 struct irdma_qp_uk_init_info { 527 struct irdma_qp_quanta *sq; 528 struct irdma_qp_quanta *rq; 529 struct irdma_uk_attrs *uk_attrs; 530 u32 IOMEM *wqe_alloc_db; 531 __le64 *shadow_area; 532 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 533 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 534 u64 *rq_wrid_array; 535 u32 qp_id; 536 u32 qp_caps; 537 u32 sq_size; 538 u32 rq_size; 539 u32 max_sq_frag_cnt; 540 u32 max_rq_frag_cnt; 541 u32 max_inline_data; 542 u32 sq_depth; 543 u32 rq_depth; 544 u8 first_sq_wq; 545 u8 type; 546 u8 sq_shift; 547 u8 rq_shift; 548 u8 rd_fence_rate; 549 int abi_ver; 550 bool legacy_mode; 551 }; 552 553 struct irdma_cq_uk_init_info { 554 u32 IOMEM *cqe_alloc_db; 555 u32 IOMEM *cq_ack_db; 556 struct irdma_cqe *cq_base; 557 __le64 *shadow_area; 558 u32 cq_size; 559 u32 cq_id; 560 bool avoid_mem_cflct; 561 }; 562 563 __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 564 u16 *quanta, u32 total_size, 565 struct irdma_post_sq_info *info); 566 __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx); 567 int irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); 568 int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq); 569 int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta); 570 int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size); 571 void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 572 u32 inline_data, u8 *shift); 573 int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, u32 *sqdepth); 574 int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, u32 *rqdepth); 575 int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, u32 srq_size, u8 shift, u32 *srqdepth); 576 void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, 577 u32 wqe_idx, bool post_sq); 578 void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx); 579 580 static inline struct qp_err_code irdma_ae_to_qp_err_code(u16 ae_id) 581 { 582 struct qp_err_code qp_err = { 0 }; 583 584 switch (ae_id) { 585 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 586 case IRDMA_AE_AMP_INVALID_STAG: 587 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 588 case IRDMA_AE_AMP_UNALLOCATED_STAG: 589 case IRDMA_AE_AMP_BAD_PD: 590 case IRDMA_AE_AMP_BAD_QP: 591 case IRDMA_AE_AMP_BAD_STAG_KEY: 592 case IRDMA_AE_AMP_BAD_STAG_INDEX: 593 case IRDMA_AE_AMP_TO_WRAP: 594 case IRDMA_AE_PRIV_OPERATION_DENIED: 595 qp_err.flush_code = FLUSH_PROT_ERR; 596 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 597 break; 598 case IRDMA_AE_UDA_XMIT_BAD_PD: 599 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 600 qp_err.flush_code = FLUSH_LOC_QP_OP_ERR; 601 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 602 break; 603 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 604 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 605 case IRDMA_AE_UDA_L4LEN_INVALID: 606 case IRDMA_AE_DDP_UBE_INVALID_MO: 607 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 608 qp_err.flush_code = FLUSH_LOC_LEN_ERR; 609 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 610 break; 611 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 612 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 613 qp_err.flush_code = FLUSH_REM_ACCESS_ERR; 614 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 615 break; 616 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 617 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 618 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 619 case IRDMA_AE_AMP_MWBIND_VALID_STAG: 620 qp_err.flush_code = FLUSH_MW_BIND_ERR; 621 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 622 break; 623 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 624 qp_err.flush_code = FLUSH_RETRY_EXC_ERR; 625 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 626 break; 627 case IRDMA_AE_IB_INVALID_REQUEST: 628 qp_err.flush_code = FLUSH_REM_INV_REQ_ERR; 629 qp_err.event_type = IRDMA_QP_EVENT_REQ_ERR; 630 break; 631 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 632 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 633 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 634 case IRDMA_AE_IB_REMOTE_OP_ERROR: 635 qp_err.flush_code = FLUSH_REM_OP_ERR; 636 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 637 break; 638 case IRDMA_AE_LCE_QP_CATASTROPHIC: 639 qp_err.flush_code = FLUSH_FATAL_ERR; 640 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 641 break; 642 default: 643 qp_err.flush_code = FLUSH_GENERAL_ERR; 644 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 645 break; 646 } 647 648 return qp_err; 649 } 650 #endif /* IRDMA_USER_H */
Cache object: 85d92446386a0366e501695d11c0a6b1
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