FreeBSD/Linux Kernel Cross Reference
sys/dev/isa/if_ecreg.h
1 /* $OpenBSD: if_ecreg.h,v 1.2 2001/01/25 03:50:50 todd Exp $ */
2 /* $NetBSD: if_ecreg.h,v 1.1 1997/11/02 00:44:26 thorpej Exp $ */
3
4 /*
5 * 3Com Etherlink II (3c503) register definitions.
6 *
7 * Copyright (C) 1993, David Greenman. This software may be used, modified,
8 * copied, distributed, and sold, in both source and binary form provided that
9 * the above copyright and these terms are retained. Under no circumstances is
10 * the author responsible for the proper functioning of this software, nor does
11 * the author assume any responsibility for damages incurred with its use.
12 */
13
14 #ifndef _DEV_ISA_IF_ECREG_H_
15 #define _DEV_ISA_IF_ECREG_H_
16
17 #define ELINK2_NIC_OFFSET 0
18 #define ELINK2_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
19
20 /*
21 * XXX - The I/O address range is fragmented in the 3c503; this is the
22 * number of regs at iobase.
23 */
24 #define ELINK2_NIC_PORTS 16
25 #define ELINK2_ASIC_PORTS 16
26
27 /* tx memory starts in second bank on 8bit cards */
28 #define ELINK2_TX_PAGE_OFFSET_8BIT 0x20
29
30 /* tx memory starts in first bank on 16bit cards */
31 #define ELINK2_TX_PAGE_OFFSET_16BIT 0x0
32
33 /* ...and rx memory starts in second bank */
34 #define ELINK2_RX_PAGE_OFFSET_16BIT 0x20
35
36
37 /*
38 * Page Start Register. Must match PSTART in NIC.
39 */
40 #define ELINK2_PSTR 0
41
42 /*
43 * Page Stop Register. Must match PSTOP in NIC.
44 */
45 #define ELINK2_PSPR 1
46
47 /*
48 * DrQ Timer Register. Determines number of bytes to be transferred during a
49 * DMA burst.
50 */
51 #define ELINK2_DQTR 2
52
53 /*
54 * Base Configuration Register. Read-only register which contains the
55 * board-configured I/O base address of the adapter. Bit encoded.
56 */
57 #define ELINK2_BCFR 3
58
59 /*
60 * EPROM Configuration Register. Read-only register which contains the
61 * board-configured memory base address. Bit encoded.
62 */
63 #define ELINK2_PCFR 4
64
65 /*
66 * GA Configuration Register. Gate-Array Configuration Register.
67 *
68 * mbs2 mbs1 mbs0 start address
69 * 0 0 0 0x0000
70 * 0 0 1 0x2000
71 * 0 1 0 0x4000
72 * 0 1 1 0x6000
73 *
74 * Note that with adapters with only 8K, the setting for 0x2000 must always be
75 * used.
76 */
77 #define ELINK2_GACFR 5
78
79 #define ELINK2_GACFR_MBS0 0x01
80 #define ELINK2_GACFR_MBS1 0x02
81 #define ELINK2_GACFR_MBS2 0x04
82
83 #define ELINK2_GACFR_RSEL 0x08 /* enable shared memory */
84 #define ELINK2_GACFR_TEST 0x10 /* for GA testing */
85 #define ELINK2_GACFR_OWS 0x20 /* select 0WS access to GA */
86 #define ELINK2_GACFR_TCM 0x40 /* Mask DMA interrupts */
87 #define ELINK2_GACFR_NIM 0x80 /* Mask NIC interrupts */
88
89 /*
90 * Control Register. Miscellaneous control functions.
91 */
92 #define ELINK2_CR 6
93
94 #define ELINK2_CR_RST 0x01 /* Reset GA and NIC */
95 #define ELINK2_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
96 #define ELINK2_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
97 #define ELINK2_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
98 #define ELINK2_CR_SHARE 0x10 /* select interrupt sharing option */
99 #define ELINK2_CR_DBSEL 0x20 /* Double buffer select */
100 #define ELINK2_CR_DDIR 0x40 /* DMA direction select */
101 #define ELINK2_CR_START 0x80 /* Start DMA controller */
102
103 /*
104 * Status Register. Miscellaneous status information.
105 */
106 #define ELINK2_STREG 7
107
108 #define ELINK2_STREG_REV 0x07 /* GA revision */
109 #define ELINK2_STREG_DIP 0x08 /* DMA in progress */
110 #define ELINK2_STREG_DTC 0x10 /* DMA terminal count */
111 #define ELINK2_STREG_OFLW 0x20 /* Overflow */
112 #define ELINK2_STREG_UFLW 0x40 /* Underflow */
113 #define ELINK2_STREG_DPRDY 0x80 /* Data port ready */
114
115 /*
116 * Interrupt/DMA Configuration Register
117 */
118 #define ELINK2_IDCFR 8
119
120 #define ELINK2_IDCFR_DRQ 0x07 /* DMA request */
121 #define ELINK2_IDCFR_UNUSED 0x08 /* not used */
122 #if 0
123 #define ELINK2_IDCFR_IRQ 0xF0 /* Interrupt request */
124 #else
125 #define ELINK2_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
126 #define ELINK2_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
127 #define ELINK2_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
128 #define ELINK2_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
129 #endif
130
131 /*
132 * DMA Address Register MSB
133 */
134 #define ELINK2_DAMSB 9
135
136 /*
137 * DMA Address Register LSB
138 */
139 #define ELINK2_DALSB 0x0a
140
141 /*
142 * Vector Pointer Register 2
143 */
144 #define ELINK2_VPTR2 0x0b
145
146 /*
147 * Vector Pointer Register 1
148 */
149 #define ELINK2_VPTR1 0x0c
150
151 /*
152 * Vector Pointer Register 0
153 */
154 #define ELINK2_VPTR0 0x0d
155
156 /*
157 * Register File Access MSB
158 */
159 #define ELINK2_RFMSB 0x0e
160
161 /*
162 * Register File Access LSB
163 */
164 #define ELINK2_RFLSB 0x0f
165
166 #endif /* _DEV_ISA_IF_ECREG_H_ */
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