The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/isa/moxa_isa.c

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    1 /*      $NetBSD: moxa_isa.c,v 1.8 2003/10/27 07:14:25 chs Exp $ */
    2 
    3 /*
    4  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
    5  * Copyright (c) 1995 Charles M. Hannum.  All rights reserved.
    6  *
    7  * This code is derived from public-domain software written by
    8  * Roland McGrath.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by Charles M. Hannum.
   21  * 4. The name of the author may not be used to endorse or promote products
   22  *    derived from this software without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __KERNEL_RCSID(0, "$NetBSD: moxa_isa.c,v 1.8 2003/10/27 07:14:25 chs Exp $");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/device.h>
   42 #include <sys/termios.h>
   43 
   44 #include <machine/bus.h>
   45 #include <machine/intr.h>
   46 
   47 #include <dev/ic/comreg.h>
   48 #include <dev/ic/comvar.h>
   49 
   50 #include <dev/isa/isavar.h>
   51 #include <dev/isa/com_multi.h>
   52 
   53 #define NSLAVES 8
   54 
   55 struct moxa_isa_softc {
   56         struct device sc_dev;
   57         void *sc_ih;
   58 
   59         bus_space_tag_t sc_iot;
   60         int sc_iobase;
   61 
   62         int sc_alive;                   /* mask of slave units attached */
   63         void *sc_slaves[NSLAVES];       /* com device unit numbers */
   64         bus_space_handle_t sc_slaveioh[NSLAVES];
   65 };
   66 
   67 int moxa_isaprobe __P((struct device *, struct cfdata *, void *));
   68 void moxa_isaattach __P((struct device *, struct device *, void *));
   69 int moxa_isaintr __P((void *));
   70 int moxa_isaprint __P((void *, const char *));
   71 
   72 CFATTACH_DECL(moxa_isa, sizeof(struct moxa_isa_softc),
   73     moxa_isaprobe, moxa_isaattach, NULL, NULL);
   74 
   75 int
   76 moxa_isaprobe(parent, self, aux)
   77         struct device *parent;
   78         struct cfdata *self;
   79         void *aux;
   80 {
   81         struct isa_attach_args *ia = aux;
   82         bus_space_tag_t iot = ia->ia_iot;
   83         bus_space_handle_t ioh;
   84         int i, iobase, rv = 1;
   85 
   86         /*
   87          * Do the normal com probe for the first UART and assume
   88          * its presence, and the ability to map the other UARTS,
   89          * means there is a multiport board there.
   90          * XXX Needs more robustness.
   91          */
   92 
   93         if (ia->ia_nio < 1)
   94                 return (0);
   95         if (ia->ia_nirq < 1)
   96                 return (0);
   97 
   98         if (ISA_DIRECT_CONFIG(ia))
   99                 return (0);
  100 
  101         /* Disallow wildcarded i/o address. */
  102         if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT)
  103                 return (0);
  104         if (ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT)
  105                 return (0);
  106 
  107         /* if the first port is in use as console, then it. */
  108         if (com_is_console(iot, ia->ia_io[0].ir_addr, 0))
  109                 goto checkmappings;
  110 
  111         if (bus_space_map(iot, ia->ia_io[0].ir_addr, COM_NPORTS, 0, &ioh)) {
  112                 rv = 0;
  113                 goto out;
  114         }
  115         rv = comprobe1(iot, ioh);
  116         bus_space_unmap(iot, ioh, COM_NPORTS);
  117         if (rv == 0)
  118                 goto out;
  119 
  120 checkmappings:
  121         for (i = 1, iobase = ia->ia_io[0].ir_addr; i < NSLAVES; i++) {
  122                 iobase += COM_NPORTS;
  123 
  124                 if (com_is_console(iot, iobase, 0))
  125                         continue;
  126 
  127                 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
  128                         rv = 0;
  129                         goto out;
  130                 }
  131                 bus_space_unmap(iot, ioh, COM_NPORTS);
  132         }
  133 
  134 out:
  135         if (rv) {
  136                 ia->ia_nio = 1;
  137                 ia->ia_io[0].ir_size = NSLAVES * COM_NPORTS;
  138 
  139                 ia->ia_nirq = 1;
  140 
  141                 ia->ia_niomem = 0;
  142                 ia->ia_ndrq = 0;
  143         }
  144         return (rv);
  145 }
  146 
  147 int
  148 moxa_isaprint(aux, pnp)
  149         void *aux;
  150         const char *pnp;
  151 {
  152         struct commulti_attach_args *ca = aux;
  153 
  154         if (pnp)
  155                 aprint_normal("com at %s", pnp);
  156         aprint_normal(" slave %d", ca->ca_slave);
  157         return (UNCONF);
  158 }
  159 
  160 void
  161 moxa_isaattach(parent, self, aux)
  162         struct device *parent, *self;
  163         void *aux;
  164 {
  165         struct moxa_isa_softc *sc = (void *)self;
  166         struct isa_attach_args *ia = aux;
  167         struct commulti_attach_args ca;
  168         bus_space_tag_t iot = ia->ia_iot;
  169         int i, iobase;
  170 
  171         printf("\n");
  172 
  173         sc->sc_iot = ia->ia_iot;
  174         sc->sc_iobase = ia->ia_io[0].ir_addr;
  175 
  176         for (i = 0; i < NSLAVES; i++) {
  177                 iobase = sc->sc_iobase + i * COM_NPORTS;
  178                 if (!com_is_console(iot, iobase, &sc->sc_slaveioh[i]) &&
  179                     bus_space_map(iot, iobase, COM_NPORTS, 0,
  180                         &sc->sc_slaveioh[i])) {
  181                         printf("%s: can't map i/o space for slave %d\n",
  182                             sc->sc_dev.dv_xname, i);
  183                         return;
  184                 }
  185         }
  186 
  187         for (i = 0; i < NSLAVES; i++) {
  188                 ca.ca_slave = i;
  189                 ca.ca_iot = sc->sc_iot;
  190                 ca.ca_ioh = sc->sc_slaveioh[i];
  191                 ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
  192                 ca.ca_noien = 1;
  193 
  194                 sc->sc_slaves[i] = config_found(self, &ca, moxa_isaprint);
  195                 if (sc->sc_slaves[i] != NULL)
  196                         sc->sc_alive |= 1 << i;
  197         }
  198 
  199         sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
  200             IST_EDGE, IPL_SERIAL, moxa_isaintr, sc);
  201 }
  202 
  203 int
  204 moxa_isaintr(arg)
  205         void *arg;
  206 {
  207         struct moxa_isa_softc *sc = arg;
  208         int bits;
  209         int rv = 0;
  210 
  211         bits = sc->sc_alive;
  212         if (bits == 0)
  213                 return (0);
  214 
  215         for (;;rv = 0) {
  216 #define TRY(n) \
  217                 if (bits & (1 << (n))) \
  218                         rv += comintr(sc->sc_slaves[n]);
  219                 TRY(0);
  220                 TRY(1);
  221                 TRY(2);
  222                 TRY(3);
  223                 TRY(4);
  224                 TRY(5);
  225                 TRY(6);
  226                 TRY(7);
  227 #undef TRY
  228                 if (rv == 0)
  229                         return (1);
  230         }
  231 }

Cache object: 7c611b24be04666f960bc771c9fd43f2


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