1 /*
2 * Copyright (c) 1998 German Tischler. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *---------------------------------------------------------------------------
32 *
33 * Card format:
34 *
35 * iobase + 0 : reset on (0x03)
36 * iobase + 1 : reset off (0x0)
37 * iobase + 2 : isac read/write
38 * iobase + 3 : hscx read/write ( offset 0-0x3f hscx0 ,
39 * offset 0x40-0x7f hscx1 )
40 * iobase + 4 : offset for indirect addressing
41 *
42 *---------------------------------------------------------------------------
43 *
44 * isic - I4B Siemens ISDN Chipset Driver for SWS cards
45 * ====================================================
46 *
47 * EXPERIMENTAL !!!!
48 * =================
49 *
50 * $Id: isic_isapnp_sws.c,v 1.5 2003/11/10 08:51:52 wiz Exp $
51 *
52 * last edit-date: [Fri Jan 5 11:38:29 2001]
53 *
54 * -hm adding driver to i4b
55 * -hm adjustments for FreeBSD < 2.2.6, no PnP support yet
56 *
57 *---------------------------------------------------------------------------*/
58
59 #include <sys/cdefs.h>
60 __KERNEL_RCSID(0, "$NetBSD: isic_isapnp_sws.c,v 1.5 2003/11/10 08:51:52 wiz Exp $");
61
62 #include "opt_isicpnp.h"
63 #ifdef ISICPNP_SEDLBAUER
64
65 #define SWS_RESON 0 /* reset on */
66 #define SWS_RESOFF 1 /* reset off */
67 #define SWS_ISAC 2 /* ISAC */
68 #define SWS_HSCX0 3 /* HSCX0 */
69 #define SWS_RW 4 /* indirect access register */
70 #define SWS_HSCX1 5 /* this is for fakeing that we mean hscx1, though */
71 /* access is done through hscx0 */
72
73 #define SWS_REGS 8 /* we use an area of 8 bytes for io */
74
75 #define SWS_BASE(X) ((unsigned int)X&~(SWS_REGS-1))
76 #define SWS_PART(X) ((unsigned int)X& (SWS_REGS-1))
77 #define SWS_ADDR(X) ((SWS_PART(X) == SWS_ISAC) ? (SWS_BASE(X)+SWS_ISAC) : (SWS_BASE(X)+SWS_HSCX0) )
78 #define SWS_REG(X,Y) ((SWS_PART(X) != SWS_HSCX1) ? Y : (Y+0x40) )
79 #define SWS_IDO(X) (SWS_BASE(X)+SWS_RW)
80
81 #include <sys/param.h>
82 #if defined(__FreeBSD__) && __FreeBSD__ >= 3
83 #include <sys/ioccom.h>
84 #else
85 #include <sys/ioctl.h>
86 #endif
87 #include <sys/kernel.h>
88 #include <sys/systm.h>
89 #include <sys/mbuf.h>
90
91 #if defined(__NetBSD__) && __NetBSD_Version__ >= 104230000
92 #include <sys/callout.h>
93 #endif
94
95 #ifdef __FreeBSD__
96 #include <machine/clock.h>
97 #include <i386/isa/isa_device.h>
98 #else
99 #include <machine/bus.h>
100 #include <sys/device.h>
101 #endif
102
103 #include <sys/socket.h>
104 #include <net/if.h>
105
106 #ifdef __FreeBSD__
107 #include <machine/i4b_debug.h>
108 #include <machine/i4b_ioctl.h>
109 #else
110 #include <netisdn/i4b_debug.h>
111 #include <netisdn/i4b_ioctl.h>
112 #include <netisdn/i4b_global.h>
113 #include <netisdn/i4b_l2.h>
114 #include <netisdn/i4b_l1l2.h>
115 #endif
116
117 #include <dev/ic/isic_l1.h>
118 #include <dev/ic/isac.h>
119 #include <dev/ic/hscx.h>
120
121 #include <netisdn/i4b_global.h>
122 #include <netisdn/i4b_l1l2.h>
123 #include <netisdn/i4b_mbuf.h>
124
125 #ifndef __FreeBSD__
126 static u_int8_t sws_read_reg __P((struct isic_softc *sc, int what, bus_size_t offs));
127 static void sws_write_reg __P((struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data));
128 static void sws_read_fifo __P((struct isic_softc *sc, int what, void *buf, size_t size));
129 static void sws_write_fifo __P((struct isic_softc *sc, int what, const void *data, size_t size));
130 void isic_attach_sws __P((struct isic_softc *sc));
131 #endif
132
133 /*---------------------------------------------------------------------------*
134 * SWS P&P ISAC get fifo routine
135 *---------------------------------------------------------------------------*/
136
137 #ifdef __FreeBSD__
138
139 static void
140 sws_read_fifo(void *buf, const void *base, size_t len)
141 {
142 outb(SWS_IDO(base),SWS_REG(base,0));
143 insb(SWS_ADDR(base),buf,len);
144 }
145
146 #else
147
148 static void
149 sws_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
150 {
151 bus_space_tag_t t = sc->sc_maps[0].t;
152 bus_space_handle_t h = sc->sc_maps[0].h;
153 switch (what) {
154 case ISIC_WHAT_ISAC:
155 bus_space_write_1(t, h, SWS_RW, 0);
156 bus_space_read_multi_1(t, h, SWS_ISAC, buf, size);
157 break;
158 case ISIC_WHAT_HSCXA:
159 bus_space_write_1(t, h, SWS_RW, 0);
160 bus_space_read_multi_1(t, h, SWS_HSCX0, buf, size);
161 break;
162 case ISIC_WHAT_HSCXB:
163 bus_space_write_1(t, h, SWS_RW, 0x40);
164 bus_space_read_multi_1(t, h, SWS_HSCX0, buf, size);
165 break;
166 }
167 }
168
169 #endif
170
171 /*---------------------------------------------------------------------------*
172 * SWS P&P ISAC put fifo routine
173 *---------------------------------------------------------------------------*/
174
175 #ifdef __FreeBSD__
176
177 static void
178 sws_write_fifo(void *base, const void *buf, size_t len)
179 {
180 outb (SWS_IDO(base),SWS_REG(base,0));
181 outsb(SWS_ADDR(base),buf,len);
182 }
183
184 #else
185
186 static void
187 sws_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
188 {
189 bus_space_tag_t t = sc->sc_maps[0].t;
190 bus_space_handle_t h = sc->sc_maps[0].h;
191 switch (what) {
192 case ISIC_WHAT_ISAC:
193 bus_space_write_1(t, h, SWS_RW, 0);
194 bus_space_write_multi_1(t, h, SWS_ISAC, (u_int8_t*)buf, size);
195 break;
196 case ISIC_WHAT_HSCXA:
197 bus_space_write_1(t, h, SWS_RW, 0);
198 bus_space_write_multi_1(t, h, SWS_HSCX0, (u_int8_t*)buf, size);
199 break;
200 case ISIC_WHAT_HSCXB:
201 bus_space_write_1(t, h, SWS_RW, 0x40);
202 bus_space_write_multi_1(t, h, SWS_HSCX0, (u_int8_t*)buf, size);
203 break;
204 }
205 }
206
207 #endif
208
209 /*---------------------------------------------------------------------------*
210 * SWS P&P ISAC put register routine
211 *---------------------------------------------------------------------------*/
212
213 #ifdef __FreeBSD__
214
215 static void
216 sws_write_reg(u_char *base, u_int offset, u_int v)
217 {
218 outb(SWS_IDO(base),SWS_REG(base,offset));
219 outb(SWS_ADDR(base),v);
220 }
221
222 #else
223
224 static void
225 sws_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
226 {
227 bus_space_tag_t t = sc->sc_maps[0].t;
228 bus_space_handle_t h = sc->sc_maps[0].h;
229 switch (what) {
230 case ISIC_WHAT_ISAC:
231 bus_space_write_1(t, h, SWS_RW, offs);
232 bus_space_write_1(t, h, SWS_ISAC, data);
233 break;
234 case ISIC_WHAT_HSCXA:
235 bus_space_write_1(t, h, SWS_RW, offs);
236 bus_space_write_1(t, h, SWS_HSCX0, data);
237 break;
238 case ISIC_WHAT_HSCXB:
239 bus_space_write_1(t, h, SWS_RW, 0x40+offs);
240 bus_space_write_1(t, h, SWS_HSCX0, data);
241 break;
242 }
243 }
244
245 #endif
246
247 /*---------------------------------------------------------------------------*
248 * SWS P&P ISAC get register routine
249 *---------------------------------------------------------------------------*/
250 #ifdef __FreeBSD__
251
252 static u_char
253 sws_read_reg(u_char *base, u_int offset)
254 {
255 outb(SWS_IDO(base),SWS_REG(base,offset));
256 return inb(SWS_ADDR(base));
257 }
258
259 #else
260
261 static u_int8_t
262 sws_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
263 {
264 bus_space_tag_t t = sc->sc_maps[0].t;
265 bus_space_handle_t h = sc->sc_maps[0].h;
266 switch (what) {
267 case ISIC_WHAT_ISAC:
268 bus_space_write_1(t, h, SWS_RW, offs);
269 return bus_space_read_1(t, h, SWS_ISAC);
270 case ISIC_WHAT_HSCXA:
271 bus_space_write_1(t, h, SWS_RW, offs);
272 return bus_space_read_1(t, h, SWS_HSCX0);
273 case ISIC_WHAT_HSCXB:
274 bus_space_write_1(t, h, SWS_RW, 0x40+offs);
275 return bus_space_read_1(t, h, SWS_HSCX0);
276 }
277 return 0;
278 }
279
280 #endif
281
282 #ifdef __FreeBSD__
283
284 /* attach callback routine */
285
286 int
287 isic_attach_sws(struct isa_device *dev)
288 {
289 struct isic_softc *sc = &l1_sc[dev->id_unit];
290
291 /* fill in isic_softc structure */
292
293 sc->readreg = sws_read_reg;
294 sc->writereg = sws_write_reg;
295 sc->readfifo = sws_read_fifo;
296 sc->writefifo = sws_write_fifo;
297 sc->clearirq = NULL;
298 sc->sc_unit = dev->id_unit;
299 sc->sc_irq = dev->id_irq;
300 sc->sc_port = dev->id_iobase;
301 sc->sc_cardtyp = CARD_TYPEP_SWS;
302 sc->sc_bustyp = BUS_TYPE_IOM2;
303 sc->sc_ipac = 0;
304 sc->sc_bfifolen = HSCX_FIFO_LEN;
305 dev->id_msize = 0;
306
307 ISAC_BASE = (caddr_t) (((u_int) sc->sc_port) + SWS_ISAC);
308 HSCX_A_BASE = (caddr_t) (((u_int) sc->sc_port) + SWS_HSCX0);
309 HSCX_B_BASE = (caddr_t) (((u_int) sc->sc_port) + SWS_HSCX1);
310
311 /*
312 * Read HSCX A/B VSTR. Expected value for the SWS PnP card is
313 * 0x05 ( = version 2.1 ) in the least significant bits.
314 */
315
316 if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
317 ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
318 {
319 printf("isic%d: HSCX VSTR test failed for SWS PnP\n",
320 dev->id_unit);
321 printf("isic%d: HSC0: VSTR: %#x\n",
322 dev->id_unit, HSCX_READ(0, H_VSTR));
323 printf("isic%d: HSC1: VSTR: %#x\n",
324 dev->id_unit, HSCX_READ(1, H_VSTR));
325 return (0);
326 }
327
328 /* reset card */
329
330 outb( ((u_int) sc->sc_port) + SWS_RESON , 0x3);
331 DELAY(SEC_DELAY / 5);
332 outb( ((u_int) sc->sc_port) + SWS_RESOFF, 0);
333 DELAY(SEC_DELAY / 5);
334
335 return(1);
336 }
337
338 #else /* !__FreeBSD__ */
339
340 void
341 isic_attach_sws(struct isic_softc *sc)
342 {
343 /* setup access routines */
344
345 sc->readreg = sws_read_reg;
346 sc->writereg = sws_write_reg;
347
348 sc->readfifo = sws_read_fifo;
349 sc->writefifo = sws_write_fifo;
350
351 /* setup card type */
352
353 sc->sc_cardtyp = CARD_TYPEP_SWS;
354
355 /* setup IOM bus type */
356
357 sc->sc_bustyp = BUS_TYPE_IOM2;
358
359 sc->sc_ipac = 0;
360 sc->sc_bfifolen = HSCX_FIFO_LEN;
361
362 /*
363 * Read HSCX A/B VSTR. Expected value for the SWS PnP card is
364 * 0x05 ( = version 2.1 ) in the least significant bits.
365 */
366
367 if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
368 ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
369 {
370 printf("%s: HSCX VSTR test failed for SWS PnP\n",
371 sc->sc_dev.dv_xname);
372 printf("%s: HSC0: VSTR: %#x\n",
373 sc->sc_dev.dv_xname, HSCX_READ(0, H_VSTR));
374 printf("%s: HSC1: VSTR: %#x\n",
375 sc->sc_dev.dv_xname, HSCX_READ(1, H_VSTR));
376 return;
377 }
378
379 /* reset card */
380 {
381 bus_space_tag_t t = sc->sc_maps[0].t;
382 bus_space_handle_t h = sc->sc_maps[0].h;
383 bus_space_write_1(t, h, SWS_RESON, 0x3);
384 DELAY(SEC_DELAY / 5);
385 bus_space_write_1(t, h, SWS_RESOFF, 0);
386 DELAY(SEC_DELAY / 5);
387 }
388 }
389
390 #endif /* !__FreeBSD__ */
391
392 #endif /* ISICPNP_SEDLBAUER */
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