The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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sys/dev/isci/scil/sci_base_controller.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
    3  *
    4  * This file is provided under a dual BSD/GPLv2 license.  When using or
    5  * redistributing this file, you may do so under either license.
    6  *
    7  * GPL LICENSE SUMMARY
    8  *
    9  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   10  *
   11  * This program is free software; you can redistribute it and/or modify
   12  * it under the terms of version 2 of the GNU General Public License as
   13  * published by the Free Software Foundation.
   14  *
   15  * This program is distributed in the hope that it will be useful, but
   16  * WITHOUT ANY WARRANTY; without even the implied warranty of
   17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   18  * General Public License for more details.
   19  *
   20  * You should have received a copy of the GNU General Public License
   21  * along with this program; if not, write to the Free Software
   22  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   23  * The full GNU General Public License is included in this distribution
   24  * in the file called LICENSE.GPL.
   25  *
   26  * BSD LICENSE
   27  *
   28  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   29  * All rights reserved.
   30  *
   31  * Redistribution and use in source and binary forms, with or without
   32  * modification, are permitted provided that the following conditions
   33  * are met:
   34  *
   35  *   * Redistributions of source code must retain the above copyright
   36  *     notice, this list of conditions and the following disclaimer.
   37  *   * Redistributions in binary form must reproduce the above copyright
   38  *     notice, this list of conditions and the following disclaimer in
   39  *     the documentation and/or other materials provided with the
   40  *     distribution.
   41  *
   42  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   43  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   44  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
   45  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   46  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   47  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   48  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   49  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   50  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   51  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   52  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   53  *
   54  * $FreeBSD$
   55  */
   56 #ifndef _SCI_BASE_CONTROLLER_H_
   57 #define _SCI_BASE_CONTROLLER_H_
   58 
   59 /**
   60  * @file
   61  *
   62  * @brief This file contains all of the structures, constants, and methods
   63  *        common to all controller object definitions.
   64  */
   65 
   66 #ifdef __cplusplus
   67 extern "C" {
   68 #endif // __cplusplus
   69 
   70 #include <dev/isci/scil/intel_sas.h>
   71 #include <dev/isci/scil/sci_controller_constants.h>
   72 
   73 #include <dev/isci/scil/sci_base_object.h>
   74 #include <dev/isci/scil/sci_base_state.h>
   75 #include <dev/isci/scil/sci_base_logger.h>
   76 #include <dev/isci/scil/sci_base_memory_descriptor_list.h>
   77 #include <dev/isci/scil/sci_base_state_machine.h>
   78 #include <dev/isci/scil/sci_base_state_machine_logger.h>
   79 
   80 /**
   81  * @enum SCI_BASE_CONTROLLER_STATES
   82  *
   83  * @brief This enumeration depicts all the states for the common controller
   84  *        state machine.
   85  */
   86 typedef enum _SCI_BASE_CONTROLLER_STATES
   87 {
   88    /**
   89     * Simply the initial state for the base controller state machine.
   90     */
   91    SCI_BASE_CONTROLLER_STATE_INITIAL = 0,
   92 
   93    /**
   94     * This state indicates that the controller is reset.  The memory for
   95     * the controller is in its initial state, but the controller requires
   96     * initialization.
   97     * This state is entered from the INITIAL state.
   98     * This state is entered from the RESETTING state.
   99     */
  100    SCI_BASE_CONTROLLER_STATE_RESET,
  101 
  102    /**
  103     * This state is typically an action state that indicates the controller
  104     * is in the process of initialization.  In this state no new IO operations
  105     * are permitted.
  106     * This state is entered from the RESET state.
  107     */
  108    SCI_BASE_CONTROLLER_STATE_INITIALIZING,
  109 
  110    /**
  111     * This state indicates that the controller has been successfully
  112     * initialized.  In this state no new IO operations are permitted.
  113     * This state is entered from the INITIALIZING state.
  114     */
  115    SCI_BASE_CONTROLLER_STATE_INITIALIZED,
  116 
  117    /**
  118     * This state indicates the controller is in the process of becoming
  119     * ready (i.e. starting).  In this state no new IO operations are permitted.
  120     * This state is entered from the INITIALIZED state.
  121     */
  122    SCI_BASE_CONTROLLER_STATE_STARTING,
  123 
  124    /**
  125     * This state indicates the controller is now ready.  Thus, the user
  126     * is able to perform IO operations on the controller.
  127     * This state is entered from the STARTING state.
  128     */
  129    SCI_BASE_CONTROLLER_STATE_READY,
  130 
  131    /**
  132     * This state is typically an action state that indicates the controller
  133     * is in the process of resetting.  Thus, the user is unable to perform
  134     * IO operations on the controller.  A reset is considered destructive in
  135     * most cases.
  136     * This state is entered from the READY state.
  137     * This state is entered from the FAILED state.
  138     * This state is entered from the STOPPED state.
  139     */
  140    SCI_BASE_CONTROLLER_STATE_RESETTING,
  141 
  142    /**
  143     * This state indicates that the controller is in the process of stopping.
  144     * In this state no new IO operations are permitted, but existing IO
  145     * operations are allowed to complete.
  146     * This state is entered from the READY state.
  147     */
  148    SCI_BASE_CONTROLLER_STATE_STOPPING,
  149 
  150    /**
  151     * This state indicates that the controller has successfully been stopped.
  152     * In this state no new IO operations are permitted.
  153     * This state is entered from the STOPPING state.
  154     */
  155    SCI_BASE_CONTROLLER_STATE_STOPPED,
  156 
  157    /**
  158     * This state indicates that the controller could not successfully be
  159     * initialized.  In this state no new IO operations are permitted.
  160     * This state is entered from the INITIALIZING state.
  161     * This state is entered from the STARTING state.
  162     * This state is entered from the STOPPING state.
  163     * This state is entered from the RESETTING state.
  164     */
  165    SCI_BASE_CONTROLLER_STATE_FAILED,
  166 
  167    SCI_BASE_CONTROLLER_MAX_STATES
  168 
  169 } SCI_BASE_CONTROLLER_STATES;
  170 
  171 /**
  172  * @struct SCI_BASE_CONTROLLER
  173  *
  174  * @brief The base controller object abstracts the fields common to all
  175  *        SCI controller objects.
  176  */
  177 typedef struct SCI_BASE_CONTROLLER
  178 {
  179    /**
  180     * The field specifies that the parent object for the base controller
  181     * is the base object itself.
  182     */
  183    SCI_BASE_OBJECT_T parent;
  184 
  185    /**
  186     * This field points to the memory descriptor list associated with this
  187     * controller.  The MDL indicates the memory requirements necessary for
  188     * this controller object.
  189     */
  190    SCI_BASE_MEMORY_DESCRIPTOR_LIST_T  mdl;
  191 
  192    /**
  193     * This field records the fact that the controller has encountered a fatal memory
  194     * error and controller must stay in failed state.
  195     */
  196    U8 error;
  197 
  198    /**
  199     * This field contains the information for the base controller state
  200     * machine.
  201     */
  202    SCI_BASE_STATE_MACHINE_T state_machine;
  203 
  204    #ifdef SCI_LOGGING
  205    SCI_BASE_STATE_MACHINE_LOGGER_T state_machine_logger;
  206    #endif // SCI_LOGGING
  207 
  208 } SCI_BASE_CONTROLLER_T;
  209 
  210 // Forward declarations
  211 struct SCI_BASE_REMOTE_DEVICE;
  212 struct SCI_BASE_REQUEST;
  213 
  214 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_HANDLER_T)(
  215    SCI_BASE_CONTROLLER_T *
  216 );
  217 
  218 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_TIMED_HANDLER_T)(
  219    SCI_BASE_CONTROLLER_T *,
  220    U32
  221 );
  222 
  223 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_REQUEST_HANDLER_T)(
  224    SCI_BASE_CONTROLLER_T *,
  225    struct SCI_BASE_REMOTE_DEVICE *,
  226    struct SCI_BASE_REQUEST *
  227 );
  228 
  229 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T)(
  230    SCI_BASE_CONTROLLER_T *,
  231    struct SCI_BASE_REMOTE_DEVICE *,
  232    struct SCI_BASE_REQUEST *,
  233    U16
  234 );
  235 
  236 
  237 /**
  238  * @struct SCI_BASE_CONTROLLER_STATE_HANDLER
  239  *
  240  * @brief This structure contains all of the state handler methods common to
  241  *        base controller state machines.  Handler methods provide the ability
  242  *        to change the behavior for user requests or transitions depending
  243  *        on the state the machine is in.
  244  */
  245 typedef struct SCI_BASE_CONTROLLER_STATE_HANDLER
  246 {
  247    /**
  248     * The start_handler specifies the method invoked when a user attempts to
  249     * start a controller.
  250     */
  251    SCI_BASE_CONTROLLER_TIMED_HANDLER_T start_handler;
  252 
  253    /**
  254     * The stop_handler specifies the method invoked when a user attempts to
  255     * stop a controller.
  256     */
  257    SCI_BASE_CONTROLLER_TIMED_HANDLER_T stop_handler;
  258 
  259    /**
  260     * The reset_handler specifies the method invoked when a user attempts to
  261     * reset a controller.
  262     */
  263    SCI_BASE_CONTROLLER_HANDLER_T reset_handler;
  264 
  265    /**
  266     * The initialize_handler specifies the method invoked when a user
  267     * attempts to initialize a controller.
  268     */
  269    SCI_BASE_CONTROLLER_HANDLER_T initialize_handler;
  270 
  271    /**
  272     * The start_io_handler specifies the method invoked when a user
  273     * attempts to start an IO request for a controller.
  274     */
  275    SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_io_handler;
  276 
  277    /**
  278     * The start_internal_request_handler specifies the method invoked when a user
  279     * attempts to start an internal request for a controller.
  280     */
  281    SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_high_priority_io_handler;
  282 
  283    /**
  284     * The complete_io_handler specifies the method invoked when a user
  285     * attempts to complete an IO request for a controller.
  286     */
  287    SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_io_handler;
  288 
  289     /**
  290     * The complete_high_priority_io_handler specifies the method invoked when a user
  291     * attempts to complete a high priority IO request for a controller.
  292     */
  293    SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_high_priority_io_handler;
  294 
  295    /**
  296     * The continue_io_handler specifies the method invoked when a user
  297     * attempts to continue an IO request for a controller.
  298     */
  299    SCI_BASE_CONTROLLER_REQUEST_HANDLER_T continue_io_handler;
  300 
  301    /**
  302     * The start_task_handler specifies the method invoked when a user
  303     * attempts to start a task management request for a controller.
  304     */
  305    SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_task_handler;
  306 
  307    /**
  308     * The complete_task_handler specifies the method invoked when a user
  309     * attempts to complete a task management request for a controller.
  310     */
  311    SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_task_handler;
  312 
  313 } SCI_BASE_CONTROLLER_STATE_HANDLER_T;
  314 
  315 /**
  316  * @brief Construct the base controller
  317  *
  318  * @param[in] this_controller This parameter specifies the base controller
  319  *            to be constructed.
  320  * @param[in] logger This parameter specifies the logger associated with
  321  *            this base controller object.
  322  * @param[in] state_table This parameter specifies the table of state
  323  *            definitions to be utilized for the controller state machine.
  324  * @param[in] mde_array This parameter specifies the array of memory
  325  *            descriptor entries to be managed by this list.
  326  * @param[in] mde_array_length This parameter specifies the size of the
  327  *            array of entries.
  328  * @param[in] next_mdl This parameter specifies a subsequent MDL object
  329  *            to be managed by this MDL object.
  330  * @param[in] oem_parameters This parameter specifies the original
  331  *            equipment manufacturer parameters to be utilized by this
  332  *            controller object.
  333  *
  334  * @return none
  335  */
  336 void sci_base_controller_construct(
  337    SCI_BASE_CONTROLLER_T             * this_controller,
  338    SCI_BASE_LOGGER_T                 * logger,
  339    SCI_BASE_STATE_T                  * state_table,
  340    SCI_PHYSICAL_MEMORY_DESCRIPTOR_T  * mdes,
  341    U32                                 mde_count,
  342    SCI_MEMORY_DESCRIPTOR_LIST_HANDLE_T next_mdl
  343 );
  344 
  345 #ifdef __cplusplus
  346 }
  347 #endif // __cplusplus
  348 
  349 #endif // _SCI_BASE_CONTROLLER_H_

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