FreeBSD/Linux Kernel Cross Reference
sys/dev/isp/ispreg.h
1 /* $FreeBSD: src/sys/dev/isp/ispreg.h,v 1.9.2.4 2000/03/04 06:04:53 mjacob Exp $ */
2 /*
3 * Machine Independent (well, as best as possible) register
4 * definitions for Qlogic ISP SCSI adapters.
5 *
6 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob
7 * NASA/Ames Research Center
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice immediately at the beginning of the file, without modification,
15 * this list of conditions, and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34 #ifndef _ISPREG_H
35 #define _ISPREG_H
36
37 /*
38 * Hardware definitions for the Qlogic ISP registers.
39 */
40
41 /*
42 * This defines types of access to various registers.
43 *
44 * R: Read Only
45 * W: Write Only
46 * RW: Read/Write
47 *
48 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
49 * if RISC processor in ISP is paused.
50 */
51
52 /*
53 * Offsets for various register blocks.
54 *
55 * Sad but true, different architectures have different offsets.
56 *
57 * Don't be alarmed if none of this makes sense. The original register
58 * layout set some defines in a certain pattern. Everything else has been
59 * grafted on since. For example, the ISP1080 manual will state that DMA
60 * registers start at 0x80 from the base of the register address space.
61 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
62 * to start at offset 0x60 because the DMA registers are all defined to
63 * be DMA_BLOCK+0x20 and so on. Clear?
64 */
65
66 #define BIU_REGS_OFF 0x00
67
68 #define PCI_MBOX_REGS_OFF 0x70
69 #define PCI_MBOX_REGS2100_OFF 0x10
70 #define SBUS_MBOX_REGS_OFF 0x80
71
72 #define PCI_SXP_REGS_OFF 0x80
73 #define SBUS_SXP_REGS_OFF 0x200
74
75 #define PCI_RISC_REGS_OFF 0x80
76 #define SBUS_RISC_REGS_OFF 0x400
77
78 /* Bless me! Chip designers have putzed it again! */
79 #define ISP1080_DMA_REGS_OFF 0x60
80 #define DMA_REGS_OFF 0x00 /* same as BIU block */
81
82 /*
83 * NB: The *_BLOCK definitions have no specific hardware meaning.
84 * They serve simply to note to the MD layer which block of
85 * registers offsets are being accessed.
86 */
87 #define _NREG_BLKS 5
88 #define _BLK_REG_SHFT 13
89 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT)
90 #define BIU_BLOCK (0 << _BLK_REG_SHFT)
91 #define MBOX_BLOCK (1 << _BLK_REG_SHFT)
92 #define SXP_BLOCK (2 << _BLK_REG_SHFT)
93 #define RISC_BLOCK (3 << _BLK_REG_SHFT)
94 #define DMA_BLOCK (4 << _BLK_REG_SHFT)
95
96 /*
97 * Bus Interface Block Register Offsets
98 */
99
100 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
101 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
102 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
103 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
104 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
105 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
106 #define BIU2100_CSR (BIU_BLOCK+0x6)
107 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
108 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
109 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
110 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
111 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
112 #define RDMA2100_CONTROL DFIFO_COMMAND
113 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
114
115 /*
116 * Putzed DMA register layouts.
117 */
118 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
119 #define CDMA2100_CONTROL CDMA_CONF
120 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
121 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
122 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
123 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
124 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
125 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
126 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
127 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
128
129 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
130 #define TDMA2100_CONTROL DDMA_CONF
131 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
132 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
133 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
134 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
135 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
136 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
137 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
138 /* these are for the 1040A cards */
139 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
140 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
141
142
143 /*
144 * Bus Interface Block Register Definitions
145 */
146 /* BUS CONFIGURATION REGISTER #0 */
147 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */
148 /* BUS CONFIGURATION REGISTER #1 */
149
150 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */
151 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */
152
153 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */
154 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */
155 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */
156 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */
157 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */
158 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */
159 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */
160 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */
161 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */
162 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
163 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
164
165 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
166 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
167 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
168
169 /* ISP2100 Bus Control/Status Register */
170
171 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */
172 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */
173 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */
174 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */
175 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */
176 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */
177 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */
178 #define BIU2100_SOFT_RESET 0x01
179 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */
180
181
182 /* BUS CONTROL REGISTER */
183 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */
184 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */
185 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */
186 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */
187 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */
188 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */
189
190 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000
191 #define BIU2100_ICR_ENA_FPM_INT 0x0020
192 #define BIU2100_ICR_ENA_FB_INT 0x0010
193 #define BIU2100_ICR_ENA_RISC_INT 0x0008
194 #define BIU2100_ICR_ENA_CDMA_INT 0x0004
195 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002
196 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
197 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
198
199 #define ENABLE_INTS(isp) (IS_SCSI(isp))? \
200 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \
201 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS)
202
203 #define INTS_ENABLED(isp) ((IS_SCSI(isp))? \
204 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\
205 (ISP_READ(isp, BIU_ICR) & \
206 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)))
207
208 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0)
209
210 /* BUS STATUS REGISTER */
211 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */
212 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */
213 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */
214 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */
215 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */
216
217 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
218 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
219 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
220 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
221 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
222 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
223 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
224
225 #define INT_PENDING(isp, isr) (IS_FC(isp)? \
226 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0))
227
228 /* BUS SEMAPHORE REGISTER */
229 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
230 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
231
232 /* NVRAM SEMAPHORE REGISTER */
233 #define BIU_NVRAM_CLOCK 0x0001
234 #define BIU_NVRAM_SELECT 0x0002
235 #define BIU_NVRAM_DATAOUT 0x0004
236 #define BIU_NVRAM_DATAIN 0x0008
237 #define ISP_NVRAM_READ 6
238
239 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */
240 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
241 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */
242 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */
243 #define DMA_DMA_DIRECTION 0x0001 /*
244 * Set DMA direction:
245 * 0 - DMA FIFO to host
246 * 1 - Host to DMA FIFO
247 */
248
249 /* COMMAND && DATA DMA CONTROL REGISTER */
250 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */
251 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /*
252 * Clear FIFO and DMA Channel,
253 * reset DMA registers
254 */
255 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */
256 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */
257 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */
258
259 /*
260 * Variants of same for 2100
261 */
262 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004
263 #define DMA_CNTRL2100_RESET_INT 0x0002
264
265
266
267 /* DMA STATUS REGISTER */
268 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */
269 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */
270 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */
271 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */
272 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */
273 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */
274
275 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */
276 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */
277 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */
278 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */
279 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */
280 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */
281 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */
282 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */
283 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */
284 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */
285 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */
286
287 /* DMA Status Register, pipeline status bits */
288 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */
289 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */
290 #define DMA_SBUS_PIPE_STAGE1 0x0040 /*
291 * Pipeline stage 1 Loaded,
292 * stage 2 empty
293 */
294 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */
295 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */
296 #define DMA_PCI_PIPE_STAGE1 0x0001 /*
297 * Pipeline stage 1 Loaded,
298 * stage 2 empty
299 */
300 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */
301
302 /* DMA Status Register, channel status bits */
303 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */
304 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */
305 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */
306 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */
307 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */
308 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */
309 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */
310
311
312 /* DMA FIFO STATUS REGISTER */
313 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */
314 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */
315 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */
316 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */
317
318 /*
319 * Mailbox Block Register Offsets
320 */
321
322 #define INMAILBOX0 (MBOX_BLOCK+0x0)
323 #define INMAILBOX1 (MBOX_BLOCK+0x2)
324 #define INMAILBOX2 (MBOX_BLOCK+0x4)
325 #define INMAILBOX3 (MBOX_BLOCK+0x6)
326 #define INMAILBOX4 (MBOX_BLOCK+0x8)
327 #define INMAILBOX5 (MBOX_BLOCK+0xA)
328 #define INMAILBOX6 (MBOX_BLOCK+0xC)
329 #define INMAILBOX7 (MBOX_BLOCK+0xE)
330
331 #define OUTMAILBOX0 (MBOX_BLOCK+0x0)
332 #define OUTMAILBOX1 (MBOX_BLOCK+0x2)
333 #define OUTMAILBOX2 (MBOX_BLOCK+0x4)
334 #define OUTMAILBOX3 (MBOX_BLOCK+0x6)
335 #define OUTMAILBOX4 (MBOX_BLOCK+0x8)
336 #define OUTMAILBOX5 (MBOX_BLOCK+0xA)
337 #define OUTMAILBOX6 (MBOX_BLOCK+0xC)
338 #define OUTMAILBOX7 (MBOX_BLOCK+0xE)
339
340 #define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2))
341 #define NMBOX(isp) \
342 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
343 ((isp)->isp_type & ISP_HA_FC))? 8 : 6)
344
345 /*
346 * SXP Block Register Offsets
347 */
348 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
349 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
350 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
351 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
352 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
353 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
354 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
355 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
356 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
357 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
358 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
359 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
360 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
361 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
362 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
363 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
364 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
365 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
366 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
367 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
368 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
369 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
370 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
371 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
372 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
373 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
374 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
375 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
376 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
377 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
378 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
379 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
380 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
381 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
382 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
383 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
384 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
385 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
386 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
387
388 /* for 1080/1280/1240 only */
389 #define SXP_BANK1_SELECT 0x100
390
391
392 /* SXP CONF1 REGISTER */
393 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */
394 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */
395 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */
396 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */
397 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */
398
399 /* SXP CONF2 REGISTER */
400 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */
401 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */
402 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */
403 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */
404 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */
405 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */
406
407 /* SXP INTERRUPT REGISTER */
408 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */
409 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */
410 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */
411 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */
412 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */
413 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */
414 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */
415 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */
416 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */
417 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */
418
419
420 /* SXP GROSS ERROR REGISTER */
421 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */
422 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */
423 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */
424 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */
425 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */
426 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */
427 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */
428
429 /* SXP EXCEPTION REGISTER */
430 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */
431 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */
432 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */
433 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */
434 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */
435 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */
436 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */
437 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */
438 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */
439 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */
440
441 /* SXP OVERRIDE REGISTER */
442 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */
443 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */
444 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */
445 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */
446 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */
447 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */
448 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */
449 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */
450 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */
451 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */
452 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */
453 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */
454 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */
455
456 /* SXP COMMANDS */
457 #define SXP_RESET_BUS_CMD 0x300b
458
459 /* SXP SCSI ID REGISTER */
460 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */
461 #define SXP_SELECT_ID 0x000F /* Select id */
462
463 /* SXP DEV CONFIG1 REGISTER */
464 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */
465 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */
466 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */
467
468
469 /* SXP DEV CONFIG2 REGISTER */
470 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */
471 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */
472 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */
473 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */
474 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */
475
476
477 /* SXP PHASE POINTER REGISTER */
478 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */
479 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */
480 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */
481 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */
482
483
484 /* SXP FIFO STATUS REGISTER */
485 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */
486 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */
487 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */
488 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */
489
490
491 /* SXP CONTROL PINS REGISTER */
492 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */
493 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */
494 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */
495 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */
496 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */
497 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */
498 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */
499 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */
500 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */
501 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */
502 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */
503 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */
504
505 /*
506 * Set the hold time for the SCSI Bus Reset to be 250 ms
507 */
508 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250
509
510 /* SXP DIFF PINS REGISTER */
511 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */
512 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */
513 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */
514 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */
515 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
516 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
517
518 /* Ultra2 only */
519 #define SXP_PINS_LVD_MODE 0x1000
520 #define SXP_PINS_HVD_MODE 0x0800
521 #define SXP_PINS_SE_MODE 0x0400
522
523 /* The above have to be put together with the DIFFM pin to make sense */
524 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE)
525 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE)
526 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE)
527 #define ISP1080_MODE_MASK \
528 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE)
529
530 /*
531 * RISC and Host Command and Control Block Register Offsets
532 */
533
534 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
535 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
536 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
537 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
538 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
539 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
540 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
541 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
542 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
543 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
544 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
545 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
546 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
547 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
548 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
549 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
550 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
551 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
552 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
553 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
554 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
555 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
556 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
557 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
558 #define RISC_MTR2100 RISC_BLOCK+0x30
559
560 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
561 #define DUAL_BANK 8
562 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
563 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
564 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
565 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
566 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
567 #define TCR RISC_BLOCK+0x46 /* W : Test Control */
568 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */
569
570
571 /* PROCESSOR STATUS REGISTER */
572 #define RISC_PSR_FORCE_TRUE 0x8000
573 #define RISC_PSR_LOOP_COUNT_DONE 0x4000
574 #define RISC_PSR_RISC_INT 0x2000
575 #define RISC_PSR_TIMER_ROLLOVER 0x1000
576 #define RISC_PSR_ALU_OVERFLOW 0x0800
577 #define RISC_PSR_ALU_MSB 0x0400
578 #define RISC_PSR_ALU_CARRY 0x0200
579 #define RISC_PSR_ALU_ZERO 0x0100
580
581 #define RISC_PSR_PCI_ULTRA 0x0080
582 #define RISC_PSR_SBUS_ULTRA 0x0020
583
584 #define RISC_PSR_DMA_INT 0x0010
585 #define RISC_PSR_SXP_INT 0x0008
586 #define RISC_PSR_HOST_INT 0x0004
587 #define RISC_PSR_INT_PENDING 0x0002
588 #define RISC_PSR_FORCE_FALSE 0x0001
589
590
591 /* Host Command and Control */
592 #define HCCR_CMD_NOP 0x0000 /* NOP */
593 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */
594 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
595 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
596 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
597 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
598 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
599 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
600 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */
601 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */
602 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */
603 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */
604 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */
605
606 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400
607 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200
608 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100
609 #define ISP2100_HCCR_PARITY 0x0001
610
611 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */
612 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */
613 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */
614
615 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */
616 #define HCCR_RESET 0x0040 /* R : reset in progress */
617 #define HCCR_PAUSE 0x0020 /* R : RISC paused */
618
619 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
620
621 /*
622 * NVRAM Definitions (PCI cards only)
623 */
624
625 #define ISPBSMX(c, byte, shift, mask) \
626 (((c)[(byte)] >> (shift)) & (mask))
627 /*
628 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
629 *
630 * Some portion of the front of this is for general host adapter properties
631 * This is followed by an array of per-target parameters, and is tailed off
632 * with a checksum xor byte at offset 127. For non-byte entities data is
633 * stored in Little Endian order.
634 */
635
636 #define ISP_NVRAM_SIZE 128
637
638 #define ISP_NVRAM_VERSION(c) (c)[4]
639 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
640 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
641 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
642 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
643 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
644 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
645 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
646 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
647 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
648 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
649 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
650 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
651 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
652 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
653 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
654 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
655 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
656 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
657 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
658 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
659 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
660 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
661 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
662 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
663 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
664 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
665 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
666 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
667 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
668
669 #define ISP_NVRAM_TARGOFF 28
670 #define ISP_NVARM_TARGSIZE 6
671 #define _IxT(tgt, tidx) \
672 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx))
673 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
674 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
675 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
676 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
677 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
678 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
679 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
680 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
681 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
682 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
683 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
684 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
685 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
686
687 /*
688 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
689 *
690 * Some portion of the front of this is for general host adapter properties
691 * This is followed by an array of per-target parameters, and is tailed off
692 * with a checksum xor byte at offset 256. For non-byte entities data is
693 * stored in Little Endian order.
694 */
695
696 #define ISP1080_NVRAM_SIZE 256
697
698 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
699
700 /* Offset 5 */
701 /*
702 uint8_t bios_configuration_mode :2;
703 uint8_t bios_disable :1;
704 uint8_t selectable_scsi_boot_enable :1;
705 uint8_t cd_rom_boot_enable :1;
706 uint8_t disable_loading_risc_code :1;
707 uint8_t enable_64bit_addressing :1;
708 uint8_t unused_7 :1;
709 */
710
711 /* Offsets 6, 7 */
712 /*
713 uint8_t boot_lun_number :5;
714 uint8_t scsi_bus_number :1;
715 uint8_t unused_6 :1;
716 uint8_t unused_7 :1;
717 uint8_t boot_target_number :4;
718 uint8_t unused_12 :1;
719 uint8_t unused_13 :1;
720 uint8_t unused_14 :1;
721 uint8_t unused_15 :1;
722 */
723
724 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
725
726 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
727 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
728
729 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
730 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
731 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
732
733 #define ISP1080_ISP_PARAMETER(c) \
734 (((c)[18]) | ((c)[19] << 8))
735
736 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
737 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
738
739 #define ISP1080_BUS1_OFF 112
740
741 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \
742 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
743 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
744 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
745 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
746 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
747 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
748 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
749
750 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
751 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
752 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
753 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
754 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
755 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
756 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
757 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
758 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
759 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
760 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
761 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
762
763 #define ISP1080_NVRAM_TARGOFF(b) \
764 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
765 #define ISP1080_NVRAM_TARGSIZE 6
766 #define _IxT8(tgt, tidx, b) \
767 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
768
769 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
770 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
771 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
772 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
773 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
774 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
775 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \
776 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
777 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
778 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
779 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
780 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
781 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
782 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
783 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \
784 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
785 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
786 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
787 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
788 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
789 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
790 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
791 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
792 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
793 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
794 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
795
796 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
797 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
798 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
799 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
800 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
801 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
802 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
803 #define ISP12160_FAST_POST ISP1080_FAST_POST
804 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
805
806 #define ISP12160_NVRAM_INITIATOR_ID \
807 ISP1080_NVRAM_INITIATOR_ID
808 #define ISP12160_NVRAM_BUS_RESET_DELAY \
809 ISP1080_NVRAM_BUS_RESET_DELAY
810 #define ISP12160_NVRAM_BUS_RETRY_COUNT \
811 ISP1080_NVRAM_BUS_RETRY_COUNT
812 #define ISP12160_NVRAM_BUS_RETRY_DELAY \
813 ISP1080_NVRAM_BUS_RETRY_DELAY
814 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
815 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
816 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
817 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
818 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
819 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
820 #define ISP12160_NVRAM_SELECTION_TIMEOUT \
821 ISP1080_NVRAM_SELECTION_TIMEOUT
822 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
823 ISP1080_NVRAM_MAX_QUEUE_DEPTH
824
825
826 #define ISP12160_BUS0_OFF 24
827 #define ISP12160_BUS1_OFF 136
828
829 #define ISP12160_NVRAM_TARGOFF(b) \
830 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
831
832 #define ISP12160_NVRAM_TARGSIZE 6
833 #define _IxT16(tgt, tidx, b) \
834 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
835
836 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
837 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
838 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
839 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
840 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
841 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
842 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \
843 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
844 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
845 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
846 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
847 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
848 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
849 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
850 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \
851 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
852
853 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
854 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
855 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
856 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
857
858 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
859 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
860 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
861 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
862
863 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
864 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
865 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
866 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
867 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
868 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
869
870 /*
871 * Qlogic 2XXX NVRAM is an array of 256 bytes.
872 *
873 * Some portion of the front of this is for general RISC engine parameters,
874 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
875 *
876 * This is followed by some general host adapter parameters, and ends with
877 * a checksum xor byte at offset 255. For non-byte entities data is stored
878 * in Little Endian order.
879 */
880 #define ISP2100_NVRAM_SIZE 256
881 /* ISP_NVRAM_VERSION is in same overall place */
882 #define ISP2100_NVRAM_RISCVER(c) (c)[6]
883 #define ISP2100_NVRAM_OPTIONS(c) (c)[8]
884 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
885 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
886 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
887 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
888 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
889
890 #define ISP2100_NVRAM_NODE_NAME(c) (\
891 (((u_int64_t)(c)[18]) << 56) | \
892 (((u_int64_t)(c)[19]) << 48) | \
893 (((u_int64_t)(c)[20]) << 40) | \
894 (((u_int64_t)(c)[21]) << 32) | \
895 (((u_int64_t)(c)[22]) << 24) | \
896 (((u_int64_t)(c)[23]) << 16) | \
897 (((u_int64_t)(c)[24]) << 8) | \
898 (((u_int64_t)(c)[25]) << 0))
899 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26]
900
901 #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70]
902 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
903 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
904 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
905 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
906 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
907 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
908
909 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\
910 (((u_int64_t)(c)[72]) << 56) | \
911 (((u_int64_t)(c)[73]) << 48) | \
912 (((u_int64_t)(c)[74]) << 40) | \
913 (((u_int64_t)(c)[75]) << 32) | \
914 (((u_int64_t)(c)[76]) << 24) | \
915 (((u_int64_t)(c)[77]) << 16) | \
916 (((u_int64_t)(c)[78]) << 8) | \
917 (((u_int64_t)(c)[79]) << 0))
918
919 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
920
921 #endif /* _ISPREG_H */
Cache object: 30efcf2521abf9758547eee15cbd2052
|