Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/iwn/if_iwnreg.h
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1 /* $FreeBSD: releng/8.1/sys/dev/iwn/if_iwnreg.h 207443 2010-04-30 18:13:11Z bschmidt $ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.37 2010/02/17 18:23:00 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define IWN_TX_RING_COUNT 256 22 #define IWN_TX_RING_LOMARK 192 23 #define IWN_TX_RING_HIMARK 224 24 #define IWN_RX_RING_COUNT_LOG 6 25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27 #define IWN4965_NTXQUEUES 16 28 #define IWN5000_NTXQUEUES 20 29 30 #define IWN4965_NDMACHNLS 7 31 #define IWN5000_NDMACHNLS 8 32 33 #define IWN_SRVC_DMACHNL 9 34 35 #define IWN_ICT_SIZE 4096 36 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37 38 /* Maximum number of DMA segments for TX. */ 39 #define IWN_MAX_SCATTER 20 40 41 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42 #define IWN_RBUF_SIZE (4 * 1024) 43 44 #if defined(__LP64__) 45 /* HW supports 36-bit DMA addresses. */ 46 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48 #else 49 #define IWN_LOADDR(paddr) (paddr) 50 #define IWN_HIADDR(paddr) (0) 51 #endif 52 53 /* Base Address Register. */ 54 #define IWN_PCI_BAR0 PCI_MAPREG_START 55 56 /* 57 * Control and status registers. 58 */ 59 #define IWN_HW_IF_CONFIG 0x000 60 #define IWN_INT_COALESCING 0x004 61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62 #define IWN_INT 0x008 63 #define IWN_INT_MASK 0x00c 64 #define IWN_FH_INT 0x010 65 #define IWN_RESET 0x020 66 #define IWN_GP_CNTRL 0x024 67 #define IWN_HW_REV 0x028 68 #define IWN_EEPROM 0x02c 69 #define IWN_EEPROM_GP 0x030 70 #define IWN_OTP_GP 0x034 71 #define IWN_GIO 0x03c 72 #define IWN_GP_DRIVER 0x050 73 #define IWN_UCODE_GP1_CLR 0x05c 74 #define IWN_LED 0x094 75 #define IWN_DRAM_INT_TBL 0x0a0 76 #define IWN_GIO_CHICKEN 0x100 77 #define IWN_ANA_PLL 0x20c 78 #define IWN_HW_REV_WA 0x22c 79 #define IWN_DBG_HPET_MEM 0x240 80 #define IWN_DBG_LINK_PWR_MGMT 0x250 81 #define IWN_MEM_RADDR 0x40c 82 #define IWN_MEM_WADDR 0x410 83 #define IWN_MEM_WDATA 0x418 84 #define IWN_MEM_RDATA 0x41c 85 #define IWN_PRPH_WADDR 0x444 86 #define IWN_PRPH_RADDR 0x448 87 #define IWN_PRPH_WDATA 0x44c 88 #define IWN_PRPH_RDATA 0x450 89 #define IWN_HBUS_TARG_WRPTR 0x460 90 91 /* 92 * Flow-Handler registers. 93 */ 94 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 95 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 96 #define IWN_FH_KW_ADDR 0x197c 97 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 98 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 99 #define IWN_FH_STATUS_WPTR 0x1bc0 100 #define IWN_FH_RX_BASE 0x1bc4 101 #define IWN_FH_RX_WPTR 0x1bc8 102 #define IWN_FH_RX_CONFIG 0x1c00 103 #define IWN_FH_RX_STATUS 0x1c44 104 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 105 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 106 #define IWN_FH_TX_CHICKEN 0x1e98 107 #define IWN_FH_TX_STATUS 0x1eb0 108 109 /* 110 * TX scheduler registers. 111 */ 112 #define IWN_SCHED_BASE 0xa02c00 113 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 114 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 115 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 116 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 117 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 118 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 119 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 120 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 121 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 122 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 123 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 124 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 125 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 126 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 127 128 /* 129 * Offsets in TX scheduler's SRAM. 130 */ 131 #define IWN4965_SCHED_CTX_OFF 0x380 132 #define IWN4965_SCHED_CTX_LEN 416 133 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 134 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 135 #define IWN5000_SCHED_CTX_OFF 0x600 136 #define IWN5000_SCHED_CTX_LEN 520 137 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 138 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 139 140 /* 141 * NIC internal memory offsets. 142 */ 143 #define IWN_APMG_CLK_CTRL 0x3000 144 #define IWN_APMG_CLK_EN 0x3004 145 #define IWN_APMG_CLK_DIS 0x3008 146 #define IWN_APMG_PS 0x300c 147 #define IWN_APMG_DIGITAL_SVR 0x3058 148 #define IWN_APMG_ANALOG_SVR 0x306c 149 #define IWN_APMG_PCI_STT 0x3010 150 #define IWN_BSM_WR_CTRL 0x3400 151 #define IWN_BSM_WR_MEM_SRC 0x3404 152 #define IWN_BSM_WR_MEM_DST 0x3408 153 #define IWN_BSM_WR_DWCOUNT 0x340c 154 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 155 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 156 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 157 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 158 #define IWN_BSM_SRAM_BASE 0x3800 159 160 /* Possible flags for register IWN_HW_IF_CONFIG. */ 161 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 162 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 163 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 164 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 165 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 166 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 167 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 168 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 169 170 /* Possible values for register IWN_INT_PERIODIC. */ 171 #define IWN_INT_PERIODIC_DIS 0x00 172 #define IWN_INT_PERIODIC_ENA 0xff 173 174 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 175 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 176 177 /* Possible values for IWN_BSM_WR_MEM_DST. */ 178 #define IWN_FW_TEXT_BASE 0x00000000 179 #define IWN_FW_DATA_BASE 0x00800000 180 181 /* Possible flags for register IWN_RESET. */ 182 #define IWN_RESET_NEVO (1 << 0) 183 #define IWN_RESET_SW (1 << 7) 184 #define IWN_RESET_MASTER_DISABLED (1 << 8) 185 #define IWN_RESET_STOP_MASTER (1 << 9) 186 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 187 188 /* Possible flags for register IWN_GP_CNTRL. */ 189 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 190 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 191 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 192 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 193 #define IWN_GP_CNTRL_SLEEP (1 << 4) 194 #define IWN_GP_CNTRL_RFKILL (1 << 27) 195 196 /* Possible flags for register IWN_HW_REV. */ 197 #define IWN_HW_REV_TYPE_SHIFT 4 198 #define IWN_HW_REV_TYPE_MASK 0x000000f0 199 #define IWN_HW_REV_TYPE_4965 0 200 #define IWN_HW_REV_TYPE_5300 2 201 #define IWN_HW_REV_TYPE_5350 3 202 #define IWN_HW_REV_TYPE_5150 4 203 #define IWN_HW_REV_TYPE_5100 5 204 #define IWN_HW_REV_TYPE_1000 6 205 #define IWN_HW_REV_TYPE_6000 7 206 #define IWN_HW_REV_TYPE_6050 8 207 208 /* Possible flags for register IWN_GIO_CHICKEN. */ 209 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 210 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 211 212 /* Possible flags for register IWN_GIO. */ 213 #define IWN_GIO_L0S_ENA (1 << 1) 214 215 /* Possible flags for register IWN_GP_DRIVER. */ 216 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 217 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 218 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 219 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 220 221 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 222 #define IWN_UCODE_GP1_RFKILL (1 << 1) 223 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 224 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 225 226 /* Possible flags/values for register IWN_LED. */ 227 #define IWN_LED_BSM_CTRL (1 << 5) 228 #define IWN_LED_OFF 0x00000038 229 #define IWN_LED_ON 0x00000078 230 231 /* Possible flags for register IWN_DRAM_INT_TBL. */ 232 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 233 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 234 235 /* Possible values for register IWN_ANA_PLL. */ 236 #define IWN_ANA_PLL_INIT 0x00880300 237 238 /* Possible flags for register IWN_FH_RX_STATUS. */ 239 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 240 241 /* Possible flags for register IWN_BSM_WR_CTRL. */ 242 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 243 #define IWN_BSM_WR_CTRL_START (1 << 31) 244 245 /* Possible flags for register IWN_INT. */ 246 #define IWN_INT_ALIVE (1 << 0) 247 #define IWN_INT_WAKEUP (1 << 1) 248 #define IWN_INT_SW_RX (1 << 3) 249 #define IWN_INT_CT_REACHED (1 << 6) 250 #define IWN_INT_RF_TOGGLED (1 << 7) 251 #define IWN_INT_SW_ERR (1 << 25) 252 #define IWN_INT_SCHED (1 << 26) 253 #define IWN_INT_FH_TX (1 << 27) 254 #define IWN_INT_RX_PERIODIC (1 << 28) 255 #define IWN_INT_HW_ERR (1 << 29) 256 #define IWN_INT_FH_RX (1 << 31) 257 258 /* Shortcut. */ 259 #define IWN_INT_MASK_DEF \ 260 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 261 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 262 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 263 264 /* Possible flags for register IWN_FH_INT. */ 265 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 266 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 267 #define IWN_FH_INT_HI_PRIOR (1 << 30) 268 /* Shortcuts for the above. */ 269 #define IWN_FH_INT_TX \ 270 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 271 #define IWN_FH_INT_RX \ 272 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 273 274 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 275 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 276 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 277 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 278 279 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 280 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 281 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 282 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 283 284 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 285 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 286 287 /* Possible flags for register IWN_FH_TX_STATUS. */ 288 #define IWN_FH_TX_STATUS_IDLE(chnl) \ 289 (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 290 291 /* Possible flags for register IWN_FH_RX_CONFIG. */ 292 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 293 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 294 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 295 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 296 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 297 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 298 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 299 300 /* Possible flags for register IWN_FH_TX_CONFIG. */ 301 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 302 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 303 304 /* Possible flags for register IWN_EEPROM. */ 305 #define IWN_EEPROM_READ_VALID (1 << 0) 306 #define IWN_EEPROM_CMD (1 << 1) 307 308 /* Possible flags for register IWN_EEPROM_GP. */ 309 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 310 311 /* Possible flags for register IWN_OTP_GP. */ 312 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 313 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 314 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 315 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 316 317 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 318 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 319 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 320 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 321 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 322 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 323 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 324 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 325 326 /* Possible flags for registers IWN_APMG_CLK_*. */ 327 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 328 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 329 330 /* Possible flags for register IWN_APMG_PS. */ 331 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 332 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 333 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 334 #define IWN_APMG_PS_PWR_SRC_VAUX 2 335 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 336 #define IWN_APMG_PS_RESET_REQ (1 << 26) 337 338 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 339 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 340 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 341 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 342 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 343 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 344 345 /* Possible flags for IWN_APMG_PCI_STT. */ 346 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 347 348 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 349 #define IWN_FW_UPDATED (1 << 31) 350 351 #define IWN_SCHED_WINSZ 64 352 #define IWN_SCHED_LIMIT 64 353 #define IWN4965_SCHED_COUNT 512 354 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 355 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 356 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 357 358 struct iwn_tx_desc { 359 uint8_t reserved1[3]; 360 uint8_t nsegs; 361 struct { 362 uint32_t addr; 363 uint16_t len; 364 } __packed segs[IWN_MAX_SCATTER]; 365 /* Pad to 128 bytes. */ 366 uint32_t reserved2; 367 } __packed; 368 369 struct iwn_rx_status { 370 uint16_t closed_count; 371 uint16_t closed_rx_count; 372 uint16_t finished_count; 373 uint16_t finished_rx_count; 374 uint32_t reserved[2]; 375 } __packed; 376 377 struct iwn_rx_desc { 378 uint32_t len; 379 uint8_t type; 380 #define IWN_UC_READY 1 381 #define IWN_ADD_NODE_DONE 24 382 #define IWN_TX_DONE 28 383 #define IWN5000_CALIBRATION_RESULT 102 384 #define IWN5000_CALIBRATION_DONE 103 385 #define IWN_START_SCAN 130 386 #define IWN_STOP_SCAN 132 387 #define IWN_RX_STATISTICS 156 388 #define IWN_BEACON_STATISTICS 157 389 #define IWN_STATE_CHANGED 161 390 #define IWN_BEACON_MISSED 162 391 #define IWN_RX_PHY 192 392 #define IWN_MPDU_RX_DONE 193 393 #define IWN_RX_DONE 195 394 #define IWN_RX_COMPRESSED_BA 197 395 396 uint8_t flags; 397 uint8_t idx; 398 uint8_t qid; 399 } __packed; 400 401 /* Possible RX status flags. */ 402 #define IWN_RX_NO_CRC_ERR (1 << 0) 403 #define IWN_RX_NO_OVFL_ERR (1 << 1) 404 /* Shortcut for the above. */ 405 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 406 #define IWN_RX_MPDU_MIC_OK (1 << 6) 407 #define IWN_RX_CIPHER_MASK (7 << 8) 408 #define IWN_RX_CIPHER_CCMP (2 << 8) 409 #define IWN_RX_MPDU_DEC (1 << 11) 410 #define IWN_RX_DECRYPT_MASK (3 << 11) 411 #define IWN_RX_DECRYPT_OK (3 << 11) 412 413 struct iwn_tx_cmd { 414 uint8_t code; 415 #define IWN_CMD_RXON 16 416 #define IWN_CMD_RXON_ASSOC 17 417 #define IWN_CMD_EDCA_PARAMS 19 418 #define IWN_CMD_TIMING 20 419 #define IWN_CMD_ADD_NODE 24 420 #define IWN_CMD_TX_DATA 28 421 #define IWN_CMD_LINK_QUALITY 78 422 #define IWN_CMD_SET_LED 72 423 #define IWN5000_CMD_WIMAX_COEX 90 424 #define IWN5000_CMD_CALIB_CONFIG 101 425 #define IWN5000_CMD_CALIB_RESULT 102 426 #define IWN5000_CMD_CALIB_COMPLETE 103 427 #define IWN_CMD_SET_POWER_MODE 119 428 #define IWN_CMD_SCAN 128 429 #define IWN_CMD_SCAN_RESULTS 131 430 #define IWN_CMD_TXPOWER_DBM 149 431 #define IWN_CMD_TXPOWER 151 432 #define IWN5000_CMD_TX_ANT_CONFIG 152 433 #define IWN_CMD_BT_COEX 155 434 #define IWN_CMD_GET_STATISTICS 156 435 #define IWN_CMD_SET_CRITICAL_TEMP 164 436 #define IWN_CMD_SET_SENSITIVITY 168 437 #define IWN_CMD_PHY_CALIB 176 438 439 uint8_t flags; 440 uint8_t idx; 441 uint8_t qid; 442 uint8_t data[136]; 443 } __packed; 444 445 /* Antenna flags, used in various commands. */ 446 #define IWN_ANT_A (1 << 0) 447 #define IWN_ANT_B (1 << 1) 448 #define IWN_ANT_C (1 << 2) 449 /* Shortcuts. */ 450 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 451 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 452 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 453 454 /* Structure for command IWN_CMD_RXON. */ 455 struct iwn_rxon { 456 uint8_t myaddr[IEEE80211_ADDR_LEN]; 457 uint16_t reserved1; 458 uint8_t bssid[IEEE80211_ADDR_LEN]; 459 uint16_t reserved2; 460 uint8_t wlap[IEEE80211_ADDR_LEN]; 461 uint16_t reserved3; 462 uint8_t mode; 463 #define IWN_MODE_HOSTAP 1 464 #define IWN_MODE_STA 3 465 #define IWN_MODE_IBSS 4 466 #define IWN_MODE_MONITOR 6 467 468 uint8_t air; 469 uint16_t rxchain; 470 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 471 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 472 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 473 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 474 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 475 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 476 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 477 478 uint8_t ofdm_mask; 479 uint8_t cck_mask; 480 uint16_t associd; 481 uint32_t flags; 482 #define IWN_RXON_24GHZ (1 << 0) 483 #define IWN_RXON_CCK (1 << 1) 484 #define IWN_RXON_AUTO (1 << 2) 485 #define IWN_RXON_SHSLOT (1 << 4) 486 #define IWN_RXON_SHPREAMBLE (1 << 5) 487 #define IWN_RXON_NODIVERSITY (1 << 7) 488 #define IWN_RXON_ANTENNA_A (1 << 8) 489 #define IWN_RXON_ANTENNA_B (1 << 9) 490 #define IWN_RXON_TSF (1 << 15) 491 #define IWN_RXON_CTS_TO_SELF (1 << 30) 492 493 uint32_t filter; 494 #define IWN_FILTER_PROMISC (1 << 0) 495 #define IWN_FILTER_CTL (1 << 1) 496 #define IWN_FILTER_MULTICAST (1 << 2) 497 #define IWN_FILTER_NODECRYPT (1 << 3) 498 #define IWN_FILTER_BSS (1 << 5) 499 #define IWN_FILTER_BEACON (1 << 6) 500 501 uint8_t chan; 502 uint8_t reserved4; 503 uint8_t ht_single_mask; 504 uint8_t ht_dual_mask; 505 /* The following fields are for >=5000 Series only. */ 506 uint8_t ht_triple_mask; 507 uint8_t reserved5; 508 uint16_t acquisition; 509 uint16_t reserved6; 510 } __packed; 511 512 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 513 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 514 515 /* Structure for command IWN_CMD_ASSOCIATE. */ 516 struct iwn_assoc { 517 uint32_t flags; 518 uint32_t filter; 519 uint8_t ofdm_mask; 520 uint8_t cck_mask; 521 uint16_t reserved; 522 } __packed; 523 524 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 525 struct iwn_edca_params { 526 uint32_t flags; 527 #define IWN_EDCA_UPDATE (1 << 0) 528 #define IWN_EDCA_TXOP (1 << 4) 529 530 struct { 531 uint16_t cwmin; 532 uint16_t cwmax; 533 uint8_t aifsn; 534 uint8_t reserved; 535 uint16_t txoplimit; 536 } __packed ac[WME_NUM_AC]; 537 } __packed; 538 539 /* Structure for command IWN_CMD_TIMING. */ 540 struct iwn_cmd_timing { 541 uint64_t tstamp; 542 uint16_t bintval; 543 uint16_t atim; 544 uint32_t binitval; 545 uint16_t lintval; 546 uint16_t reserved; 547 } __packed; 548 549 /* Structure for command IWN_CMD_ADD_NODE. */ 550 struct iwn_node_info { 551 uint8_t control; 552 #define IWN_NODE_UPDATE (1 << 0) 553 554 uint8_t reserved1[3]; 555 556 uint8_t macaddr[IEEE80211_ADDR_LEN]; 557 uint16_t reserved2; 558 uint8_t id; 559 #define IWN_ID_BSS 0 560 #define IWN5000_ID_BROADCAST 15 561 #define IWN4965_ID_BROADCAST 31 562 563 uint8_t flags; 564 #define IWN_FLAG_SET_KEY (1 << 0) 565 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 566 #define IWN_FLAG_SET_TXRATE (1 << 2) 567 #define IWN_FLAG_SET_ADDBA (1 << 3) 568 #define IWN_FLAG_SET_DELBA (1 << 4) 569 570 uint16_t reserved3; 571 uint16_t kflags; 572 #define IWN_KFLAG_CCMP (1 << 1) 573 #define IWN_KFLAG_MAP (1 << 3) 574 #define IWN_KFLAG_KID(kid) ((kid) << 8) 575 #define IWN_KFLAG_INVALID (1 << 11) 576 #define IWN_KFLAG_GROUP (1 << 14) 577 578 uint8_t tsc2; /* TKIP TSC2 */ 579 uint8_t reserved4; 580 uint16_t ttak[5]; 581 uint8_t kid; 582 uint8_t reserved5; 583 uint8_t key[16]; 584 /* The following 3 fields are for 5000 Series only. */ 585 uint64_t tsc; 586 uint8_t rxmic[8]; 587 uint8_t txmic[8]; 588 589 uint32_t htflags; 590 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 591 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 592 593 uint32_t mask; 594 uint16_t disable_tid; 595 uint16_t reserved6; 596 uint8_t addba_tid; 597 uint8_t delba_tid; 598 uint16_t addba_ssn; 599 uint32_t reserved7; 600 } __packed; 601 602 struct iwn4965_node_info { 603 uint8_t control; 604 uint8_t reserved1[3]; 605 uint8_t macaddr[IEEE80211_ADDR_LEN]; 606 uint16_t reserved2; 607 uint8_t id; 608 uint8_t flags; 609 uint16_t reserved3; 610 uint16_t kflags; 611 uint8_t tsc2; /* TKIP TSC2 */ 612 uint8_t reserved4; 613 uint16_t ttak[5]; 614 uint8_t kid; 615 uint8_t reserved5; 616 uint8_t key[16]; 617 uint32_t htflags; 618 uint32_t mask; 619 uint16_t disable_tid; 620 uint16_t reserved6; 621 uint8_t addba_tid; 622 uint8_t delba_tid; 623 uint16_t addba_ssn; 624 uint32_t reserved7; 625 } __packed; 626 627 #define IWN_RFLAG_CCK (1 << 1) 628 #define IWN_RFLAG_ANT(x) ((x) << 6) 629 630 /* Structure for command IWN_CMD_TX_DATA. */ 631 struct iwn_cmd_data { 632 uint16_t len; 633 uint16_t lnext; 634 uint32_t flags; 635 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 636 #define IWN_TX_NEED_RTS (1 << 1) 637 #define IWN_TX_NEED_CTS (1 << 2) 638 #define IWN_TX_NEED_ACK (1 << 3) 639 #define IWN_TX_LINKQ (1 << 4) 640 #define IWN_TX_IMM_BA (1 << 6) 641 #define IWN_TX_FULL_TXOP (1 << 7) 642 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 643 #define IWN_TX_AUTO_SEQ (1 << 13) 644 #define IWN_TX_MORE_FRAG (1 << 14) 645 #define IWN_TX_INSERT_TSTAMP (1 << 16) 646 #define IWN_TX_NEED_PADDING (1 << 20) 647 648 uint32_t scratch; 649 uint8_t plcp; 650 uint8_t rflags; 651 uint16_t xrflags; 652 653 uint8_t id; 654 uint8_t security; 655 #define IWN_CIPHER_WEP40 1 656 #define IWN_CIPHER_CCMP 2 657 #define IWN_CIPHER_TKIP 3 658 #define IWN_CIPHER_WEP104 9 659 660 uint8_t linkq; 661 uint8_t reserved2; 662 uint8_t key[16]; 663 uint16_t fnext; 664 uint16_t reserved3; 665 uint32_t lifetime; 666 #define IWN_LIFETIME_INFINITE 0xffffffff 667 668 uint32_t loaddr; 669 uint8_t hiaddr; 670 uint8_t rts_ntries; 671 uint8_t data_ntries; 672 uint8_t tid; 673 uint16_t timeout; 674 uint16_t txop; 675 } __packed; 676 677 /* Structure for command IWN_CMD_LINK_QUALITY. */ 678 #define IWN_MAX_TX_RETRIES 16 679 struct iwn_cmd_link_quality { 680 uint8_t id; 681 uint8_t reserved1; 682 uint16_t ctl; 683 uint8_t flags; 684 uint8_t mimo; 685 uint8_t antmsk_1stream; 686 uint8_t antmsk_2stream; 687 uint8_t ridx[WME_NUM_AC]; 688 uint16_t ampdu_limit; 689 uint8_t ampdu_threshold; 690 uint8_t ampdu_max; 691 uint32_t reserved2; 692 struct { 693 uint8_t plcp; 694 uint8_t rflags; 695 uint16_t xrflags; 696 } __packed retry[IWN_MAX_TX_RETRIES]; 697 uint32_t reserved3; 698 } __packed; 699 700 /* Structure for command IWN_CMD_SET_LED. */ 701 struct iwn_cmd_led { 702 uint32_t unit; /* multiplier (in usecs) */ 703 uint8_t which; 704 #define IWN_LED_ACTIVITY 1 705 #define IWN_LED_LINK 2 706 707 uint8_t off; 708 uint8_t on; 709 uint8_t reserved; 710 } __packed; 711 712 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 713 struct iwn5000_wimax_coex { 714 uint32_t flags; 715 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 716 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 717 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 718 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 719 720 struct iwn5000_wimax_event { 721 uint8_t request; 722 uint8_t window; 723 uint8_t reserved; 724 uint8_t flags; 725 } __packed events[16]; 726 } __packed; 727 728 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 729 struct iwn5000_calib_elem { 730 uint32_t enable; 731 uint32_t start; 732 uint32_t send; 733 uint32_t apply; 734 uint32_t reserved; 735 } __packed; 736 737 struct iwn5000_calib_status { 738 struct iwn5000_calib_elem once; 739 struct iwn5000_calib_elem perd; 740 uint32_t flags; 741 } __packed; 742 743 struct iwn5000_calib_config { 744 struct iwn5000_calib_status ucode; 745 struct iwn5000_calib_status driver; 746 uint32_t reserved; 747 } __packed; 748 749 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 750 struct iwn_pmgt_cmd { 751 uint16_t flags; 752 #define IWN_PS_ALLOW_SLEEP (1 << 0) 753 #define IWN_PS_NOTIFY (1 << 1) 754 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 755 #define IWN_PS_PCI_PMGT (1 << 3) 756 #define IWN_PS_FAST_PD (1 << 4) 757 758 uint8_t keepalive; 759 uint8_t debug; 760 uint32_t rxtimeout; 761 uint32_t txtimeout; 762 uint32_t intval[5]; 763 uint32_t beacons; 764 } __packed; 765 766 /* Structures for command IWN_CMD_SCAN. */ 767 struct iwn_scan_essid { 768 uint8_t id; 769 uint8_t len; 770 uint8_t data[IEEE80211_NWID_LEN]; 771 } __packed; 772 773 struct iwn_scan_hdr { 774 uint16_t len; 775 uint8_t reserved1; 776 uint8_t nchan; 777 uint16_t quiet_time; 778 uint16_t quiet_threshold; 779 uint16_t crc_threshold; 780 uint16_t rxchain; 781 uint32_t max_svc; /* background scans */ 782 uint32_t pause_svc; /* background scans */ 783 uint32_t flags; 784 uint32_t filter; 785 786 /* Followed by a struct iwn_cmd_data. */ 787 /* Followed by an array of 20 structs iwn_scan_essid. */ 788 /* Followed by probe request body. */ 789 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 790 } __packed; 791 792 struct iwn_scan_chan { 793 uint32_t flags; 794 #define IWN_CHAN_ACTIVE (1 << 0) 795 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 796 797 uint16_t chan; 798 uint8_t rf_gain; 799 uint8_t dsp_gain; 800 uint16_t active; /* msecs */ 801 uint16_t passive; /* msecs */ 802 } __packed; 803 804 /* Maximum size of a scan command. */ 805 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 806 807 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 808 #define IWN_RIDX_MAX 32 809 struct iwn4965_cmd_txpower { 810 uint8_t band; 811 uint8_t reserved1; 812 uint8_t chan; 813 uint8_t reserved2; 814 struct { 815 uint8_t rf_gain[2]; 816 uint8_t dsp_gain[2]; 817 } __packed power[IWN_RIDX_MAX + 1]; 818 } __packed; 819 820 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 821 struct iwn5000_cmd_txpower { 822 int8_t global_limit; /* in half-dBm */ 823 #define IWN5000_TXPOWER_AUTO 0x7f 824 #define IWN5000_TXPOWER_MAX_DBM 16 825 826 uint8_t flags; 827 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 828 829 int8_t srv_limit; /* in half-dBm */ 830 uint8_t reserved; 831 } __packed; 832 833 /* Structure for command IWN_CMD_BLUETOOTH. */ 834 struct iwn_bluetooth { 835 uint8_t flags; 836 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 837 #define IWN_BT_COEX_BT_PRIO (1 << 1) 838 #define IWN_BT_COEX_2_WIRE (1 << 2) 839 840 uint8_t lead_time; 841 #define IWN_BT_LEAD_TIME_DEF 30 842 843 uint8_t max_kill; 844 #define IWN_BT_MAX_KILL_DEF 5 845 846 uint8_t reserved; 847 uint32_t kill_ack; 848 uint32_t kill_cts; 849 } __packed; 850 851 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 852 struct iwn_critical_temp { 853 uint32_t reserved; 854 uint32_t tempM; 855 uint32_t tempR; 856 /* degK <-> degC conversion macros. */ 857 #define IWN_CTOK(c) ((c) + 273) 858 #define IWN_KTOC(k) ((k) - 273) 859 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 860 } __packed; 861 862 /* Structure for command IWN_CMD_SET_SENSITIVITY. */ 863 struct iwn_sensitivity_cmd { 864 uint16_t which; 865 #define IWN_SENSITIVITY_DEFAULTTBL 0 866 #define IWN_SENSITIVITY_WORKTBL 1 867 868 uint16_t energy_cck; 869 uint16_t energy_ofdm; 870 uint16_t corr_ofdm_x1; 871 uint16_t corr_ofdm_mrc_x1; 872 uint16_t corr_cck_mrc_x4; 873 uint16_t corr_ofdm_x4; 874 uint16_t corr_ofdm_mrc_x4; 875 uint16_t corr_barker; 876 uint16_t corr_barker_mrc; 877 uint16_t corr_cck_x4; 878 uint16_t energy_ofdm_th; 879 } __packed; 880 881 /* Structures for command IWN_CMD_PHY_CALIB. */ 882 struct iwn_phy_calib { 883 uint8_t code; 884 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 885 #define IWN5000_PHY_CALIB_DC 8 886 #define IWN5000_PHY_CALIB_LO 9 887 #define IWN5000_PHY_CALIB_TX_IQ 11 888 #define IWN5000_PHY_CALIB_CRYSTAL 15 889 #define IWN5000_PHY_CALIB_BASE_BAND 16 890 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 891 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 892 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 893 894 uint8_t group; 895 uint8_t ngroups; 896 uint8_t isvalid; 897 } __packed; 898 899 struct iwn5000_phy_calib_crystal { 900 uint8_t code; 901 uint8_t group; 902 uint8_t ngroups; 903 uint8_t isvalid; 904 905 uint8_t cap_pin[2]; 906 uint8_t reserved[2]; 907 } __packed; 908 909 struct iwn_phy_calib_gain { 910 uint8_t code; 911 uint8_t group; 912 uint8_t ngroups; 913 uint8_t isvalid; 914 915 int8_t gain[3]; 916 uint8_t reserved; 917 } __packed; 918 919 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 920 struct iwn_spectrum_cmd { 921 uint16_t len; 922 uint8_t token; 923 uint8_t id; 924 uint8_t origin; 925 uint8_t periodic; 926 uint16_t timeout; 927 uint32_t start; 928 uint32_t reserved1; 929 uint32_t flags; 930 uint32_t filter; 931 uint16_t nchan; 932 uint16_t reserved2; 933 struct { 934 uint32_t duration; 935 uint8_t chan; 936 uint8_t type; 937 #define IWN_MEASUREMENT_BASIC (1 << 0) 938 #define IWN_MEASUREMENT_CCA (1 << 1) 939 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 940 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 941 #define IWN_MEASUREMENT_FRAME (1 << 4) 942 #define IWN_MEASUREMENT_IDLE (1 << 7) 943 944 uint16_t reserved; 945 } __packed chan[10]; 946 } __packed; 947 948 /* Structure for IWN_UC_READY notification. */ 949 #define IWN_NATTEN_GROUPS 5 950 struct iwn_ucode_info { 951 uint8_t minor; 952 uint8_t major; 953 uint16_t reserved1; 954 uint8_t revision[8]; 955 uint8_t type; 956 uint8_t subtype; 957 #define IWN_UCODE_RUNTIME 0 958 #define IWN_UCODE_INIT 9 959 960 uint16_t reserved2; 961 uint32_t logptr; 962 uint32_t errptr; 963 uint32_t tstamp; 964 uint32_t valid; 965 966 /* The following fields are for UCODE_INIT only. */ 967 int32_t volt; 968 struct { 969 int32_t chan20MHz; 970 int32_t chan40MHz; 971 } __packed temp[4]; 972 int32_t atten[IWN_NATTEN_GROUPS][2]; 973 } __packed; 974 975 /* Structures for IWN_TX_DONE notification. */ 976 #define IWN_TX_SUCCESS 0x00 977 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 978 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 979 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 980 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 981 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 982 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 983 984 struct iwn4965_tx_stat { 985 uint8_t nframes; 986 uint8_t btkillcnt; 987 uint8_t rtsfailcnt; 988 uint8_t ackfailcnt; 989 uint8_t rate; 990 uint8_t rflags; 991 uint16_t xrflags; 992 uint16_t duration; 993 uint16_t reserved; 994 uint32_t power[2]; 995 uint32_t status; 996 } __packed; 997 998 struct iwn5000_tx_stat { 999 uint8_t nframes; 1000 uint8_t btkillcnt; 1001 uint8_t rtsfailcnt; 1002 uint8_t ackfailcnt; 1003 uint8_t rate; 1004 uint8_t rflags; 1005 uint16_t xrflags; 1006 uint16_t duration; 1007 uint16_t reserved; 1008 uint32_t power[2]; 1009 uint32_t info; 1010 uint16_t seq; 1011 uint16_t len; 1012 uint8_t tlc; 1013 uint8_t ratid; 1014 uint8_t fc[2]; 1015 uint16_t status; 1016 uint16_t sequence; 1017 } __packed; 1018 1019 /* Structure for IWN_BEACON_MISSED notification. */ 1020 struct iwn_beacon_missed { 1021 uint32_t consecutive; 1022 uint32_t total; 1023 uint32_t expected; 1024 uint32_t received; 1025 } __packed; 1026 1027 /* Structure for IWN_MPDU_RX_DONE notification. */ 1028 struct iwn_rx_mpdu { 1029 uint16_t len; 1030 uint16_t reserved; 1031 } __packed; 1032 1033 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1034 struct iwn4965_rx_phystat { 1035 uint16_t antenna; 1036 uint16_t agc; 1037 uint8_t rssi[6]; 1038 } __packed; 1039 1040 struct iwn5000_rx_phystat { 1041 uint32_t reserved1; 1042 uint32_t agc; 1043 uint16_t rssi[3]; 1044 } __packed; 1045 1046 struct iwn_rx_stat { 1047 uint8_t phy_len; 1048 uint8_t cfg_phy_len; 1049 #define IWN_STAT_MAXLEN 20 1050 1051 uint8_t id; 1052 uint8_t reserved1; 1053 uint64_t tstamp; 1054 uint32_t beacon; 1055 uint16_t flags; 1056 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1057 1058 uint16_t chan; 1059 uint8_t phybuf[32]; 1060 uint8_t rate; 1061 uint8_t rflags; 1062 uint16_t xrflags; 1063 uint16_t len; 1064 uint16_t reserve3; 1065 } __packed; 1066 1067 #define IWN_RSSI_TO_DBM 44 1068 1069 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1070 struct iwn_compressed_ba { 1071 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1072 uint16_t reserved; 1073 uint8_t id; 1074 uint8_t tid; 1075 uint16_t seq; 1076 uint64_t bitmap; 1077 uint16_t qid; 1078 uint16_t ssn; 1079 } __packed; 1080 1081 /* Structure for IWN_START_SCAN notification. */ 1082 struct iwn_start_scan { 1083 uint64_t tstamp; 1084 uint32_t tbeacon; 1085 uint8_t chan; 1086 uint8_t band; 1087 uint16_t reserved; 1088 uint32_t status; 1089 } __packed; 1090 1091 /* Structure for IWN_STOP_SCAN notification. */ 1092 struct iwn_stop_scan { 1093 uint8_t nchan; 1094 uint8_t status; 1095 uint8_t reserved; 1096 uint8_t chan; 1097 uint64_t tsf; 1098 } __packed; 1099 1100 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1101 struct iwn_spectrum_notif { 1102 uint8_t id; 1103 uint8_t token; 1104 uint8_t idx; 1105 uint8_t state; 1106 #define IWN_MEASUREMENT_START 0 1107 #define IWN_MEASUREMENT_STOP 1 1108 1109 uint32_t start; 1110 uint8_t band; 1111 uint8_t chan; 1112 uint8_t type; 1113 uint8_t reserved1; 1114 uint32_t cca_ofdm; 1115 uint32_t cca_cck; 1116 uint32_t cca_time; 1117 uint8_t basic; 1118 uint8_t reserved2[3]; 1119 uint32_t ofdm[8]; 1120 uint32_t cck[8]; 1121 uint32_t stop; 1122 uint32_t status; 1123 #define IWN_MEASUREMENT_OK 0 1124 #define IWN_MEASUREMENT_CONCURRENT 1 1125 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1126 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1127 #define IWN_MEASUREMENT_STOPPED 6 1128 #define IWN_MEASUREMENT_TIMEOUT 7 1129 #define IWN_MEASUREMENT_FAILED 8 1130 } __packed; 1131 1132 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1133 struct iwn_rx_phy_stats { 1134 uint32_t ina; 1135 uint32_t fina; 1136 uint32_t bad_plcp; 1137 uint32_t bad_crc32; 1138 uint32_t overrun; 1139 uint32_t eoverrun; 1140 uint32_t good_crc32; 1141 uint32_t fa; 1142 uint32_t bad_fina_sync; 1143 uint32_t sfd_timeout; 1144 uint32_t fina_timeout; 1145 uint32_t no_rts_ack; 1146 uint32_t rxe_limit; 1147 uint32_t ack; 1148 uint32_t cts; 1149 uint32_t ba_resp; 1150 uint32_t dsp_kill; 1151 uint32_t bad_mh; 1152 uint32_t rssi_sum; 1153 uint32_t reserved; 1154 } __packed; 1155 1156 struct iwn_rx_general_stats { 1157 uint32_t bad_cts; 1158 uint32_t bad_ack; 1159 uint32_t not_bss; 1160 uint32_t filtered; 1161 uint32_t bad_chan; 1162 uint32_t beacons; 1163 uint32_t missed_beacons; 1164 uint32_t adc_saturated; /* time in 0.8us */ 1165 uint32_t ina_searched; /* time in 0.8us */ 1166 uint32_t noise[3]; 1167 uint32_t flags; 1168 uint32_t load; 1169 uint32_t fa; 1170 uint32_t rssi[3]; 1171 uint32_t energy[3]; 1172 } __packed; 1173 1174 struct iwn_rx_ht_phy_stats { 1175 uint32_t bad_plcp; 1176 uint32_t overrun; 1177 uint32_t eoverrun; 1178 uint32_t good_crc32; 1179 uint32_t bad_crc32; 1180 uint32_t bad_mh; 1181 uint32_t good_ampdu_crc32; 1182 uint32_t ampdu; 1183 uint32_t fragment; 1184 uint32_t reserved; 1185 } __packed; 1186 1187 struct iwn_rx_stats { 1188 struct iwn_rx_phy_stats ofdm; 1189 struct iwn_rx_phy_stats cck; 1190 struct iwn_rx_general_stats general; 1191 struct iwn_rx_ht_phy_stats ht; 1192 } __packed; 1193 1194 struct iwn_tx_stats { 1195 uint32_t preamble; 1196 uint32_t rx_detected; 1197 uint32_t bt_defer; 1198 uint32_t bt_kill; 1199 uint32_t short_len; 1200 uint32_t cts_timeout; 1201 uint32_t ack_timeout; 1202 uint32_t exp_ack; 1203 uint32_t ack; 1204 uint32_t msdu; 1205 uint32_t busrt_err1; 1206 uint32_t burst_err2; 1207 uint32_t cts_collision; 1208 uint32_t ack_collision; 1209 uint32_t ba_timeout; 1210 uint32_t ba_resched; 1211 uint32_t query_ampdu; 1212 uint32_t query; 1213 uint32_t query_ampdu_frag; 1214 uint32_t query_mismatch; 1215 uint32_t not_ready; 1216 uint32_t underrun; 1217 uint32_t bt_ht_kill; 1218 uint32_t rx_ba_resp; 1219 uint32_t reserved[2]; 1220 } __packed; 1221 1222 struct iwn_general_stats { 1223 uint32_t temp; 1224 uint32_t temp_m; 1225 uint32_t burst_check; 1226 uint32_t burst; 1227 uint32_t reserved1[4]; 1228 uint32_t sleep; 1229 uint32_t slot_out; 1230 uint32_t slot_idle; 1231 uint32_t ttl_tstamp; 1232 uint32_t tx_ant_a; 1233 uint32_t tx_ant_b; 1234 uint32_t exec; 1235 uint32_t probe; 1236 uint32_t reserved2[2]; 1237 uint32_t rx_enabled; 1238 uint32_t reserved3[3]; 1239 } __packed; 1240 1241 struct iwn_stats { 1242 uint32_t flags; 1243 struct iwn_rx_stats rx; 1244 struct iwn_tx_stats tx; 1245 struct iwn_general_stats general; 1246 } __packed; 1247 1248 1249 /* Firmware error dump. */ 1250 struct iwn_fw_dump { 1251 uint32_t valid; 1252 uint32_t id; 1253 uint32_t pc; 1254 uint32_t branch_link[2]; 1255 uint32_t interrupt_link[2]; 1256 uint32_t error_data[2]; 1257 uint32_t src_line; 1258 uint32_t tsf; 1259 uint32_t time[2]; 1260 } __packed; 1261 1262 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1263 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1264 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1265 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1266 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1267 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1268 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1269 1270 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1271 1272 /* 1273 * Offsets into EEPROM. 1274 */ 1275 #define IWN_EEPROM_MAC 0x015 1276 #define IWN_EEPROM_RFCFG 0x048 1277 #define IWN4965_EEPROM_DOMAIN 0x060 1278 #define IWN4965_EEPROM_BAND1 0x063 1279 #define IWN5000_EEPROM_REG 0x066 1280 #define IWN5000_EEPROM_CAL 0x067 1281 #define IWN4965_EEPROM_BAND2 0x072 1282 #define IWN4965_EEPROM_BAND3 0x080 1283 #define IWN4965_EEPROM_BAND4 0x08d 1284 #define IWN4965_EEPROM_BAND5 0x099 1285 #define IWN4965_EEPROM_BAND6 0x0a0 1286 #define IWN4965_EEPROM_BAND7 0x0a8 1287 #define IWN4965_EEPROM_MAXPOW 0x0e8 1288 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1289 #define IWN4965_EEPROM_BANDS 0x0ea 1290 /* Indirect offsets. */ 1291 #define IWN5000_EEPROM_DOMAIN 0x001 1292 #define IWN5000_EEPROM_BAND1 0x004 1293 #define IWN5000_EEPROM_BAND2 0x013 1294 #define IWN5000_EEPROM_BAND3 0x021 1295 #define IWN5000_EEPROM_BAND4 0x02e 1296 #define IWN5000_EEPROM_BAND5 0x03a 1297 #define IWN5000_EEPROM_BAND6 0x041 1298 #define IWN5000_EEPROM_BAND7 0x049 1299 #define IWN6000_EEPROM_ENHINFO 0x054 1300 #define IWN5000_EEPROM_CRYSTAL 0x128 1301 #define IWN5000_EEPROM_TEMP 0x12a 1302 #define IWN5000_EEPROM_VOLT 0x12b 1303 1304 /* Possible flags for IWN_EEPROM_RFCFG. */ 1305 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1306 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1307 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1308 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1309 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1310 1311 struct iwn_eeprom_chan { 1312 uint8_t flags; 1313 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1314 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1315 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1316 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1317 1318 int8_t maxpwr; 1319 } __packed; 1320 1321 struct iwn_eeprom_enhinfo { 1322 uint16_t chan; 1323 int8_t chain[3]; /* max power in half-dBm */ 1324 uint8_t reserved; 1325 int8_t mimo2; /* max power in half-dBm */ 1326 int8_t mimo3; /* max power in half-dBm */ 1327 } __packed; 1328 1329 struct iwn5000_eeprom_calib_hdr { 1330 uint8_t version; 1331 uint8_t pa_type; 1332 uint16_t volt; 1333 } __packed; 1334 1335 #define IWN_NSAMPLES 3 1336 struct iwn4965_eeprom_chan_samples { 1337 uint8_t num; 1338 struct { 1339 uint8_t temp; 1340 uint8_t gain; 1341 uint8_t power; 1342 int8_t pa_det; 1343 } samples[2][IWN_NSAMPLES]; 1344 } __packed; 1345 1346 #define IWN_NBANDS 8 1347 struct iwn4965_eeprom_band { 1348 uint8_t lo; /* low channel number */ 1349 uint8_t hi; /* high channel number */ 1350 struct iwn4965_eeprom_chan_samples chans[2]; 1351 } __packed; 1352 1353 /* 1354 * Offsets of channels descriptions in EEPROM. 1355 */ 1356 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1357 IWN4965_EEPROM_BAND1, 1358 IWN4965_EEPROM_BAND2, 1359 IWN4965_EEPROM_BAND3, 1360 IWN4965_EEPROM_BAND4, 1361 IWN4965_EEPROM_BAND5, 1362 IWN4965_EEPROM_BAND6, 1363 IWN4965_EEPROM_BAND7 1364 }; 1365 1366 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1367 IWN5000_EEPROM_BAND1, 1368 IWN5000_EEPROM_BAND2, 1369 IWN5000_EEPROM_BAND3, 1370 IWN5000_EEPROM_BAND4, 1371 IWN5000_EEPROM_BAND5, 1372 IWN5000_EEPROM_BAND6, 1373 IWN5000_EEPROM_BAND7 1374 }; 1375 1376 #define IWN_CHAN_BANDS_COUNT 7 1377 #define IWN_MAX_CHAN_PER_BAND 14 1378 static const struct iwn_chan_band { 1379 uint8_t nchan; 1380 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1381 } iwn_bands[] = { 1382 /* 20MHz channels, 2GHz band. */ 1383 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1384 /* 20MHz channels, 5GHz band. */ 1385 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1386 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1387 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1388 { 6, { 145, 149, 153, 157, 161, 165 } }, 1389 /* 40MHz channels (primary channels), 2GHz band. */ 1390 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1391 /* 40MHz channels (primary channels), 5GHz band. */ 1392 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1393 }; 1394 1395 #define IWN1000_OTP_NBLOCKS 3 1396 #define IWN6000_OTP_NBLOCKS 4 1397 #define IWN6050_OTP_NBLOCKS 7 1398 1399 /* HW rate indices. */ 1400 #define IWN_RIDX_CCK1 0 1401 #define IWN_RIDX_CCK11 3 1402 #define IWN_RIDX_OFDM6 4 1403 #define IWN_RIDX_OFDM54 11 1404 1405 static const struct iwn_rate { 1406 uint8_t rate; 1407 uint8_t plcp; 1408 uint8_t flags; 1409 } iwn_rates[IWN_RIDX_MAX + 1] = { 1410 { 2, 10, IWN_RFLAG_CCK }, 1411 { 4, 20, IWN_RFLAG_CCK }, 1412 { 11, 55, IWN_RFLAG_CCK }, 1413 { 22, 110, IWN_RFLAG_CCK }, 1414 { 12, 0xd, 0 }, 1415 { 18, 0xf, 0 }, 1416 { 24, 0x5, 0 }, 1417 { 36, 0x7, 0 }, 1418 { 48, 0x9, 0 }, 1419 { 72, 0xb, 0 }, 1420 { 96, 0x1, 0 }, 1421 { 108, 0x3, 0 }, 1422 { 120, 0x3, 0 } 1423 }; 1424 1425 #define IWN4965_MAX_PWR_INDEX 107 1426 1427 /* 1428 * RF Tx gain values from highest to lowest power (values obtained from 1429 * the reference driver.) 1430 */ 1431 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1432 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1433 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1434 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1435 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1436 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1437 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1440 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1442 }; 1443 1444 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1445 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1446 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1447 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1448 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1449 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1450 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1451 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1452 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1453 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1454 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1455 }; 1456 1457 /* 1458 * DSP pre-DAC gain values from highest to lowest power (values obtained 1459 * from the reference driver.) 1460 */ 1461 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1462 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1463 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1464 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1465 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1466 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1467 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1468 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1469 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1470 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1471 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1472 }; 1473 1474 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1475 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1476 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1477 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1478 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1479 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1480 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1481 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1482 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1483 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1484 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1485 }; 1486 1487 /* 1488 * Power saving settings (values obtained from the reference driver.) 1489 */ 1490 #define IWN_NDTIMRANGES 3 1491 #define IWN_NPOWERLEVELS 6 1492 static const struct iwn_pmgt { 1493 uint32_t rxtimeout; 1494 uint32_t txtimeout; 1495 uint32_t intval[5]; 1496 int skip_dtim; 1497 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1498 /* DTIM <= 2 */ 1499 { 1500 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1501 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1502 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1503 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1504 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1505 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1506 }, 1507 /* 3 <= DTIM <= 10 */ 1508 { 1509 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1510 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1511 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1512 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1513 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1514 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1515 }, 1516 /* DTIM >= 11 */ 1517 { 1518 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1519 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1520 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1521 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1522 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1523 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1524 } 1525 }; 1526 1527 struct iwn_sensitivity_limits { 1528 uint32_t min_ofdm_x1; 1529 uint32_t max_ofdm_x1; 1530 uint32_t min_ofdm_mrc_x1; 1531 uint32_t max_ofdm_mrc_x1; 1532 uint32_t min_ofdm_x4; 1533 uint32_t max_ofdm_x4; 1534 uint32_t min_ofdm_mrc_x4; 1535 uint32_t max_ofdm_mrc_x4; 1536 uint32_t min_cck_x4; 1537 uint32_t max_cck_x4; 1538 uint32_t min_cck_mrc_x4; 1539 uint32_t max_cck_mrc_x4; 1540 uint32_t min_energy_cck; 1541 uint32_t energy_cck; 1542 uint32_t energy_ofdm; 1543 }; 1544 1545 /* 1546 * RX sensitivity limits (values obtained from the reference driver.) 1547 */ 1548 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1549 105, 140, 1550 220, 270, 1551 85, 120, 1552 170, 210, 1553 125, 200, 1554 200, 400, 1555 97, 1556 100, 1557 100 1558 }; 1559 1560 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1561 120, 120, /* min = max for performance bug in DSP. */ 1562 240, 240, /* min = max for performance bug in DSP. */ 1563 90, 120, 1564 170, 210, 1565 125, 200, 1566 170, 400, 1567 95, 1568 95, 1569 95 1570 }; 1571 1572 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1573 105, 105, /* min = max for performance bug in DSP. */ 1574 220, 220, /* min = max for performance bug in DSP. */ 1575 90, 120, 1576 170, 210, 1577 125, 200, 1578 170, 400, 1579 95, 1580 95, 1581 95 1582 }; 1583 1584 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1585 120, 155, 1586 240, 290, 1587 90, 120, 1588 170, 210, 1589 125, 200, 1590 170, 400, 1591 95, 1592 95, 1593 95 1594 }; 1595 1596 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1597 105, 110, 1598 192, 232, 1599 80, 145, 1600 128, 232, 1601 125, 175, 1602 160, 310, 1603 97, 1604 97, 1605 100 1606 }; 1607 1608 /* Map TID to TX scheduler's FIFO. */ 1609 static const uint8_t iwn_tid2fifo[] = { 1610 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1611 }; 1612 1613 /* WiFi/WiMAX coexist event priority table for 6050. */ 1614 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1615 { 0x04, 0x03, 0x00, 0x00 }, 1616 { 0x04, 0x03, 0x00, 0x03 }, 1617 { 0x04, 0x03, 0x00, 0x03 }, 1618 { 0x04, 0x03, 0x00, 0x03 }, 1619 { 0x04, 0x03, 0x00, 0x00 }, 1620 { 0x04, 0x03, 0x00, 0x07 }, 1621 { 0x04, 0x03, 0x00, 0x00 }, 1622 { 0x04, 0x03, 0x00, 0x03 }, 1623 { 0x04, 0x03, 0x00, 0x03 }, 1624 { 0x04, 0x03, 0x00, 0x00 }, 1625 { 0x06, 0x03, 0x00, 0x07 }, 1626 { 0x04, 0x03, 0x00, 0x00 }, 1627 { 0x06, 0x06, 0x00, 0x03 }, 1628 { 0x04, 0x03, 0x00, 0x07 }, 1629 { 0x04, 0x03, 0x00, 0x00 }, 1630 { 0x04, 0x03, 0x00, 0x00 } 1631 }; 1632 1633 /* Firmware errors. */ 1634 static const char * const iwn_fw_errmsg[] = { 1635 "OK", 1636 "FAIL", 1637 "BAD_PARAM", 1638 "BAD_CHECKSUM", 1639 "NMI_INTERRUPT_WDG", 1640 "SYSASSERT", 1641 "FATAL_ERROR", 1642 "BAD_COMMAND", 1643 "HW_ERROR_TUNE_LOCK", 1644 "HW_ERROR_TEMPERATURE", 1645 "ILLEGAL_CHAN_FREQ", 1646 "VCC_NOT_STABLE", 1647 "FH_ERROR", 1648 "NMI_INTERRUPT_HOST", 1649 "NMI_INTERRUPT_ACTION_PT", 1650 "NMI_INTERRUPT_UNKNOWN", 1651 "UCODE_VERSION_MISMATCH", 1652 "HW_ERROR_ABS_LOCK", 1653 "HW_ERROR_CAL_LOCK_FAIL", 1654 "NMI_INTERRUPT_INST_ACTION_PT", 1655 "NMI_INTERRUPT_DATA_ACTION_PT", 1656 "NMI_TRM_HW_ER", 1657 "NMI_INTERRUPT_TRM", 1658 "NMI_INTERRUPT_BREAKPOINT" 1659 "DEBUG_0", 1660 "DEBUG_1", 1661 "DEBUG_2", 1662 "DEBUG_3", 1663 "ADVANCED_SYSASSERT" 1664 }; 1665 1666 /* Find least significant bit that is set. */ 1667 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1668 1669 #define IWN_READ(sc, reg) \ 1670 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1671 1672 #define IWN_WRITE(sc, reg, val) \ 1673 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1674 1675 #define IWN_WRITE_1(sc, reg, val) \ 1676 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1677 1678 #define IWN_SETBITS(sc, reg, mask) \ 1679 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1680 1681 #define IWN_CLRBITS(sc, reg, mask) \ 1682 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1683 1684 #define IWN_BARRIER_WRITE(sc) \ 1685 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1686 BUS_SPACE_BARRIER_WRITE) 1687 1688 #define IWN_BARRIER_READ_WRITE(sc) \ 1689 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1690 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
Cache object: 8e1a8e71e83955ced060589fc1b427b9
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