1 /* $FreeBSD: releng/9.1/sys/dev/iwn/if_iwnreg.h 227967 2011-11-25 12:19:13Z bschmidt $ */
2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */
3
4 /*-
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 #define IWN_TX_RING_COUNT 256
22 #define IWN_TX_RING_LOMARK 192
23 #define IWN_TX_RING_HIMARK 224
24 #define IWN_RX_RING_COUNT_LOG 6
25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
26
27 #define IWN4965_NTXQUEUES 16
28 #define IWN5000_NTXQUEUES 20
29
30 #define IWN4965_FIRSTAGGQUEUE 7
31 #define IWN5000_FIRSTAGGQUEUE 10
32
33 #define IWN4965_NDMACHNLS 7
34 #define IWN5000_NDMACHNLS 8
35
36 #define IWN_SRVC_DMACHNL 9
37
38 #define IWN_ICT_SIZE 4096
39 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
40
41 /* Maximum number of DMA segments for TX. */
42 #define IWN_MAX_SCATTER 20
43
44 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
45 #define IWN_RBUF_SIZE (4 * 1024)
46
47 #if defined(__LP64__)
48 /* HW supports 36-bit DMA addresses. */
49 #define IWN_LOADDR(paddr) ((uint32_t)(paddr))
50 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
51 #else
52 #define IWN_LOADDR(paddr) (paddr)
53 #define IWN_HIADDR(paddr) (0)
54 #endif
55
56 /*
57 * Control and status registers.
58 */
59 #define IWN_HW_IF_CONFIG 0x000
60 #define IWN_INT_COALESCING 0x004
61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
62 #define IWN_INT 0x008
63 #define IWN_INT_MASK 0x00c
64 #define IWN_FH_INT 0x010
65 #define IWN_RESET 0x020
66 #define IWN_GP_CNTRL 0x024
67 #define IWN_HW_REV 0x028
68 #define IWN_EEPROM 0x02c
69 #define IWN_EEPROM_GP 0x030
70 #define IWN_OTP_GP 0x034
71 #define IWN_GIO 0x03c
72 #define IWN_GP_DRIVER 0x050
73 #define IWN_UCODE_GP1_CLR 0x05c
74 #define IWN_LED 0x094
75 #define IWN_DRAM_INT_TBL 0x0a0
76 #define IWN_SHADOW_REG_CTRL 0x0a8
77 #define IWN_GIO_CHICKEN 0x100
78 #define IWN_ANA_PLL 0x20c
79 #define IWN_HW_REV_WA 0x22c
80 #define IWN_DBG_HPET_MEM 0x240
81 #define IWN_DBG_LINK_PWR_MGMT 0x250
82 #define IWN_MEM_RADDR 0x40c
83 #define IWN_MEM_WADDR 0x410
84 #define IWN_MEM_WDATA 0x418
85 #define IWN_MEM_RDATA 0x41c
86 #define IWN_PRPH_WADDR 0x444
87 #define IWN_PRPH_RADDR 0x448
88 #define IWN_PRPH_WDATA 0x44c
89 #define IWN_PRPH_RDATA 0x450
90 #define IWN_HBUS_TARG_WRPTR 0x460
91
92 /*
93 * Flow-Handler registers.
94 */
95 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
96 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
97 #define IWN_FH_KW_ADDR 0x197c
98 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
99 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
100 #define IWN_FH_STATUS_WPTR 0x1bc0
101 #define IWN_FH_RX_BASE 0x1bc4
102 #define IWN_FH_RX_WPTR 0x1bc8
103 #define IWN_FH_RX_CONFIG 0x1c00
104 #define IWN_FH_RX_STATUS 0x1c44
105 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
106 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
107 #define IWN_FH_TX_CHICKEN 0x1e98
108 #define IWN_FH_TX_STATUS 0x1eb0
109
110 /*
111 * TX scheduler registers.
112 */
113 #define IWN_SCHED_BASE 0xa02c00
114 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
115 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
116 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
117 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
118 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
119 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
120 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
121 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
122 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
123 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
124 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
125 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
126 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
127 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
128
129 /*
130 * Offsets in TX scheduler's SRAM.
131 */
132 #define IWN4965_SCHED_CTX_OFF 0x380
133 #define IWN4965_SCHED_CTX_LEN 416
134 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
135 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
136 #define IWN5000_SCHED_CTX_OFF 0x600
137 #define IWN5000_SCHED_CTX_LEN 520
138 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
139 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
140
141 /*
142 * NIC internal memory offsets.
143 */
144 #define IWN_APMG_CLK_CTRL 0x3000
145 #define IWN_APMG_CLK_EN 0x3004
146 #define IWN_APMG_CLK_DIS 0x3008
147 #define IWN_APMG_PS 0x300c
148 #define IWN_APMG_DIGITAL_SVR 0x3058
149 #define IWN_APMG_ANALOG_SVR 0x306c
150 #define IWN_APMG_PCI_STT 0x3010
151 #define IWN_BSM_WR_CTRL 0x3400
152 #define IWN_BSM_WR_MEM_SRC 0x3404
153 #define IWN_BSM_WR_MEM_DST 0x3408
154 #define IWN_BSM_WR_DWCOUNT 0x340c
155 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
156 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
157 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
158 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
159 #define IWN_BSM_SRAM_BASE 0x3800
160
161 /* Possible flags for register IWN_HW_IF_CONFIG. */
162 #define IWN_HW_IF_CONFIG_4965_R (1 << 4)
163 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
164 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
165 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
166 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
167 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
168 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
169 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
170
171 /* Possible values for register IWN_INT_PERIODIC. */
172 #define IWN_INT_PERIODIC_DIS 0x00
173 #define IWN_INT_PERIODIC_ENA 0xff
174
175 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
176 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
177
178 /* Possible values for IWN_BSM_WR_MEM_DST. */
179 #define IWN_FW_TEXT_BASE 0x00000000
180 #define IWN_FW_DATA_BASE 0x00800000
181
182 /* Possible flags for register IWN_RESET. */
183 #define IWN_RESET_NEVO (1 << 0)
184 #define IWN_RESET_SW (1 << 7)
185 #define IWN_RESET_MASTER_DISABLED (1 << 8)
186 #define IWN_RESET_STOP_MASTER (1 << 9)
187 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31)
188
189 /* Possible flags for register IWN_GP_CNTRL. */
190 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
191 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
192 #define IWN_GP_CNTRL_INIT_DONE (1 << 2)
193 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
194 #define IWN_GP_CNTRL_SLEEP (1 << 4)
195 #define IWN_GP_CNTRL_RFKILL (1 << 27)
196
197 /* Possible flags for register IWN_HW_REV. */
198 #define IWN_HW_REV_TYPE_SHIFT 4
199 #define IWN_HW_REV_TYPE_MASK 0x000000f0
200 #define IWN_HW_REV_TYPE_4965 0
201 #define IWN_HW_REV_TYPE_5300 2
202 #define IWN_HW_REV_TYPE_5350 3
203 #define IWN_HW_REV_TYPE_5150 4
204 #define IWN_HW_REV_TYPE_5100 5
205 #define IWN_HW_REV_TYPE_1000 6
206 #define IWN_HW_REV_TYPE_6000 7
207 #define IWN_HW_REV_TYPE_6050 8
208 #define IWN_HW_REV_TYPE_6005 11
209
210 /* Possible flags for register IWN_GIO_CHICKEN. */
211 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
212 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
213
214 /* Possible flags for register IWN_GIO. */
215 #define IWN_GIO_L0S_ENA (1 << 1)
216
217 /* Possible flags for register IWN_GP_DRIVER. */
218 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
219 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
220 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
221 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2)
222 #define IWN_GP_DRIVER_6050_1X2 (1 << 3)
223
224 /* Possible flags for register IWN_UCODE_GP1_CLR. */
225 #define IWN_UCODE_GP1_RFKILL (1 << 1)
226 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
227 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
228
229 /* Possible flags/values for register IWN_LED. */
230 #define IWN_LED_BSM_CTRL (1 << 5)
231 #define IWN_LED_OFF 0x00000038
232 #define IWN_LED_ON 0x00000078
233
234 /* Possible flags for register IWN_DRAM_INT_TBL. */
235 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
236 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31)
237
238 /* Possible values for register IWN_ANA_PLL. */
239 #define IWN_ANA_PLL_INIT 0x00880300
240
241 /* Possible flags for register IWN_FH_RX_STATUS. */
242 #define IWN_FH_RX_STATUS_IDLE (1 << 24)
243
244 /* Possible flags for register IWN_BSM_WR_CTRL. */
245 #define IWN_BSM_WR_CTRL_START_EN (1 << 30)
246 #define IWN_BSM_WR_CTRL_START (1 << 31)
247
248 /* Possible flags for register IWN_INT. */
249 #define IWN_INT_ALIVE (1 << 0)
250 #define IWN_INT_WAKEUP (1 << 1)
251 #define IWN_INT_SW_RX (1 << 3)
252 #define IWN_INT_CT_REACHED (1 << 6)
253 #define IWN_INT_RF_TOGGLED (1 << 7)
254 #define IWN_INT_SW_ERR (1 << 25)
255 #define IWN_INT_SCHED (1 << 26)
256 #define IWN_INT_FH_TX (1 << 27)
257 #define IWN_INT_RX_PERIODIC (1 << 28)
258 #define IWN_INT_HW_ERR (1 << 29)
259 #define IWN_INT_FH_RX (1 << 31)
260
261 /* Shortcut. */
262 #define IWN_INT_MASK_DEF \
263 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
264 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
265 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
266
267 /* Possible flags for register IWN_FH_INT. */
268 #define IWN_FH_INT_TX_CHNL(x) (1 << (x))
269 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
270 #define IWN_FH_INT_HI_PRIOR (1 << 30)
271 /* Shortcuts for the above. */
272 #define IWN_FH_INT_TX \
273 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
274 #define IWN_FH_INT_RX \
275 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
276
277 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
278 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
279 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
280 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
281
282 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
283 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
284 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
285 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3
286
287 /* Possible flags for register IWN_FH_TX_CHICKEN. */
288 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
289
290 /* Possible flags for register IWN_FH_TX_STATUS. */
291 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))
292
293 /* Possible flags for register IWN_FH_RX_CONFIG. */
294 #define IWN_FH_RX_CONFIG_ENA (1 << 31)
295 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
296 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
297 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
298 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12)
299 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
300 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
301
302 /* Possible flags for register IWN_FH_TX_CONFIG. */
303 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
304 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
305
306 /* Possible flags for register IWN_EEPROM. */
307 #define IWN_EEPROM_READ_VALID (1 << 0)
308 #define IWN_EEPROM_CMD (1 << 1)
309
310 /* Possible flags for register IWN_EEPROM_GP. */
311 #define IWN_EEPROM_GP_IF_OWNER 0x00000180
312
313 /* Possible flags for register IWN_OTP_GP. */
314 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16)
315 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17)
316 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20)
317 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21)
318
319 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
320 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
321 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
322 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
323 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
324 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
325 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
326 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
327
328 /* Possible flags for registers IWN_APMG_CLK_*. */
329 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
330 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
331
332 /* Possible flags for register IWN_APMG_PS. */
333 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
334 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
335 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
336 #define IWN_APMG_PS_PWR_SRC_VAUX 2
337 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
338 #define IWN_APMG_PS_RESET_REQ (1 << 26)
339
340 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
341 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
342 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \
343 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
344 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \
345 IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
346
347 /* Possible flags for IWN_APMG_PCI_STT. */
348 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
349
350 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
351 #define IWN_FW_UPDATED (1 << 31)
352
353 #define IWN_SCHED_WINSZ 64
354 #define IWN_SCHED_LIMIT 64
355 #define IWN4965_SCHED_COUNT 512
356 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
357 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
358 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
359
360 struct iwn_tx_desc {
361 uint8_t reserved1[3];
362 uint8_t nsegs;
363 struct {
364 uint32_t addr;
365 uint16_t len;
366 } __packed segs[IWN_MAX_SCATTER];
367 /* Pad to 128 bytes. */
368 uint32_t reserved2;
369 } __packed;
370
371 struct iwn_rx_status {
372 uint16_t closed_count;
373 uint16_t closed_rx_count;
374 uint16_t finished_count;
375 uint16_t finished_rx_count;
376 uint32_t reserved[2];
377 } __packed;
378
379 struct iwn_rx_desc {
380 uint32_t len;
381 uint8_t type;
382 #define IWN_UC_READY 1
383 #define IWN_ADD_NODE_DONE 24
384 #define IWN_TX_DONE 28
385 #define IWN5000_CALIBRATION_RESULT 102
386 #define IWN5000_CALIBRATION_DONE 103
387 #define IWN_START_SCAN 130
388 #define IWN_STOP_SCAN 132
389 #define IWN_RX_STATISTICS 156
390 #define IWN_BEACON_STATISTICS 157
391 #define IWN_STATE_CHANGED 161
392 #define IWN_BEACON_MISSED 162
393 #define IWN_RX_PHY 192
394 #define IWN_MPDU_RX_DONE 193
395 #define IWN_RX_DONE 195
396 #define IWN_RX_COMPRESSED_BA 197
397
398 uint8_t flags;
399 uint8_t idx;
400 uint8_t qid;
401 } __packed;
402
403 /* Possible RX status flags. */
404 #define IWN_RX_NO_CRC_ERR (1 << 0)
405 #define IWN_RX_NO_OVFL_ERR (1 << 1)
406 /* Shortcut for the above. */
407 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
408 #define IWN_RX_MPDU_MIC_OK (1 << 6)
409 #define IWN_RX_CIPHER_MASK (7 << 8)
410 #define IWN_RX_CIPHER_CCMP (2 << 8)
411 #define IWN_RX_MPDU_DEC (1 << 11)
412 #define IWN_RX_DECRYPT_MASK (3 << 11)
413 #define IWN_RX_DECRYPT_OK (3 << 11)
414
415 struct iwn_tx_cmd {
416 uint8_t code;
417 #define IWN_CMD_RXON 16
418 #define IWN_CMD_RXON_ASSOC 17
419 #define IWN_CMD_EDCA_PARAMS 19
420 #define IWN_CMD_TIMING 20
421 #define IWN_CMD_ADD_NODE 24
422 #define IWN_CMD_TX_DATA 28
423 #define IWN_CMD_LINK_QUALITY 78
424 #define IWN_CMD_SET_LED 72
425 #define IWN5000_CMD_WIMAX_COEX 90
426 #define IWN5000_CMD_CALIB_CONFIG 101
427 #define IWN5000_CMD_CALIB_RESULT 102
428 #define IWN5000_CMD_CALIB_COMPLETE 103
429 #define IWN_CMD_SET_POWER_MODE 119
430 #define IWN_CMD_SCAN 128
431 #define IWN_CMD_SCAN_RESULTS 131
432 #define IWN_CMD_TXPOWER_DBM 149
433 #define IWN_CMD_TXPOWER 151
434 #define IWN5000_CMD_TX_ANT_CONFIG 152
435 #define IWN_CMD_BT_COEX 155
436 #define IWN_CMD_GET_STATISTICS 156
437 #define IWN_CMD_SET_CRITICAL_TEMP 164
438 #define IWN_CMD_SET_SENSITIVITY 168
439 #define IWN_CMD_PHY_CALIB 176
440 #define IWN_CMD_BT_COEX_PRIOTABLE 204
441 #define IWN_CMD_BT_COEX_PROT 205
442
443 uint8_t flags;
444 uint8_t idx;
445 uint8_t qid;
446 uint8_t data[136];
447 } __packed;
448
449 /* Antenna flags, used in various commands. */
450 #define IWN_ANT_A (1 << 0)
451 #define IWN_ANT_B (1 << 1)
452 #define IWN_ANT_C (1 << 2)
453 /* Shortcuts. */
454 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B)
455 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C)
456 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
457
458 /* Structure for command IWN_CMD_RXON. */
459 struct iwn_rxon {
460 uint8_t myaddr[IEEE80211_ADDR_LEN];
461 uint16_t reserved1;
462 uint8_t bssid[IEEE80211_ADDR_LEN];
463 uint16_t reserved2;
464 uint8_t wlap[IEEE80211_ADDR_LEN];
465 uint16_t reserved3;
466 uint8_t mode;
467 #define IWN_MODE_HOSTAP 1
468 #define IWN_MODE_STA 3
469 #define IWN_MODE_IBSS 4
470 #define IWN_MODE_MONITOR 6
471
472 uint8_t air;
473 uint16_t rxchain;
474 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
475 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
476 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
477 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
478 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
479 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
480 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
481
482 uint8_t ofdm_mask;
483 uint8_t cck_mask;
484 uint16_t associd;
485 uint32_t flags;
486 #define IWN_RXON_24GHZ (1 << 0)
487 #define IWN_RXON_CCK (1 << 1)
488 #define IWN_RXON_AUTO (1 << 2)
489 #define IWN_RXON_SHSLOT (1 << 4)
490 #define IWN_RXON_SHPREAMBLE (1 << 5)
491 #define IWN_RXON_NODIVERSITY (1 << 7)
492 #define IWN_RXON_ANTENNA_A (1 << 8)
493 #define IWN_RXON_ANTENNA_B (1 << 9)
494 #define IWN_RXON_TSF (1 << 15)
495 #define IWN_RXON_HT_HT40MINUS (1 << 22)
496 #define IWN_RXON_HT_PROTMODE(x) (x << 23)
497 #define IWN_RXON_HT_MODEPURE40 (1 << 25)
498 #define IWN_RXON_HT_MODEMIXED (2 << 25)
499 #define IWN_RXON_CTS_TO_SELF (1 << 30)
500
501 uint32_t filter;
502 #define IWN_FILTER_PROMISC (1 << 0)
503 #define IWN_FILTER_CTL (1 << 1)
504 #define IWN_FILTER_MULTICAST (1 << 2)
505 #define IWN_FILTER_NODECRYPT (1 << 3)
506 #define IWN_FILTER_BSS (1 << 5)
507 #define IWN_FILTER_BEACON (1 << 6)
508
509 uint8_t chan;
510 uint8_t reserved4;
511 uint8_t ht_single_mask;
512 uint8_t ht_dual_mask;
513 /* The following fields are for >=5000 Series only. */
514 uint8_t ht_triple_mask;
515 uint8_t reserved5;
516 uint16_t acquisition;
517 uint16_t reserved6;
518 } __packed;
519
520 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
521 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
522
523 /* Structure for command IWN_CMD_ASSOCIATE. */
524 struct iwn_assoc {
525 uint32_t flags;
526 uint32_t filter;
527 uint8_t ofdm_mask;
528 uint8_t cck_mask;
529 uint16_t reserved;
530 } __packed;
531
532 /* Structure for command IWN_CMD_EDCA_PARAMS. */
533 struct iwn_edca_params {
534 uint32_t flags;
535 #define IWN_EDCA_UPDATE (1 << 0)
536 #define IWN_EDCA_TXOP (1 << 4)
537
538 struct {
539 uint16_t cwmin;
540 uint16_t cwmax;
541 uint8_t aifsn;
542 uint8_t reserved;
543 uint16_t txoplimit;
544 } __packed ac[WME_NUM_AC];
545 } __packed;
546
547 /* Structure for command IWN_CMD_TIMING. */
548 struct iwn_cmd_timing {
549 uint64_t tstamp;
550 uint16_t bintval;
551 uint16_t atim;
552 uint32_t binitval;
553 uint16_t lintval;
554 uint16_t reserved;
555 } __packed;
556
557 /* Structure for command IWN_CMD_ADD_NODE. */
558 struct iwn_node_info {
559 uint8_t control;
560 #define IWN_NODE_UPDATE (1 << 0)
561
562 uint8_t reserved1[3];
563
564 uint8_t macaddr[IEEE80211_ADDR_LEN];
565 uint16_t reserved2;
566 uint8_t id;
567 #define IWN_ID_BSS 0
568 #define IWN5000_ID_BROADCAST 15
569 #define IWN4965_ID_BROADCAST 31
570
571 uint8_t flags;
572 #define IWN_FLAG_SET_KEY (1 << 0)
573 #define IWN_FLAG_SET_DISABLE_TID (1 << 1)
574 #define IWN_FLAG_SET_TXRATE (1 << 2)
575 #define IWN_FLAG_SET_ADDBA (1 << 3)
576 #define IWN_FLAG_SET_DELBA (1 << 4)
577
578 uint16_t reserved3;
579 uint16_t kflags;
580 #define IWN_KFLAG_CCMP (1 << 1)
581 #define IWN_KFLAG_MAP (1 << 3)
582 #define IWN_KFLAG_KID(kid) ((kid) << 8)
583 #define IWN_KFLAG_INVALID (1 << 11)
584 #define IWN_KFLAG_GROUP (1 << 14)
585
586 uint8_t tsc2; /* TKIP TSC2 */
587 uint8_t reserved4;
588 uint16_t ttak[5];
589 uint8_t kid;
590 uint8_t reserved5;
591 uint8_t key[16];
592 /* The following 3 fields are for 5000 Series only. */
593 uint64_t tsc;
594 uint8_t rxmic[8];
595 uint8_t txmic[8];
596
597 uint32_t htflags;
598 #define IWN_SMPS_MIMO_PROT (1 << 17)
599 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19)
600 #define IWN_NODE_HT40 (1 << 21)
601 #define IWN_SMPS_MIMO_DIS (1 << 22)
602 #define IWN_AMDPU_DENSITY(x) ((x) << 23)
603
604 uint32_t mask;
605 uint16_t disable_tid;
606 uint16_t reserved6;
607 uint8_t addba_tid;
608 uint8_t delba_tid;
609 uint16_t addba_ssn;
610 uint32_t reserved7;
611 } __packed;
612
613 struct iwn4965_node_info {
614 uint8_t control;
615 uint8_t reserved1[3];
616 uint8_t macaddr[IEEE80211_ADDR_LEN];
617 uint16_t reserved2;
618 uint8_t id;
619 uint8_t flags;
620 uint16_t reserved3;
621 uint16_t kflags;
622 uint8_t tsc2; /* TKIP TSC2 */
623 uint8_t reserved4;
624 uint16_t ttak[5];
625 uint8_t kid;
626 uint8_t reserved5;
627 uint8_t key[16];
628 uint32_t htflags;
629 uint32_t mask;
630 uint16_t disable_tid;
631 uint16_t reserved6;
632 uint8_t addba_tid;
633 uint8_t delba_tid;
634 uint16_t addba_ssn;
635 uint32_t reserved7;
636 } __packed;
637
638 #define IWN_RFLAG_MCS (1 << 8)
639 #define IWN_RFLAG_CCK (1 << 9)
640 #define IWN_RFLAG_GREENFIELD (1 << 10)
641 #define IWN_RFLAG_HT40 (1 << 11)
642 #define IWN_RFLAG_DUPLICATE (1 << 12)
643 #define IWN_RFLAG_SGI (1 << 13)
644 #define IWN_RFLAG_ANT(x) ((x) << 14)
645
646 /* Structure for command IWN_CMD_TX_DATA. */
647 struct iwn_cmd_data {
648 uint16_t len;
649 uint16_t lnext;
650 uint32_t flags;
651 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
652 #define IWN_TX_NEED_RTS (1 << 1)
653 #define IWN_TX_NEED_CTS (1 << 2)
654 #define IWN_TX_NEED_ACK (1 << 3)
655 #define IWN_TX_LINKQ (1 << 4)
656 #define IWN_TX_IMM_BA (1 << 6)
657 #define IWN_TX_FULL_TXOP (1 << 7)
658 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
659 #define IWN_TX_AUTO_SEQ (1 << 13)
660 #define IWN_TX_MORE_FRAG (1 << 14)
661 #define IWN_TX_INSERT_TSTAMP (1 << 16)
662 #define IWN_TX_NEED_PADDING (1 << 20)
663
664 uint32_t scratch;
665 uint32_t rate;
666
667 uint8_t id;
668 uint8_t security;
669 #define IWN_CIPHER_WEP40 1
670 #define IWN_CIPHER_CCMP 2
671 #define IWN_CIPHER_TKIP 3
672 #define IWN_CIPHER_WEP104 9
673
674 uint8_t linkq;
675 uint8_t reserved2;
676 uint8_t key[16];
677 uint16_t fnext;
678 uint16_t reserved3;
679 uint32_t lifetime;
680 #define IWN_LIFETIME_INFINITE 0xffffffff
681
682 uint32_t loaddr;
683 uint8_t hiaddr;
684 uint8_t rts_ntries;
685 uint8_t data_ntries;
686 uint8_t tid;
687 uint16_t timeout;
688 uint16_t txop;
689 } __packed;
690
691 /* Structure for command IWN_CMD_LINK_QUALITY. */
692 #define IWN_MAX_TX_RETRIES 16
693 struct iwn_cmd_link_quality {
694 uint8_t id;
695 uint8_t reserved1;
696 uint16_t ctl;
697 uint8_t flags;
698 uint8_t mimo;
699 uint8_t antmsk_1stream;
700 uint8_t antmsk_2stream;
701 uint8_t ridx[WME_NUM_AC];
702 uint16_t ampdu_limit;
703 uint8_t ampdu_threshold;
704 uint8_t ampdu_max;
705 uint32_t reserved2;
706 uint32_t retry[IWN_MAX_TX_RETRIES];
707 uint32_t reserved3;
708 } __packed;
709
710 /* Structure for command IWN_CMD_SET_LED. */
711 struct iwn_cmd_led {
712 uint32_t unit; /* multiplier (in usecs) */
713 uint8_t which;
714 #define IWN_LED_ACTIVITY 1
715 #define IWN_LED_LINK 2
716
717 uint8_t off;
718 uint8_t on;
719 uint8_t reserved;
720 } __packed;
721
722 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
723 struct iwn5000_wimax_coex {
724 uint32_t flags;
725 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
726 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
727 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
728 #define IWN_WIMAX_COEX_ENABLE (1 << 7)
729
730 struct iwn5000_wimax_event {
731 uint8_t request;
732 uint8_t window;
733 uint8_t reserved;
734 uint8_t flags;
735 } __packed events[16];
736 } __packed;
737
738 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
739 struct iwn5000_calib_elem {
740 uint32_t enable;
741 uint32_t start;
742 #define IWN5000_CALIB_DC (1 << 1)
743
744 uint32_t send;
745 uint32_t apply;
746 uint32_t reserved;
747 } __packed;
748
749 struct iwn5000_calib_status {
750 struct iwn5000_calib_elem once;
751 struct iwn5000_calib_elem perd;
752 uint32_t flags;
753 } __packed;
754
755 struct iwn5000_calib_config {
756 struct iwn5000_calib_status ucode;
757 struct iwn5000_calib_status driver;
758 uint32_t reserved;
759 } __packed;
760
761 /* Structure for command IWN_CMD_SET_POWER_MODE. */
762 struct iwn_pmgt_cmd {
763 uint16_t flags;
764 #define IWN_PS_ALLOW_SLEEP (1 << 0)
765 #define IWN_PS_NOTIFY (1 << 1)
766 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2)
767 #define IWN_PS_PCI_PMGT (1 << 3)
768 #define IWN_PS_FAST_PD (1 << 4)
769
770 uint8_t keepalive;
771 uint8_t debug;
772 uint32_t rxtimeout;
773 uint32_t txtimeout;
774 uint32_t intval[5];
775 uint32_t beacons;
776 } __packed;
777
778 /* Structures for command IWN_CMD_SCAN. */
779 struct iwn_scan_essid {
780 uint8_t id;
781 uint8_t len;
782 uint8_t data[IEEE80211_NWID_LEN];
783 } __packed;
784
785 struct iwn_scan_hdr {
786 uint16_t len;
787 uint8_t reserved1;
788 uint8_t nchan;
789 uint16_t quiet_time;
790 uint16_t quiet_threshold;
791 uint16_t crc_threshold;
792 uint16_t rxchain;
793 uint32_t max_svc; /* background scans */
794 uint32_t pause_svc; /* background scans */
795 uint32_t flags;
796 uint32_t filter;
797
798 /* Followed by a struct iwn_cmd_data. */
799 /* Followed by an array of 20 structs iwn_scan_essid. */
800 /* Followed by probe request body. */
801 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */
802 } __packed;
803
804 struct iwn_scan_chan {
805 uint32_t flags;
806 #define IWN_CHAN_ACTIVE (1 << 0)
807 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
808
809 uint16_t chan;
810 uint8_t rf_gain;
811 uint8_t dsp_gain;
812 uint16_t active; /* msecs */
813 uint16_t passive; /* msecs */
814 } __packed;
815
816 /* Maximum size of a scan command. */
817 #define IWN_SCAN_MAXSZ (MCLBYTES - 4)
818
819 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
820 #define IWN_RIDX_MAX 32
821 struct iwn4965_cmd_txpower {
822 uint8_t band;
823 uint8_t reserved1;
824 uint8_t chan;
825 uint8_t reserved2;
826 struct {
827 uint8_t rf_gain[2];
828 uint8_t dsp_gain[2];
829 } __packed power[IWN_RIDX_MAX + 1];
830 } __packed;
831
832 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
833 struct iwn5000_cmd_txpower {
834 int8_t global_limit; /* in half-dBm */
835 #define IWN5000_TXPOWER_AUTO 0x7f
836 #define IWN5000_TXPOWER_MAX_DBM 16
837
838 uint8_t flags;
839 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6)
840
841 int8_t srv_limit; /* in half-dBm */
842 uint8_t reserved;
843 } __packed;
844
845 /* Structures for command IWN_CMD_BLUETOOTH. */
846 struct iwn_bluetooth {
847 uint8_t flags;
848 #define IWN_BT_COEX_CHAN_ANN (1 << 0)
849 #define IWN_BT_COEX_BT_PRIO (1 << 1)
850 #define IWN_BT_COEX_2_WIRE (1 << 2)
851
852 uint8_t lead_time;
853 #define IWN_BT_LEAD_TIME_DEF 30
854
855 uint8_t max_kill;
856 #define IWN_BT_MAX_KILL_DEF 5
857
858 uint8_t reserved;
859 uint32_t kill_ack;
860 uint32_t kill_cts;
861 } __packed;
862
863 struct iwn6000_btcoex_config {
864 uint8_t flags;
865 uint8_t lead_time;
866 uint8_t max_kill;
867 uint8_t bt3_t7_timer;
868 uint32_t kill_ack;
869 uint32_t kill_cts;
870 uint8_t sample_time;
871 uint8_t bt3_t2_timer;
872 uint16_t bt4_reaction;
873 uint32_t lookup_table[12];
874 uint16_t bt4_decision;
875 uint16_t valid;
876 uint8_t prio_boost;
877 uint8_t tx_prio_boost;
878 uint16_t rx_prio_boost;
879 } __packed;
880
881 struct iwn_btcoex_priotable {
882 uint8_t calib_init1;
883 uint8_t calib_init2;
884 uint8_t calib_periodic_low1;
885 uint8_t calib_periodic_low2;
886 uint8_t calib_periodic_high1;
887 uint8_t calib_periodic_high2;
888 uint8_t dtim;
889 uint8_t scan52;
890 uint8_t scan24;
891 uint8_t reserved[7];
892 } __packed;
893
894 struct iwn_btcoex_prot {
895 uint8_t open;
896 uint8_t type;
897 uint8_t reserved[2];
898 } __packed;
899
900 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
901 struct iwn_critical_temp {
902 uint32_t reserved;
903 uint32_t tempM;
904 uint32_t tempR;
905 /* degK <-> degC conversion macros. */
906 #define IWN_CTOK(c) ((c) + 273)
907 #define IWN_KTOC(k) ((k) - 273)
908 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
909 } __packed;
910
911 /* Structures for command IWN_CMD_SET_SENSITIVITY. */
912 struct iwn_sensitivity_cmd {
913 uint16_t which;
914 #define IWN_SENSITIVITY_DEFAULTTBL 0
915 #define IWN_SENSITIVITY_WORKTBL 1
916
917 uint16_t energy_cck;
918 uint16_t energy_ofdm;
919 uint16_t corr_ofdm_x1;
920 uint16_t corr_ofdm_mrc_x1;
921 uint16_t corr_cck_mrc_x4;
922 uint16_t corr_ofdm_x4;
923 uint16_t corr_ofdm_mrc_x4;
924 uint16_t corr_barker;
925 uint16_t corr_barker_mrc;
926 uint16_t corr_cck_x4;
927 uint16_t energy_ofdm_th;
928 } __packed;
929
930 struct iwn_enhanced_sensitivity_cmd {
931 uint16_t which;
932 uint16_t energy_cck;
933 uint16_t energy_ofdm;
934 uint16_t corr_ofdm_x1;
935 uint16_t corr_ofdm_mrc_x1;
936 uint16_t corr_cck_mrc_x4;
937 uint16_t corr_ofdm_x4;
938 uint16_t corr_ofdm_mrc_x4;
939 uint16_t corr_barker;
940 uint16_t corr_barker_mrc;
941 uint16_t corr_cck_x4;
942 uint16_t energy_ofdm_th;
943 /* "Enhanced" part. */
944 uint16_t ina_det_ofdm;
945 uint16_t ina_det_cck;
946 uint16_t corr_11_9_en;
947 uint16_t ofdm_det_slope_mrc;
948 uint16_t ofdm_det_icept_mrc;
949 uint16_t ofdm_det_slope;
950 uint16_t ofdm_det_icept;
951 uint16_t cck_det_slope_mrc;
952 uint16_t cck_det_icept_mrc;
953 uint16_t cck_det_slope;
954 uint16_t cck_det_icept;
955 uint16_t reserved;
956 } __packed;
957
958 /* Structures for command IWN_CMD_PHY_CALIB. */
959 struct iwn_phy_calib {
960 uint8_t code;
961 #define IWN4965_PHY_CALIB_DIFF_GAIN 7
962 #define IWN5000_PHY_CALIB_DC 8
963 #define IWN5000_PHY_CALIB_LO 9
964 #define IWN5000_PHY_CALIB_TX_IQ 11
965 #define IWN5000_PHY_CALIB_CRYSTAL 15
966 #define IWN5000_PHY_CALIB_BASE_BAND 16
967 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17
968 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18
969
970 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
971 #define IWN5000_PHY_CALIB_NOISE_GAIN 19
972
973 uint8_t group;
974 uint8_t ngroups;
975 uint8_t isvalid;
976 } __packed;
977
978 struct iwn5000_phy_calib_crystal {
979 uint8_t code;
980 uint8_t group;
981 uint8_t ngroups;
982 uint8_t isvalid;
983
984 uint8_t cap_pin[2];
985 uint8_t reserved[2];
986 } __packed;
987
988 struct iwn5000_phy_calib_temp_offset {
989 uint8_t code;
990 uint8_t group;
991 uint8_t ngroups;
992 uint8_t isvalid;
993 int16_t offset;
994 #define IWN_DEFAULT_TEMP_OFFSET 2700
995
996 uint16_t reserved;
997 } __packed;
998
999 struct iwn_phy_calib_gain {
1000 uint8_t code;
1001 uint8_t group;
1002 uint8_t ngroups;
1003 uint8_t isvalid;
1004
1005 int8_t gain[3];
1006 uint8_t reserved;
1007 } __packed;
1008
1009 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
1010 struct iwn_spectrum_cmd {
1011 uint16_t len;
1012 uint8_t token;
1013 uint8_t id;
1014 uint8_t origin;
1015 uint8_t periodic;
1016 uint16_t timeout;
1017 uint32_t start;
1018 uint32_t reserved1;
1019 uint32_t flags;
1020 uint32_t filter;
1021 uint16_t nchan;
1022 uint16_t reserved2;
1023 struct {
1024 uint32_t duration;
1025 uint8_t chan;
1026 uint8_t type;
1027 #define IWN_MEASUREMENT_BASIC (1 << 0)
1028 #define IWN_MEASUREMENT_CCA (1 << 1)
1029 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
1030 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
1031 #define IWN_MEASUREMENT_FRAME (1 << 4)
1032 #define IWN_MEASUREMENT_IDLE (1 << 7)
1033
1034 uint16_t reserved;
1035 } __packed chan[10];
1036 } __packed;
1037
1038 /* Structure for IWN_UC_READY notification. */
1039 #define IWN_NATTEN_GROUPS 5
1040 struct iwn_ucode_info {
1041 uint8_t minor;
1042 uint8_t major;
1043 uint16_t reserved1;
1044 uint8_t revision[8];
1045 uint8_t type;
1046 uint8_t subtype;
1047 #define IWN_UCODE_RUNTIME 0
1048 #define IWN_UCODE_INIT 9
1049
1050 uint16_t reserved2;
1051 uint32_t logptr;
1052 uint32_t errptr;
1053 uint32_t tstamp;
1054 uint32_t valid;
1055
1056 /* The following fields are for UCODE_INIT only. */
1057 int32_t volt;
1058 struct {
1059 int32_t chan20MHz;
1060 int32_t chan40MHz;
1061 } __packed temp[4];
1062 int32_t atten[IWN_NATTEN_GROUPS][2];
1063 } __packed;
1064
1065 /* Structures for IWN_TX_DONE notification. */
1066 #define IWN_TX_SUCCESS 0x00
1067 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
1068 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
1069 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
1070 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
1071 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
1072 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
1073
1074 struct iwn4965_tx_stat {
1075 uint8_t nframes;
1076 uint8_t btkillcnt;
1077 uint8_t rtsfailcnt;
1078 uint8_t ackfailcnt;
1079 uint32_t rate;
1080 uint16_t duration;
1081 uint16_t reserved;
1082 uint32_t power[2];
1083 uint32_t status;
1084 } __packed;
1085
1086 struct iwn5000_tx_stat {
1087 uint8_t nframes;
1088 uint8_t btkillcnt;
1089 uint8_t rtsfailcnt;
1090 uint8_t ackfailcnt;
1091 uint32_t rate;
1092 uint16_t duration;
1093 uint16_t reserved;
1094 uint32_t power[2];
1095 uint32_t info;
1096 uint16_t seq;
1097 uint16_t len;
1098 uint8_t tlc;
1099 uint8_t ratid;
1100 uint8_t fc[2];
1101 uint16_t status;
1102 uint16_t sequence;
1103 } __packed;
1104
1105 /* Structure for IWN_BEACON_MISSED notification. */
1106 struct iwn_beacon_missed {
1107 uint32_t consecutive;
1108 uint32_t total;
1109 uint32_t expected;
1110 uint32_t received;
1111 } __packed;
1112
1113 /* Structure for IWN_MPDU_RX_DONE notification. */
1114 struct iwn_rx_mpdu {
1115 uint16_t len;
1116 uint16_t reserved;
1117 } __packed;
1118
1119 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1120 struct iwn4965_rx_phystat {
1121 uint16_t antenna;
1122 uint16_t agc;
1123 uint8_t rssi[6];
1124 } __packed;
1125
1126 struct iwn5000_rx_phystat {
1127 uint32_t reserved1;
1128 uint32_t agc;
1129 uint16_t rssi[3];
1130 } __packed;
1131
1132 struct iwn_rx_stat {
1133 uint8_t phy_len;
1134 uint8_t cfg_phy_len;
1135 #define IWN_STAT_MAXLEN 20
1136
1137 uint8_t id;
1138 uint8_t reserved1;
1139 uint64_t tstamp;
1140 uint32_t beacon;
1141 uint16_t flags;
1142 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2)
1143
1144 uint16_t chan;
1145 uint8_t phybuf[32];
1146 uint32_t rate;
1147 uint16_t len;
1148 uint16_t reserve3;
1149 } __packed;
1150
1151 #define IWN_RSSI_TO_DBM 44
1152
1153 /* Structure for IWN_RX_COMPRESSED_BA notification. */
1154 struct iwn_compressed_ba {
1155 uint8_t macaddr[IEEE80211_ADDR_LEN];
1156 uint16_t reserved;
1157 uint8_t id;
1158 uint8_t tid;
1159 uint16_t seq;
1160 uint64_t bitmap;
1161 uint16_t qid;
1162 uint16_t ssn;
1163 } __packed;
1164
1165 /* Structure for IWN_START_SCAN notification. */
1166 struct iwn_start_scan {
1167 uint64_t tstamp;
1168 uint32_t tbeacon;
1169 uint8_t chan;
1170 uint8_t band;
1171 uint16_t reserved;
1172 uint32_t status;
1173 } __packed;
1174
1175 /* Structure for IWN_STOP_SCAN notification. */
1176 struct iwn_stop_scan {
1177 uint8_t nchan;
1178 uint8_t status;
1179 uint8_t reserved;
1180 uint8_t chan;
1181 uint64_t tsf;
1182 } __packed;
1183
1184 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1185 struct iwn_spectrum_notif {
1186 uint8_t id;
1187 uint8_t token;
1188 uint8_t idx;
1189 uint8_t state;
1190 #define IWN_MEASUREMENT_START 0
1191 #define IWN_MEASUREMENT_STOP 1
1192
1193 uint32_t start;
1194 uint8_t band;
1195 uint8_t chan;
1196 uint8_t type;
1197 uint8_t reserved1;
1198 uint32_t cca_ofdm;
1199 uint32_t cca_cck;
1200 uint32_t cca_time;
1201 uint8_t basic;
1202 uint8_t reserved2[3];
1203 uint32_t ofdm[8];
1204 uint32_t cck[8];
1205 uint32_t stop;
1206 uint32_t status;
1207 #define IWN_MEASUREMENT_OK 0
1208 #define IWN_MEASUREMENT_CONCURRENT 1
1209 #define IWN_MEASUREMENT_CSA_CONFLICT 2
1210 #define IWN_MEASUREMENT_TGH_CONFLICT 3
1211 #define IWN_MEASUREMENT_STOPPED 6
1212 #define IWN_MEASUREMENT_TIMEOUT 7
1213 #define IWN_MEASUREMENT_FAILED 8
1214 } __packed;
1215
1216 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1217 struct iwn_rx_phy_stats {
1218 uint32_t ina;
1219 uint32_t fina;
1220 uint32_t bad_plcp;
1221 uint32_t bad_crc32;
1222 uint32_t overrun;
1223 uint32_t eoverrun;
1224 uint32_t good_crc32;
1225 uint32_t fa;
1226 uint32_t bad_fina_sync;
1227 uint32_t sfd_timeout;
1228 uint32_t fina_timeout;
1229 uint32_t no_rts_ack;
1230 uint32_t rxe_limit;
1231 uint32_t ack;
1232 uint32_t cts;
1233 uint32_t ba_resp;
1234 uint32_t dsp_kill;
1235 uint32_t bad_mh;
1236 uint32_t rssi_sum;
1237 uint32_t reserved;
1238 } __packed;
1239
1240 struct iwn_rx_general_stats {
1241 uint32_t bad_cts;
1242 uint32_t bad_ack;
1243 uint32_t not_bss;
1244 uint32_t filtered;
1245 uint32_t bad_chan;
1246 uint32_t beacons;
1247 uint32_t missed_beacons;
1248 uint32_t adc_saturated; /* time in 0.8us */
1249 uint32_t ina_searched; /* time in 0.8us */
1250 uint32_t noise[3];
1251 uint32_t flags;
1252 uint32_t load;
1253 uint32_t fa;
1254 uint32_t rssi[3];
1255 uint32_t energy[3];
1256 } __packed;
1257
1258 struct iwn_rx_ht_phy_stats {
1259 uint32_t bad_plcp;
1260 uint32_t overrun;
1261 uint32_t eoverrun;
1262 uint32_t good_crc32;
1263 uint32_t bad_crc32;
1264 uint32_t bad_mh;
1265 uint32_t good_ampdu_crc32;
1266 uint32_t ampdu;
1267 uint32_t fragment;
1268 uint32_t reserved;
1269 } __packed;
1270
1271 struct iwn_rx_stats {
1272 struct iwn_rx_phy_stats ofdm;
1273 struct iwn_rx_phy_stats cck;
1274 struct iwn_rx_general_stats general;
1275 struct iwn_rx_ht_phy_stats ht;
1276 } __packed;
1277
1278 struct iwn_tx_stats {
1279 uint32_t preamble;
1280 uint32_t rx_detected;
1281 uint32_t bt_defer;
1282 uint32_t bt_kill;
1283 uint32_t short_len;
1284 uint32_t cts_timeout;
1285 uint32_t ack_timeout;
1286 uint32_t exp_ack;
1287 uint32_t ack;
1288 uint32_t msdu;
1289 uint32_t busrt_err1;
1290 uint32_t burst_err2;
1291 uint32_t cts_collision;
1292 uint32_t ack_collision;
1293 uint32_t ba_timeout;
1294 uint32_t ba_resched;
1295 uint32_t query_ampdu;
1296 uint32_t query;
1297 uint32_t query_ampdu_frag;
1298 uint32_t query_mismatch;
1299 uint32_t not_ready;
1300 uint32_t underrun;
1301 uint32_t bt_ht_kill;
1302 uint32_t rx_ba_resp;
1303 uint32_t reserved[2];
1304 } __packed;
1305
1306 struct iwn_general_stats {
1307 uint32_t temp;
1308 uint32_t temp_m;
1309 uint32_t burst_check;
1310 uint32_t burst;
1311 uint32_t reserved1[4];
1312 uint32_t sleep;
1313 uint32_t slot_out;
1314 uint32_t slot_idle;
1315 uint32_t ttl_tstamp;
1316 uint32_t tx_ant_a;
1317 uint32_t tx_ant_b;
1318 uint32_t exec;
1319 uint32_t probe;
1320 uint32_t reserved2[2];
1321 uint32_t rx_enabled;
1322 uint32_t reserved3[3];
1323 } __packed;
1324
1325 struct iwn_stats {
1326 uint32_t flags;
1327 struct iwn_rx_stats rx;
1328 struct iwn_tx_stats tx;
1329 struct iwn_general_stats general;
1330 } __packed;
1331
1332
1333 /* Firmware error dump. */
1334 struct iwn_fw_dump {
1335 uint32_t valid;
1336 uint32_t id;
1337 uint32_t pc;
1338 uint32_t branch_link[2];
1339 uint32_t interrupt_link[2];
1340 uint32_t error_data[2];
1341 uint32_t src_line;
1342 uint32_t tsf;
1343 uint32_t time[2];
1344 } __packed;
1345
1346 /* TLV firmware header. */
1347 struct iwn_fw_tlv_hdr {
1348 uint32_t zero; /* Always 0, to differentiate from legacy. */
1349 uint32_t signature;
1350 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */
1351
1352 uint8_t descr[64];
1353 uint32_t rev;
1354 #define IWN_FW_API(x) (((x) >> 8) & 0xff)
1355
1356 uint32_t build;
1357 uint64_t altmask;
1358 } __packed;
1359
1360 /* TLV header. */
1361 struct iwn_fw_tlv {
1362 uint16_t type;
1363 #define IWN_FW_TLV_MAIN_TEXT 1
1364 #define IWN_FW_TLV_MAIN_DATA 2
1365 #define IWN_FW_TLV_INIT_TEXT 3
1366 #define IWN_FW_TLV_INIT_DATA 4
1367 #define IWN_FW_TLV_BOOT_TEXT 5
1368 #define IWN_FW_TLV_PBREQ_MAXLEN 6
1369 #define IWN_FW_TLV_ENH_SENS 14
1370 #define IWN_FW_TLV_PHY_CALIB 15
1371
1372 uint16_t alt;
1373 uint32_t len;
1374 } __packed;
1375
1376 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1377 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1378 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1379 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1380 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
1381 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1382 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1383
1384 /*
1385 * Offsets into EEPROM.
1386 */
1387 #define IWN_EEPROM_MAC 0x015
1388 #define IWN_EEPROM_SKU_CAP 0x045
1389 #define IWN_EEPROM_RFCFG 0x048
1390 #define IWN4965_EEPROM_DOMAIN 0x060
1391 #define IWN4965_EEPROM_BAND1 0x063
1392 #define IWN5000_EEPROM_REG 0x066
1393 #define IWN5000_EEPROM_CAL 0x067
1394 #define IWN4965_EEPROM_BAND2 0x072
1395 #define IWN4965_EEPROM_BAND3 0x080
1396 #define IWN4965_EEPROM_BAND4 0x08d
1397 #define IWN4965_EEPROM_BAND5 0x099
1398 #define IWN4965_EEPROM_BAND6 0x0a0
1399 #define IWN4965_EEPROM_BAND7 0x0a8
1400 #define IWN4965_EEPROM_MAXPOW 0x0e8
1401 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1402 #define IWN4965_EEPROM_BANDS 0x0ea
1403 /* Indirect offsets. */
1404 #define IWN5000_EEPROM_DOMAIN 0x001
1405 #define IWN5000_EEPROM_BAND1 0x004
1406 #define IWN5000_EEPROM_BAND2 0x013
1407 #define IWN5000_EEPROM_BAND3 0x021
1408 #define IWN5000_EEPROM_BAND4 0x02e
1409 #define IWN5000_EEPROM_BAND5 0x03a
1410 #define IWN5000_EEPROM_BAND6 0x041
1411 #define IWN6000_EEPROM_BAND6 0x040
1412 #define IWN5000_EEPROM_BAND7 0x049
1413 #define IWN6000_EEPROM_ENHINFO 0x054
1414 #define IWN5000_EEPROM_CRYSTAL 0x128
1415 #define IWN5000_EEPROM_TEMP 0x12a
1416 #define IWN5000_EEPROM_VOLT 0x12b
1417
1418 /* Possible flags for IWN_EEPROM_SKU_CAP. */
1419 #define IWN_EEPROM_SKU_CAP_11N (1 << 6)
1420 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7)
1421 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8)
1422
1423 /* Possible flags for IWN_EEPROM_RFCFG. */
1424 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1425 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1426 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1427 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1428 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1429
1430 struct iwn_eeprom_chan {
1431 uint8_t flags;
1432 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1433 #define IWN_EEPROM_CHAN_IBSS (1 << 1)
1434 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1435 #define IWN_EEPROM_CHAN_RADAR (1 << 4)
1436
1437 int8_t maxpwr;
1438 } __packed;
1439
1440 struct iwn_eeprom_enhinfo {
1441 uint8_t flags;
1442 #define IWN_ENHINFO_VALID 0x01
1443 #define IWN_ENHINFO_5GHZ 0x02
1444 #define IWN_ENHINFO_OFDM 0x04
1445 #define IWN_ENHINFO_HT40 0x08
1446 #define IWN_ENHINFO_HTAP 0x10
1447 #define IWN_ENHINFO_RES1 0x20
1448 #define IWN_ENHINFO_RES2 0x40
1449 #define IWN_ENHINFO_COMMON 0x80
1450
1451 uint8_t chan;
1452 int8_t chain[3]; /* max power in half-dBm */
1453 uint8_t reserved;
1454 int8_t mimo2; /* max power in half-dBm */
1455 int8_t mimo3; /* max power in half-dBm */
1456 } __packed;
1457
1458 struct iwn5000_eeprom_calib_hdr {
1459 uint8_t version;
1460 uint8_t pa_type;
1461 uint16_t volt;
1462 } __packed;
1463
1464 #define IWN_NSAMPLES 3
1465 struct iwn4965_eeprom_chan_samples {
1466 uint8_t num;
1467 struct {
1468 uint8_t temp;
1469 uint8_t gain;
1470 uint8_t power;
1471 int8_t pa_det;
1472 } samples[2][IWN_NSAMPLES];
1473 } __packed;
1474
1475 #define IWN_NBANDS 8
1476 struct iwn4965_eeprom_band {
1477 uint8_t lo; /* low channel number */
1478 uint8_t hi; /* high channel number */
1479 struct iwn4965_eeprom_chan_samples chans[2];
1480 } __packed;
1481
1482 /*
1483 * Offsets of channels descriptions in EEPROM.
1484 */
1485 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1486 IWN4965_EEPROM_BAND1,
1487 IWN4965_EEPROM_BAND2,
1488 IWN4965_EEPROM_BAND3,
1489 IWN4965_EEPROM_BAND4,
1490 IWN4965_EEPROM_BAND5,
1491 IWN4965_EEPROM_BAND6,
1492 IWN4965_EEPROM_BAND7
1493 };
1494
1495 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1496 IWN5000_EEPROM_BAND1,
1497 IWN5000_EEPROM_BAND2,
1498 IWN5000_EEPROM_BAND3,
1499 IWN5000_EEPROM_BAND4,
1500 IWN5000_EEPROM_BAND5,
1501 IWN5000_EEPROM_BAND6,
1502 IWN5000_EEPROM_BAND7
1503 };
1504
1505 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = {
1506 IWN5000_EEPROM_BAND1,
1507 IWN5000_EEPROM_BAND2,
1508 IWN5000_EEPROM_BAND3,
1509 IWN5000_EEPROM_BAND4,
1510 IWN5000_EEPROM_BAND5,
1511 IWN6000_EEPROM_BAND6,
1512 IWN5000_EEPROM_BAND7
1513 };
1514
1515 #define IWN_CHAN_BANDS_COUNT 7
1516 #define IWN_MAX_CHAN_PER_BAND 14
1517 static const struct iwn_chan_band {
1518 uint8_t nchan;
1519 uint8_t chan[IWN_MAX_CHAN_PER_BAND];
1520 } iwn_bands[] = {
1521 /* 20MHz channels, 2GHz band. */
1522 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1523 /* 20MHz channels, 5GHz band. */
1524 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1525 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1526 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1527 { 6, { 145, 149, 153, 157, 161, 165 } },
1528 /* 40MHz channels (primary channels), 2GHz band. */
1529 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1530 /* 40MHz channels (primary channels), 5GHz band. */
1531 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1532 };
1533
1534 #define IWN1000_OTP_NBLOCKS 3
1535 #define IWN6000_OTP_NBLOCKS 4
1536 #define IWN6050_OTP_NBLOCKS 7
1537
1538 /* HW rate indices. */
1539 #define IWN_RIDX_CCK1 0
1540 #define IWN_RIDX_OFDM6 4
1541
1542 #define IWN4965_MAX_PWR_INDEX 107
1543
1544 /*
1545 * RF Tx gain values from highest to lowest power (values obtained from
1546 * the reference driver.)
1547 */
1548 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1549 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
1550 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
1551 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
1552 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
1553 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
1554 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
1555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1559 };
1560
1561 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1562 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
1563 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
1564 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
1565 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
1566 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
1567 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
1568 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
1569 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
1570 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
1571 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1572 };
1573
1574 /*
1575 * DSP pre-DAC gain values from highest to lowest power (values obtained
1576 * from the reference driver.)
1577 */
1578 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1579 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1580 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1581 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1582 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1583 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1584 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1585 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
1586 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
1587 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
1588 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
1589 };
1590
1591 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1592 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1593 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1594 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1595 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1596 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1597 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1598 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1599 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1600 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1601 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
1602 };
1603
1604 /*
1605 * Power saving settings (values obtained from the reference driver.)
1606 */
1607 #define IWN_NDTIMRANGES 3
1608 #define IWN_NPOWERLEVELS 6
1609 static const struct iwn_pmgt {
1610 uint32_t rxtimeout;
1611 uint32_t txtimeout;
1612 uint32_t intval[5];
1613 int skip_dtim;
1614 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
1615 /* DTIM <= 2 */
1616 {
1617 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1618 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
1619 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
1620 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
1621 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
1622 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
1623 },
1624 /* 3 <= DTIM <= 10 */
1625 {
1626 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1627 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
1628 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
1629 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
1630 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
1631 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
1632 },
1633 /* DTIM >= 11 */
1634 {
1635 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1636 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
1637 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
1638 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
1639 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
1640 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
1641 }
1642 };
1643
1644 struct iwn_sensitivity_limits {
1645 uint32_t min_ofdm_x1;
1646 uint32_t max_ofdm_x1;
1647 uint32_t min_ofdm_mrc_x1;
1648 uint32_t max_ofdm_mrc_x1;
1649 uint32_t min_ofdm_x4;
1650 uint32_t max_ofdm_x4;
1651 uint32_t min_ofdm_mrc_x4;
1652 uint32_t max_ofdm_mrc_x4;
1653 uint32_t min_cck_x4;
1654 uint32_t max_cck_x4;
1655 uint32_t min_cck_mrc_x4;
1656 uint32_t max_cck_mrc_x4;
1657 uint32_t min_energy_cck;
1658 uint32_t energy_cck;
1659 uint32_t energy_ofdm;
1660 };
1661
1662 /*
1663 * RX sensitivity limits (values obtained from the reference driver.)
1664 */
1665 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1666 105, 140,
1667 220, 270,
1668 85, 120,
1669 170, 210,
1670 125, 200,
1671 200, 400,
1672 97,
1673 100,
1674 100
1675 };
1676
1677 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
1678 120, 120, /* min = max for performance bug in DSP. */
1679 240, 240, /* min = max for performance bug in DSP. */
1680 90, 120,
1681 170, 210,
1682 125, 200,
1683 170, 400,
1684 95,
1685 95,
1686 95
1687 };
1688
1689 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
1690 105, 105, /* min = max for performance bug in DSP. */
1691 220, 220, /* min = max for performance bug in DSP. */
1692 90, 120,
1693 170, 210,
1694 125, 200,
1695 170, 400,
1696 95,
1697 95,
1698 95
1699 };
1700
1701 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
1702 120, 155,
1703 240, 290,
1704 90, 120,
1705 170, 210,
1706 125, 200,
1707 170, 400,
1708 95,
1709 95,
1710 95
1711 };
1712
1713 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
1714 105, 110,
1715 192, 232,
1716 80, 145,
1717 128, 232,
1718 125, 175,
1719 160, 310,
1720 97,
1721 97,
1722 100
1723 };
1724
1725 /* Map TID to TX scheduler's FIFO. */
1726 static const uint8_t iwn_tid2fifo[] = {
1727 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1728 };
1729
1730 /* WiFi/WiMAX coexist event priority table for 6050. */
1731 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
1732 { 0x04, 0x03, 0x00, 0x00 },
1733 { 0x04, 0x03, 0x00, 0x03 },
1734 { 0x04, 0x03, 0x00, 0x03 },
1735 { 0x04, 0x03, 0x00, 0x03 },
1736 { 0x04, 0x03, 0x00, 0x00 },
1737 { 0x04, 0x03, 0x00, 0x07 },
1738 { 0x04, 0x03, 0x00, 0x00 },
1739 { 0x04, 0x03, 0x00, 0x03 },
1740 { 0x04, 0x03, 0x00, 0x03 },
1741 { 0x04, 0x03, 0x00, 0x00 },
1742 { 0x06, 0x03, 0x00, 0x07 },
1743 { 0x04, 0x03, 0x00, 0x00 },
1744 { 0x06, 0x06, 0x00, 0x03 },
1745 { 0x04, 0x03, 0x00, 0x07 },
1746 { 0x04, 0x03, 0x00, 0x00 },
1747 { 0x04, 0x03, 0x00, 0x00 }
1748 };
1749
1750 /* Firmware errors. */
1751 static const char * const iwn_fw_errmsg[] = {
1752 "OK",
1753 "FAIL",
1754 "BAD_PARAM",
1755 "BAD_CHECKSUM",
1756 "NMI_INTERRUPT_WDG",
1757 "SYSASSERT",
1758 "FATAL_ERROR",
1759 "BAD_COMMAND",
1760 "HW_ERROR_TUNE_LOCK",
1761 "HW_ERROR_TEMPERATURE",
1762 "ILLEGAL_CHAN_FREQ",
1763 "VCC_NOT_STABLE",
1764 "FH_ERROR",
1765 "NMI_INTERRUPT_HOST",
1766 "NMI_INTERRUPT_ACTION_PT",
1767 "NMI_INTERRUPT_UNKNOWN",
1768 "UCODE_VERSION_MISMATCH",
1769 "HW_ERROR_ABS_LOCK",
1770 "HW_ERROR_CAL_LOCK_FAIL",
1771 "NMI_INTERRUPT_INST_ACTION_PT",
1772 "NMI_INTERRUPT_DATA_ACTION_PT",
1773 "NMI_TRM_HW_ER",
1774 "NMI_INTERRUPT_TRM",
1775 "NMI_INTERRUPT_BREAKPOINT"
1776 "DEBUG_0",
1777 "DEBUG_1",
1778 "DEBUG_2",
1779 "DEBUG_3",
1780 "ADVANCED_SYSASSERT"
1781 };
1782
1783 /* Find least significant bit that is set. */
1784 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1785
1786 #define IWN_READ(sc, reg) \
1787 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1788
1789 #define IWN_WRITE(sc, reg, val) \
1790 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1791
1792 #define IWN_WRITE_1(sc, reg, val) \
1793 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1794
1795 #define IWN_SETBITS(sc, reg, mask) \
1796 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1797
1798 #define IWN_CLRBITS(sc, reg, mask) \
1799 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
1800
1801 #define IWN_BARRIER_WRITE(sc) \
1802 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1803 BUS_SPACE_BARRIER_WRITE)
1804
1805 #define IWN_BARRIER_READ_WRITE(sc) \
1806 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1807 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
Cache object: 82dbdbc7f9ba5e90e82bc3758efa4f02
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