The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ixgb/if_ixgb.h

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    1 /**************************************************************************
    2 
    3 Copyright (c) 2001-2004, Intel Corporation
    4 All rights reserved.
    5 
    6 Redistribution and use in source and binary forms, with or without
    7 modification, are permitted provided that the following conditions are met:
    8 
    9  1. Redistributions of source code must retain the above copyright notice,
   10     this list of conditions and the following disclaimer.
   11 
   12  2. Redistributions in binary form must reproduce the above copyright
   13     notice, this list of conditions and the following disclaimer in the
   14     documentation and/or other materials provided with the distribution.
   15 
   16  3. Neither the name of the Intel Corporation nor the names of its
   17     contributors may be used to endorse or promote products derived from
   18     this software without specific prior written permission.
   19 
   20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30 POSSIBILITY OF SUCH DAMAGE.
   31 
   32 ***************************************************************************/
   33 /*$FreeBSD: releng/5.4/sys/dev/ixgb/if_ixgb.h 144355 2005-03-30 23:08:46Z mux $*/
   34 
   35 #ifndef _IXGB_H_DEFINED_
   36 #define _IXGB_H_DEFINED_
   37 
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/mbuf.h>
   42 #include <sys/protosw.h>
   43 #include <sys/socket.h>
   44 #include <sys/malloc.h>
   45 #include <sys/module.h>
   46 #include <sys/kernel.h>
   47 #include <sys/sockio.h>
   48 
   49 #include <net/if.h>
   50 #include <net/if_arp.h>
   51 #include <net/ethernet.h>
   52 #include <net/if_dl.h>
   53 #include <net/if_media.h>
   54 
   55 #include <net/bpf.h>
   56 #include <net/if_types.h>
   57 #include <net/if_vlan_var.h>
   58 
   59 #include <netinet/in_systm.h>
   60 #include <netinet/in.h>
   61 #include <netinet/ip.h>
   62 #include <netinet/tcp.h>
   63 #include <netinet/udp.h>
   64 
   65 #include <sys/bus.h>
   66 #include <machine/bus.h>
   67 #include <sys/rman.h>
   68 #include <machine/resource.h>
   69 #include <machine/clock.h>
   70 #if __FreeBSD_version >= 502000
   71 #include <dev/pci/pcivar.h>
   72 #include <dev/pci/pcireg.h>
   73 #else
   74 #include <pci/pcivar.h>
   75 #include <pci/pcireg.h>
   76 #endif
   77 #include <sys/proc.h>
   78 #include <sys/sysctl.h>
   79 #include <sys/endian.h>
   80 #include "opt_bdg.h"
   81 
   82 #include <dev/ixgb/ixgb_hw.h>
   83 #include <dev/ixgb/ixgb_ee.h>
   84 #include <dev/ixgb/ixgb_ids.h>
   85 
   86 /* Tunables */
   87 
   88 /*
   89  * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
   90  * number of transmit descriptors allocated by the driver. Increasing this
   91  * value allows the driver to queue more transmits. Each descriptor is 16
   92  * bytes.
   93  */
   94 #define IXGB_MAX_TXD                      256
   95 
   96 /*
   97  * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the
   98  * number of receive descriptors allocated by the driver. Increasing this
   99  * value allows the driver to buffer more incoming packets. Each descriptor
  100  * is 16 bytes.  A receive buffer is also allocated for each descriptor. The
  101  * maximum MTU size is 16110.
  102  * 
  103  */
  104 #define IXGB_MAX_RXD                     1024
  105 
  106 /*
  107  * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value
  108  * delays the generation of transmit interrupts in units of 1.024
  109  * microseconds. Transmit interrupt reduction can improve CPU efficiency if
  110  * properly tuned for specific network traffic. If the system is reporting
  111  * dropped transmits, this value may be set too high causing the driver to
  112  * run out of available transmit descriptors.
  113  */
  114 #define TIDV 32
  115 
  116 /*
  117  * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value
  118  * delays the generation of receive interrupts in units of 1.024
  119  * microseconds.  Receive interrupt reduction can improve CPU efficiency if
  120  * properly tuned for specific network traffic. Increasing this value adds
  121  * extra latency to frame reception and can end up decreasing the throughput
  122  * of TCP traffic. If the system is reporting dropped receives, this value
  123  * may be set too high, causing the driver to run out of available receive
  124  * descriptors.
  125  * 
  126  */
  127 #define RDTR 72
  128 
  129 
  130 /*
  131  * This parameter controls the maximum no of times the driver will loop in
  132  * the isr. Minimum Value = 1
  133  */
  134 #define IXGB_MAX_INTR                     3
  135 
  136 
  137 /*
  138  * Inform the stack about transmit checksum offload capabilities.
  139  */
  140 #define IXGB_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
  141 
  142 /*
  143  * This parameter controls the duration of transmit watchdog timer.
  144  */
  145 #define IXGB_TX_TIMEOUT                   5     /* set to 5 seconds */
  146 
  147 /*
  148  * This parameter controls when the driver calls the routine to reclaim
  149  * transmit descriptors.
  150  */
  151 #define IXGB_TX_CLEANUP_THRESHOLD         IXGB_MAX_TXD / 8
  152 
  153 /* 
  154  * Flow Control Types. 
  155  * 1. ixgb_fc_none - Flow Control Disabled 
  156  * 2. ixgb_fc_rx_pause - Flow Control Receive Only
  157  * 3. ixgb_fc_tx_pause - Flow Control Transmit Only
  158  * 4. ixgb_fc_full - Flow Control Enabled
  159  */
  160 #define FLOW_CONTROL_NONE       ixgb_fc_none 
  161 #define FLOW_CONTROL_RX_PAUSE   ixgb_fc_rx_pause
  162 #define FLOW_CONTROL_TX_PAUSE   ixgb_fc_tx_pause
  163 #define FLOW_CONTROL_FULL       ixgb_fc_full
  164 
  165 /*
  166  * Set the flow control type. Assign one of the above flow control types to be enabled.
  167  * Default Value: FLOW_CONTROL_FULL   
  168  */    
  169 #define FLOW_CONTROL            FLOW_CONTROL_FULL
  170 
  171 /*
  172  * Receive Flow control low threshold (when we send a resume frame) (FCRTL)
  173  * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be
  174  * less than high threshold by at least 8 bytes Default Value:  163,840
  175  * (0x28000)
  176  */
  177 #define FCRTL                   0x28000
  178 
  179 /*
  180  * Receive Flow control high threshold (when we send a pause frame) (FCRTH)
  181  * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default
  182  * Value: 196,608 (0x30000)
  183  */
  184 #define FCRTH                   0x30000
  185 
  186 /*
  187  * Flow control request timeout (how long to pause the link partner's tx)
  188  * (PAP 15:0) Valid Range: 1 - 65535 Default Value:  256 (0x100)
  189  */
  190 #define FCPAUSE              0x100
  191 
  192 /* Tunables -- End */
  193 
  194 
  195 #define IXGB_VENDOR_ID                    0x8086
  196 #define IXGB_MMBA                         0x0010        /* Mem base address */
  197 #define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
  198 
  199 #define IOCTL_CMD_TYPE                  u_long
  200 #define MAX_NUM_MULTICAST_ADDRESSES     128
  201 #define PCI_ANY_ID                      (~0U)
  202 #define ETHER_ALIGN                     2
  203 
  204 /* Defines for printing debug information */
  205 #define DEBUG_INIT  0
  206 #define DEBUG_IOCTL 0
  207 #define DEBUG_HW    0
  208 #define _SV_        0
  209 
  210 #define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
  211 #define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
  212 #define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
  213 #define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
  214 #define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
  215 #define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
  216 #define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
  217 #define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
  218 #define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
  219 
  220 
  221 /* Supported RX Buffer Sizes */
  222 #define IXGB_RXBUFFER_2048        2048
  223 #define IXGB_RXBUFFER_4096        4096
  224 #define IXGB_RXBUFFER_8192        8192
  225 #define IXGB_RXBUFFER_16384      16384
  226 
  227 #define IXGB_MAX_SCATTER           100
  228 
  229 /*
  230  * ******************************************************************************
  231  * vendor_info_array
  232  * 
  233  * This array contains the list of Subvendor/Subdevice IDs on which the driver
  234  * should load.
  235  * 
  236 *****************************************************************************
  237  */
  238 typedef struct _ixgb_vendor_info_t {
  239         unsigned int    vendor_id;
  240         unsigned int    device_id;
  241         unsigned int    subvendor_id;
  242         unsigned int    subdevice_id;
  243         unsigned int    index;
  244 }               ixgb_vendor_info_t;
  245 
  246 
  247 struct ixgb_buffer {
  248         struct mbuf    *m_head;
  249         bus_dmamap_t    map;    /* bus_dma map for packet */
  250 };
  251 
  252 struct ixgb_q {
  253         bus_dmamap_t    map;    /* bus_dma map for packet */
  254         int             nsegs;  /* # of segments/descriptors */
  255         bus_dma_segment_t segs[IXGB_MAX_SCATTER];
  256 };
  257 
  258 /*
  259  * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free.
  260  */
  261 struct ixgb_dma_alloc {
  262         bus_addr_t      dma_paddr;
  263         caddr_t         dma_vaddr;
  264         bus_dma_tag_t   dma_tag;
  265         bus_dmamap_t    dma_map;
  266         bus_dma_segment_t dma_seg;
  267         bus_size_t      dma_size;
  268         int             dma_nseg;
  269 };
  270 
  271 typedef enum _XSUM_CONTEXT_T {
  272         OFFLOAD_NONE,
  273         OFFLOAD_TCP_IP,
  274         OFFLOAD_UDP_IP
  275 }               XSUM_CONTEXT_T;
  276 
  277 /* Our adapter structure */
  278 struct adapter {
  279         struct arpcom   interface_data;
  280         struct adapter *next;
  281         struct adapter *prev;
  282         struct ixgb_hw  hw;
  283 
  284         /* FreeBSD operating-system-specific structures */
  285         struct ixgb_osdep osdep;
  286         struct device  *dev;
  287         struct resource *res_memory;
  288         struct resource *res_ioport;
  289         struct resource *res_interrupt;
  290         void           *int_handler_tag;
  291         struct ifmedia  media;
  292         struct callout_handle timer_handle;
  293         int             io_rid;
  294         u_int8_t        unit;
  295 
  296         /* Info about the board itself */
  297         u_int32_t       part_num;
  298         u_int8_t        link_active;
  299         u_int16_t       link_speed;
  300         u_int16_t       link_duplex;
  301         u_int32_t       tx_int_delay;
  302         u_int32_t       tx_abs_int_delay;
  303         u_int32_t       rx_int_delay;
  304         u_int32_t       rx_abs_int_delay;
  305 
  306         int             raidc;
  307 
  308         XSUM_CONTEXT_T  active_checksum_context;
  309 
  310         /*
  311          * Transmit definitions
  312          * 
  313          * We have an array of num_tx_desc descriptors (handled by the
  314          * controller) paired with an array of tx_buffers (at
  315          * tx_buffer_area). The index of the next available descriptor is
  316          * next_avail_tx_desc. The number of remaining tx_desc is
  317          * num_tx_desc_avail.
  318          */
  319         struct ixgb_dma_alloc txdma;    /* bus_dma glue for tx desc */
  320         struct ixgb_tx_desc *tx_desc_base;
  321         u_int32_t       next_avail_tx_desc;
  322         u_int32_t       oldest_used_tx_desc;
  323                         volatile u_int16_t num_tx_desc_avail;
  324         u_int16_t       num_tx_desc;
  325         u_int32_t       txd_cmd;
  326         struct ixgb_buffer *tx_buffer_area;
  327         bus_dma_tag_t   txtag;  /* dma tag for tx */
  328 
  329         /*
  330          * Receive definitions
  331          * 
  332          * we have an array of num_rx_desc rx_desc (handled by the controller),
  333          * and paired with an array of rx_buffers (at rx_buffer_area). The
  334          * next pair to check on receive is at offset next_rx_desc_to_check
  335          */
  336         struct ixgb_dma_alloc rxdma;    /* bus_dma glue for rx desc */
  337         struct ixgb_rx_desc *rx_desc_base;
  338         u_int32_t       next_rx_desc_to_check;
  339         u_int16_t       num_rx_desc;
  340         u_int32_t       rx_buffer_len;
  341         struct ixgb_buffer *rx_buffer_area;
  342         bus_dma_tag_t   rxtag;  /* dma tag for Rx */
  343         u_int32_t       next_rx_desc_to_use;
  344 
  345 
  346         /* Jumbo frame */
  347         struct mbuf    *fmp;
  348         struct mbuf    *lmp;
  349 
  350         struct sysctl_ctx_list sysctl_ctx;
  351         struct sysctl_oid *sysctl_tree;
  352 
  353         /* Misc stats maintained by the driver */
  354         unsigned long   dropped_pkts;
  355         unsigned long   mbuf_alloc_failed;
  356         unsigned long   mbuf_cluster_failed;
  357         unsigned long   no_tx_desc_avail1;
  358         unsigned long   no_tx_desc_avail2;
  359         unsigned long   no_tx_map_avail;
  360         unsigned long   no_tx_dma_setup;
  361 
  362         boolean_t       in_detach;
  363 
  364         /* Board specific private data */
  365 #ifdef _SV_
  366         struct ixgb_sv_stats {
  367                 uint64_t        icr_rxdmt0;
  368                 uint64_t        icr_rxo;
  369                 uint64_t        icr_rxt0;
  370                 uint64_t        icr_TXDW;
  371         }               sv_stats;
  372         unsigned long   no_pkts_avail;
  373         unsigned long   clean_tx_interrupts;
  374 #endif
  375 
  376         struct ixgb_hw_stats stats;
  377 };
  378 
  379 #endif                          /* _IXGB_H_DEFINED_ */

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