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sys/dev/ixgbe/ixgbe_82599.c
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1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_82599.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #define IXGBE_82599_MAX_TX_QUEUES 128 43 #define IXGBE_82599_MAX_RX_QUEUES 128 44 #define IXGBE_82599_RAR_ENTRIES 128 45 #define IXGBE_82599_MC_TBL_SIZE 128 46 #define IXGBE_82599_VFT_TBL_SIZE 128 47 #define IXGBE_82599_RX_PB_SIZE 512 48 49 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, 51 bool autoneg_wait_to_complete); 52 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 53 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 54 u16 offset, u16 *data); 55 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 56 u16 words, u16 *data); 57 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 58 u8 dev_addr, u8 *data); 59 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 60 u8 dev_addr, u8 data); 61 62 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 63 { 64 struct ixgbe_mac_info *mac = &hw->mac; 65 66 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 67 68 /* 69 * enable the laser control functions for SFP+ fiber 70 * and MNG not enabled 71 */ 72 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 73 !ixgbe_mng_enabled(hw)) { 74 mac->ops.disable_tx_laser = 75 ixgbe_disable_tx_laser_multispeed_fiber; 76 mac->ops.enable_tx_laser = 77 ixgbe_enable_tx_laser_multispeed_fiber; 78 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 79 80 } else { 81 mac->ops.disable_tx_laser = NULL; 82 mac->ops.enable_tx_laser = NULL; 83 mac->ops.flap_tx_laser = NULL; 84 } 85 86 if (hw->phy.multispeed_fiber) { 87 /* Set up dual speed SFP+ support */ 88 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 89 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 90 mac->ops.set_rate_select_speed = 91 ixgbe_set_hard_rate_select_speed; 92 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) 93 mac->ops.set_rate_select_speed = 94 ixgbe_set_soft_rate_select_speed; 95 } else { 96 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 97 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 98 hw->phy.smart_speed == ixgbe_smart_speed_on) && 99 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 100 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 101 } else { 102 mac->ops.setup_link = ixgbe_setup_mac_link_82599; 103 } 104 } 105 } 106 107 /** 108 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 109 * @hw: pointer to hardware structure 110 * 111 * Initialize any function pointers that were not able to be 112 * set during init_shared_code because the PHY/SFP type was 113 * not known. Perform the SFP init if necessary. 114 * 115 **/ 116 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 117 { 118 struct ixgbe_mac_info *mac = &hw->mac; 119 struct ixgbe_phy_info *phy = &hw->phy; 120 s32 ret_val = IXGBE_SUCCESS; 121 u32 esdp; 122 123 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 124 125 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 126 /* Store flag indicating I2C bus access control unit. */ 127 hw->phy.qsfp_shared_i2c_bus = true; 128 129 /* Initialize access to QSFP+ I2C bus */ 130 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 131 esdp |= IXGBE_ESDP_SDP0_DIR; 132 esdp &= ~IXGBE_ESDP_SDP1_DIR; 133 esdp &= ~IXGBE_ESDP_SDP0; 134 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 135 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 136 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 137 IXGBE_WRITE_FLUSH(hw); 138 139 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 140 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 141 } 142 /* Identify the PHY or SFP module */ 143 ret_val = phy->ops.identify(hw); 144 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 145 goto init_phy_ops_out; 146 147 /* Setup function pointers based on detected SFP module and speeds */ 148 ixgbe_init_mac_link_ops_82599(hw); 149 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 150 hw->phy.ops.reset = NULL; 151 152 /* If copper media, overwrite with copper function pointers */ 153 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 154 mac->ops.setup_link = ixgbe_setup_copper_link_82599; 155 mac->ops.get_link_capabilities = 156 ixgbe_get_copper_link_capabilities_generic; 157 } 158 159 /* Set necessary function pointers based on PHY type */ 160 switch (hw->phy.type) { 161 case ixgbe_phy_tn: 162 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 163 phy->ops.check_link = ixgbe_check_phy_link_tnx; 164 phy->ops.get_firmware_version = 165 ixgbe_get_phy_firmware_version_tnx; 166 break; 167 default: 168 break; 169 } 170 init_phy_ops_out: 171 return ret_val; 172 } 173 174 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 175 { 176 s32 ret_val = IXGBE_SUCCESS; 177 u16 list_offset, data_offset, data_value; 178 179 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 180 181 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 182 ixgbe_init_mac_link_ops_82599(hw); 183 184 hw->phy.ops.reset = NULL; 185 186 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 187 &data_offset); 188 if (ret_val != IXGBE_SUCCESS) 189 goto setup_sfp_out; 190 191 /* PHY config will finish before releasing the semaphore */ 192 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 193 IXGBE_GSSR_MAC_CSR_SM); 194 if (ret_val != IXGBE_SUCCESS) { 195 ret_val = IXGBE_ERR_SWFW_SYNC; 196 goto setup_sfp_out; 197 } 198 199 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 200 goto setup_sfp_err; 201 while (data_value != 0xffff) { 202 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 203 IXGBE_WRITE_FLUSH(hw); 204 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 205 goto setup_sfp_err; 206 } 207 208 /* Release the semaphore */ 209 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 210 /* Delay obtaining semaphore again to allow FW access 211 * prot_autoc_write uses the semaphore too. 212 */ 213 msec_delay(hw->eeprom.semaphore_delay); 214 215 /* Restart DSP and set SFI mode */ 216 ret_val = hw->mac.ops.prot_autoc_write(hw, 217 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 218 false); 219 220 if (ret_val) { 221 DEBUGOUT("sfp module setup not complete\n"); 222 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 223 goto setup_sfp_out; 224 } 225 226 } 227 228 setup_sfp_out: 229 return ret_val; 230 231 setup_sfp_err: 232 /* Release the semaphore */ 233 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 234 /* Delay obtaining semaphore again to allow FW access */ 235 msec_delay(hw->eeprom.semaphore_delay); 236 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 237 "eeprom read at offset %d failed", data_offset); 238 return IXGBE_ERR_PHY; 239 } 240 241 /** 242 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 243 * @hw: pointer to hardware structure 244 * @locked: Return the if we locked for this read. 245 * @reg_val: Value we read from AUTOC 246 * 247 * For this part (82599) we need to wrap read-modify-writes with a possible 248 * FW/SW lock. It is assumed this lock will be freed with the next 249 * prot_autoc_write_82599(). 250 */ 251 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 252 { 253 s32 ret_val; 254 255 *locked = false; 256 /* If LESM is on then we need to hold the SW/FW semaphore. */ 257 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 258 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 259 IXGBE_GSSR_MAC_CSR_SM); 260 if (ret_val != IXGBE_SUCCESS) 261 return IXGBE_ERR_SWFW_SYNC; 262 263 *locked = true; 264 } 265 266 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 267 return IXGBE_SUCCESS; 268 } 269 270 /** 271 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 272 * @hw: pointer to hardware structure 273 * @autoc: value to write to AUTOC 274 * @locked: bool to indicate whether the SW/FW lock was already taken by 275 * previous proc_autoc_read_82599. 276 * 277 * This part (82599) may need to hold the SW/FW lock around all writes to 278 * AUTOC. Likewise after a write we need to do a pipeline reset. 279 */ 280 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 281 { 282 s32 ret_val = IXGBE_SUCCESS; 283 284 /* Blocked by MNG FW so bail */ 285 if (ixgbe_check_reset_blocked(hw)) 286 goto out; 287 288 /* We only need to get the lock if: 289 * - We didn't do it already (in the read part of a read-modify-write) 290 * - LESM is enabled. 291 */ 292 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 293 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 294 IXGBE_GSSR_MAC_CSR_SM); 295 if (ret_val != IXGBE_SUCCESS) 296 return IXGBE_ERR_SWFW_SYNC; 297 298 locked = true; 299 } 300 301 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 302 ret_val = ixgbe_reset_pipeline_82599(hw); 303 304 out: 305 /* Free the SW/FW semaphore as we either grabbed it here or 306 * already had it when this function was called. 307 */ 308 if (locked) 309 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 310 311 return ret_val; 312 } 313 314 /** 315 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 316 * @hw: pointer to hardware structure 317 * 318 * Initialize the function pointers and assign the MAC type for 82599. 319 * Does not touch the hardware. 320 **/ 321 322 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 323 { 324 struct ixgbe_mac_info *mac = &hw->mac; 325 struct ixgbe_phy_info *phy = &hw->phy; 326 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 327 s32 ret_val; 328 329 DEBUGFUNC("ixgbe_init_ops_82599"); 330 331 ixgbe_init_phy_ops_generic(hw); 332 ret_val = ixgbe_init_ops_generic(hw); 333 334 /* PHY */ 335 phy->ops.identify = ixgbe_identify_phy_82599; 336 phy->ops.init = ixgbe_init_phy_ops_82599; 337 338 /* MAC */ 339 mac->ops.reset_hw = ixgbe_reset_hw_82599; 340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 341 mac->ops.get_media_type = ixgbe_get_media_type_82599; 342 mac->ops.get_supported_physical_layer = 343 ixgbe_get_supported_physical_layer_82599; 344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 349 mac->ops.start_hw = ixgbe_start_hw_82599; 350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 355 mac->ops.prot_autoc_read = prot_autoc_read_82599; 356 mac->ops.prot_autoc_write = prot_autoc_write_82599; 357 358 /* RAR, Multicast, VLAN */ 359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 363 mac->rar_highwater = 1; 364 mac->ops.set_vfta = ixgbe_set_vfta_generic; 365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 371 372 /* Link */ 373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 374 mac->ops.check_link = ixgbe_check_mac_link_generic; 375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 376 ixgbe_init_mac_link_ops_82599(hw); 377 378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 385 386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 387 & IXGBE_FWSM_MODE_MASK); 388 389 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 390 391 /* EEPROM */ 392 eeprom->ops.read = ixgbe_read_eeprom_82599; 393 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; 394 395 /* Manageability interface */ 396 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 397 398 mac->ops.get_thermal_sensor_data = 399 ixgbe_get_thermal_sensor_data_generic; 400 mac->ops.init_thermal_sensor_thresh = 401 ixgbe_init_thermal_sensor_thresh_generic; 402 403 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 404 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 405 mac->ops.bypass_set = ixgbe_bypass_set_generic; 406 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 407 408 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 409 410 return ret_val; 411 } 412 413 /** 414 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 415 * @hw: pointer to hardware structure 416 * @speed: pointer to link speed 417 * @autoneg: true when autoneg or autotry is enabled 418 * 419 * Determines the link capabilities by reading the AUTOC register. 420 **/ 421 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 422 ixgbe_link_speed *speed, 423 bool *autoneg) 424 { 425 s32 status = IXGBE_SUCCESS; 426 u32 autoc = 0; 427 428 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 429 430 431 /* Check if 1G SFP module. */ 432 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 433 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 434 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 436 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 438 *speed = IXGBE_LINK_SPEED_1GB_FULL; 439 *autoneg = true; 440 goto out; 441 } 442 443 /* 444 * Determine link capabilities based on the stored value of AUTOC, 445 * which represents EEPROM defaults. If AUTOC value has not 446 * been stored, use the current register values. 447 */ 448 if (hw->mac.orig_link_settings_stored) 449 autoc = hw->mac.orig_autoc; 450 else 451 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 452 453 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 454 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 455 *speed = IXGBE_LINK_SPEED_1GB_FULL; 456 *autoneg = false; 457 break; 458 459 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 460 *speed = IXGBE_LINK_SPEED_10GB_FULL; 461 *autoneg = false; 462 break; 463 464 case IXGBE_AUTOC_LMS_1G_AN: 465 *speed = IXGBE_LINK_SPEED_1GB_FULL; 466 *autoneg = true; 467 break; 468 469 case IXGBE_AUTOC_LMS_10G_SERIAL: 470 *speed = IXGBE_LINK_SPEED_10GB_FULL; 471 *autoneg = false; 472 break; 473 474 case IXGBE_AUTOC_LMS_KX4_KX_KR: 475 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 476 *speed = IXGBE_LINK_SPEED_UNKNOWN; 477 if (autoc & IXGBE_AUTOC_KR_SUPP) 478 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 479 if (autoc & IXGBE_AUTOC_KX4_SUPP) 480 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 481 if (autoc & IXGBE_AUTOC_KX_SUPP) 482 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 483 *autoneg = true; 484 break; 485 486 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 487 *speed = IXGBE_LINK_SPEED_100_FULL; 488 if (autoc & IXGBE_AUTOC_KR_SUPP) 489 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 490 if (autoc & IXGBE_AUTOC_KX4_SUPP) 491 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 492 if (autoc & IXGBE_AUTOC_KX_SUPP) 493 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 494 *autoneg = true; 495 break; 496 497 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 498 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 499 *autoneg = false; 500 break; 501 502 default: 503 status = IXGBE_ERR_LINK_SETUP; 504 goto out; 505 break; 506 } 507 508 if (hw->phy.multispeed_fiber) { 509 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 510 IXGBE_LINK_SPEED_1GB_FULL; 511 512 /* QSFP must not enable full auto-negotiation 513 * Limited autoneg is enabled at 1G 514 */ 515 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 516 *autoneg = false; 517 else 518 *autoneg = true; 519 } 520 521 out: 522 return status; 523 } 524 525 /** 526 * ixgbe_get_media_type_82599 - Get media type 527 * @hw: pointer to hardware structure 528 * 529 * Returns the media type (fiber, copper, backplane) 530 **/ 531 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 532 { 533 enum ixgbe_media_type media_type; 534 535 DEBUGFUNC("ixgbe_get_media_type_82599"); 536 537 /* Detect if there is a copper PHY attached. */ 538 switch (hw->phy.type) { 539 case ixgbe_phy_cu_unknown: 540 case ixgbe_phy_tn: 541 media_type = ixgbe_media_type_copper; 542 goto out; 543 default: 544 break; 545 } 546 547 switch (hw->device_id) { 548 case IXGBE_DEV_ID_82599_KX4: 549 case IXGBE_DEV_ID_82599_KX4_MEZZ: 550 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 551 case IXGBE_DEV_ID_82599_KR: 552 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 553 case IXGBE_DEV_ID_82599_XAUI_LOM: 554 /* Default device ID is mezzanine card KX/KX4 */ 555 media_type = ixgbe_media_type_backplane; 556 break; 557 case IXGBE_DEV_ID_82599_SFP: 558 case IXGBE_DEV_ID_82599_SFP_FCOE: 559 case IXGBE_DEV_ID_82599_SFP_EM: 560 case IXGBE_DEV_ID_82599_SFP_SF2: 561 case IXGBE_DEV_ID_82599_SFP_SF_QP: 562 case IXGBE_DEV_ID_82599EN_SFP: 563 media_type = ixgbe_media_type_fiber; 564 break; 565 case IXGBE_DEV_ID_82599_CX4: 566 media_type = ixgbe_media_type_cx4; 567 break; 568 case IXGBE_DEV_ID_82599_T3_LOM: 569 media_type = ixgbe_media_type_copper; 570 break; 571 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 572 media_type = ixgbe_media_type_fiber_qsfp; 573 break; 574 case IXGBE_DEV_ID_82599_BYPASS: 575 media_type = ixgbe_media_type_fiber_fixed; 576 hw->phy.multispeed_fiber = true; 577 break; 578 default: 579 media_type = ixgbe_media_type_unknown; 580 break; 581 } 582 out: 583 return media_type; 584 } 585 586 /** 587 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 588 * @hw: pointer to hardware structure 589 * 590 * Disables link during D3 power down sequence. 591 * 592 **/ 593 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 594 { 595 u32 autoc2_reg; 596 u16 ee_ctrl_2 = 0; 597 598 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 599 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 600 601 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 602 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 603 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 604 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 605 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 606 } 607 } 608 609 /** 610 * ixgbe_start_mac_link_82599 - Setup MAC link settings 611 * @hw: pointer to hardware structure 612 * @autoneg_wait_to_complete: true when waiting for completion is needed 613 * 614 * Configures link settings based on values in the ixgbe_hw struct. 615 * Restarts the link. Performs autonegotiation if needed. 616 **/ 617 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 618 bool autoneg_wait_to_complete) 619 { 620 u32 autoc_reg; 621 u32 links_reg; 622 u32 i; 623 s32 status = IXGBE_SUCCESS; 624 bool got_lock = false; 625 626 DEBUGFUNC("ixgbe_start_mac_link_82599"); 627 628 629 /* reset_pipeline requires us to hold this lock as it writes to 630 * AUTOC. 631 */ 632 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 633 status = hw->mac.ops.acquire_swfw_sync(hw, 634 IXGBE_GSSR_MAC_CSR_SM); 635 if (status != IXGBE_SUCCESS) 636 goto out; 637 638 got_lock = true; 639 } 640 641 /* Restart link */ 642 ixgbe_reset_pipeline_82599(hw); 643 644 if (got_lock) 645 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 646 647 /* Only poll for autoneg to complete if specified to do so */ 648 if (autoneg_wait_to_complete) { 649 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 650 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 651 IXGBE_AUTOC_LMS_KX4_KX_KR || 652 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 653 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 654 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 655 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 656 links_reg = 0; /* Just in case Autoneg time = 0 */ 657 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 658 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 659 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 660 break; 661 msec_delay(100); 662 } 663 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 664 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 665 DEBUGOUT("Autoneg did not complete.\n"); 666 } 667 } 668 } 669 670 /* Add delay to filter out noises during initial link setup */ 671 msec_delay(50); 672 673 out: 674 return status; 675 } 676 677 /** 678 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 679 * @hw: pointer to hardware structure 680 * 681 * The base drivers may require better control over SFP+ module 682 * PHY states. This includes selectively shutting down the Tx 683 * laser on the PHY, effectively halting physical link. 684 **/ 685 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 686 { 687 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 688 689 /* Blocked by MNG FW so bail */ 690 if (ixgbe_check_reset_blocked(hw)) 691 return; 692 693 /* Disable Tx laser; allow 100us to go dark per spec */ 694 esdp_reg |= IXGBE_ESDP_SDP3; 695 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 696 IXGBE_WRITE_FLUSH(hw); 697 usec_delay(100); 698 } 699 700 /** 701 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 702 * @hw: pointer to hardware structure 703 * 704 * The base drivers may require better control over SFP+ module 705 * PHY states. This includes selectively turning on the Tx 706 * laser on the PHY, effectively starting physical link. 707 **/ 708 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 709 { 710 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 711 712 /* Enable Tx laser; allow 100ms to light up */ 713 esdp_reg &= ~IXGBE_ESDP_SDP3; 714 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 715 IXGBE_WRITE_FLUSH(hw); 716 msec_delay(100); 717 } 718 719 /** 720 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 721 * @hw: pointer to hardware structure 722 * 723 * When the driver changes the link speeds that it can support, 724 * it sets autotry_restart to true to indicate that we need to 725 * initiate a new autotry session with the link partner. To do 726 * so, we set the speed then disable and re-enable the Tx laser, to 727 * alert the link partner that it also needs to restart autotry on its 728 * end. This is consistent with true clause 37 autoneg, which also 729 * involves a loss of signal. 730 **/ 731 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 732 { 733 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 734 735 /* Blocked by MNG FW so bail */ 736 if (ixgbe_check_reset_blocked(hw)) 737 return; 738 739 if (hw->mac.autotry_restart) { 740 ixgbe_disable_tx_laser_multispeed_fiber(hw); 741 ixgbe_enable_tx_laser_multispeed_fiber(hw); 742 hw->mac.autotry_restart = false; 743 } 744 } 745 746 /** 747 * ixgbe_set_hard_rate_select_speed - Set module link speed 748 * @hw: pointer to hardware structure 749 * @speed: link speed to set 750 * 751 * Set module link speed via RS0/RS1 rate select pins. 752 */ 753 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 754 ixgbe_link_speed speed) 755 { 756 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 757 758 switch (speed) { 759 case IXGBE_LINK_SPEED_10GB_FULL: 760 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 761 break; 762 case IXGBE_LINK_SPEED_1GB_FULL: 763 esdp_reg &= ~IXGBE_ESDP_SDP5; 764 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 765 break; 766 default: 767 DEBUGOUT("Invalid fixed module speed\n"); 768 return; 769 } 770 771 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 772 IXGBE_WRITE_FLUSH(hw); 773 } 774 775 /** 776 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 777 * @hw: pointer to hardware structure 778 * @speed: new link speed 779 * @autoneg_wait_to_complete: true when waiting for completion is needed 780 * 781 * Implements the Intel SmartSpeed algorithm. 782 **/ 783 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 784 ixgbe_link_speed speed, 785 bool autoneg_wait_to_complete) 786 { 787 s32 status = IXGBE_SUCCESS; 788 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 789 s32 i, j; 790 bool link_up = false; 791 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 792 793 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 794 795 /* Set autoneg_advertised value based on input link speed */ 796 hw->phy.autoneg_advertised = 0; 797 798 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 799 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 800 801 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 802 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 803 804 if (speed & IXGBE_LINK_SPEED_100_FULL) 805 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 806 807 /* 808 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 809 * autoneg advertisement if link is unable to be established at the 810 * highest negotiated rate. This can sometimes happen due to integrity 811 * issues with the physical media connection. 812 */ 813 814 /* First, try to get link with full advertisement */ 815 hw->phy.smart_speed_active = false; 816 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 817 status = ixgbe_setup_mac_link_82599(hw, speed, 818 autoneg_wait_to_complete); 819 if (status != IXGBE_SUCCESS) 820 goto out; 821 822 /* 823 * Wait for the controller to acquire link. Per IEEE 802.3ap, 824 * Section 73.10.2, we may have to wait up to 500ms if KR is 825 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 826 * Table 9 in the AN MAS. 827 */ 828 for (i = 0; i < 5; i++) { 829 msec_delay(100); 830 831 /* If we have link, just jump out */ 832 status = ixgbe_check_link(hw, &link_speed, &link_up, 833 false); 834 if (status != IXGBE_SUCCESS) 835 goto out; 836 837 if (link_up) 838 goto out; 839 } 840 } 841 842 /* 843 * We didn't get link. If we advertised KR plus one of KX4/KX 844 * (or BX4/BX), then disable KR and try again. 845 */ 846 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 847 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 848 goto out; 849 850 /* Turn SmartSpeed on to disable KR support */ 851 hw->phy.smart_speed_active = true; 852 status = ixgbe_setup_mac_link_82599(hw, speed, 853 autoneg_wait_to_complete); 854 if (status != IXGBE_SUCCESS) 855 goto out; 856 857 /* 858 * Wait for the controller to acquire link. 600ms will allow for 859 * the AN link_fail_inhibit_timer as well for multiple cycles of 860 * parallel detect, both 10g and 1g. This allows for the maximum 861 * connect attempts as defined in the AN MAS table 73-7. 862 */ 863 for (i = 0; i < 6; i++) { 864 msec_delay(100); 865 866 /* If we have link, just jump out */ 867 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 868 if (status != IXGBE_SUCCESS) 869 goto out; 870 871 if (link_up) 872 goto out; 873 } 874 875 /* We didn't get link. Turn SmartSpeed back off. */ 876 hw->phy.smart_speed_active = false; 877 status = ixgbe_setup_mac_link_82599(hw, speed, 878 autoneg_wait_to_complete); 879 880 out: 881 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 882 DEBUGOUT("Smartspeed has downgraded the link speed " 883 "from the maximum advertised\n"); 884 return status; 885 } 886 887 /** 888 * ixgbe_setup_mac_link_82599 - Set MAC link speed 889 * @hw: pointer to hardware structure 890 * @speed: new link speed 891 * @autoneg_wait_to_complete: true when waiting for completion is needed 892 * 893 * Set the link speed in the AUTOC register and restarts link. 894 **/ 895 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 896 ixgbe_link_speed speed, 897 bool autoneg_wait_to_complete) 898 { 899 bool autoneg = false; 900 s32 status = IXGBE_SUCCESS; 901 u32 pma_pmd_1g, link_mode; 902 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ 903 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ 904 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ 905 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 906 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 907 u32 links_reg; 908 u32 i; 909 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 910 911 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 912 913 /* Check to see if speed passed in is supported. */ 914 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 915 if (status) 916 goto out; 917 918 speed &= link_capabilities; 919 920 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 921 status = IXGBE_ERR_LINK_SETUP; 922 goto out; 923 } 924 925 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 926 if (hw->mac.orig_link_settings_stored) 927 orig_autoc = hw->mac.orig_autoc; 928 else 929 orig_autoc = autoc; 930 931 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 932 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 933 934 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 935 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 936 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 937 /* Set KX4/KX/KR support according to speed requested */ 938 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 939 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 940 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 941 autoc |= IXGBE_AUTOC_KX4_SUPP; 942 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 943 (hw->phy.smart_speed_active == false)) 944 autoc |= IXGBE_AUTOC_KR_SUPP; 945 } 946 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 947 autoc |= IXGBE_AUTOC_KX_SUPP; 948 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 949 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 950 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 951 /* Switch from 1G SFI to 10G SFI if requested */ 952 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 953 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 954 autoc &= ~IXGBE_AUTOC_LMS_MASK; 955 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 956 } 957 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 958 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 959 /* Switch from 10G SFI to 1G SFI if requested */ 960 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 961 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 962 autoc &= ~IXGBE_AUTOC_LMS_MASK; 963 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 964 autoc |= IXGBE_AUTOC_LMS_1G_AN; 965 else 966 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 967 } 968 } 969 970 if (autoc != current_autoc) { 971 /* Restart link */ 972 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 973 if (status != IXGBE_SUCCESS) 974 goto out; 975 976 /* Only poll for autoneg to complete if specified to do so */ 977 if (autoneg_wait_to_complete) { 978 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 979 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 980 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 981 links_reg = 0; /*Just in case Autoneg time=0*/ 982 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 983 links_reg = 984 IXGBE_READ_REG(hw, IXGBE_LINKS); 985 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 986 break; 987 msec_delay(100); 988 } 989 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 990 status = 991 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 992 DEBUGOUT("Autoneg did not complete.\n"); 993 } 994 } 995 } 996 997 /* Add delay to filter out noises during initial link setup */ 998 msec_delay(50); 999 } 1000 1001 out: 1002 return status; 1003 } 1004 1005 /** 1006 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1007 * @hw: pointer to hardware structure 1008 * @speed: new link speed 1009 * @autoneg_wait_to_complete: true if waiting is needed to complete 1010 * 1011 * Restarts link on PHY and MAC based on settings passed in. 1012 **/ 1013 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1014 ixgbe_link_speed speed, 1015 bool autoneg_wait_to_complete) 1016 { 1017 s32 status; 1018 1019 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1020 1021 /* Setup the PHY according to input speed */ 1022 status = hw->phy.ops.setup_link_speed(hw, speed, 1023 autoneg_wait_to_complete); 1024 /* Set up MAC */ 1025 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1026 1027 return status; 1028 } 1029 1030 /** 1031 * ixgbe_reset_hw_82599 - Perform hardware reset 1032 * @hw: pointer to hardware structure 1033 * 1034 * Resets the hardware by resetting the transmit and receive units, masks 1035 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1036 * reset. 1037 **/ 1038 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1039 { 1040 ixgbe_link_speed link_speed; 1041 s32 status; 1042 u32 ctrl = 0; 1043 u32 i, autoc, autoc2; 1044 u32 curr_lms; 1045 bool link_up = false; 1046 1047 DEBUGFUNC("ixgbe_reset_hw_82599"); 1048 1049 /* Call adapter stop to disable tx/rx and clear interrupts */ 1050 status = hw->mac.ops.stop_adapter(hw); 1051 if (status != IXGBE_SUCCESS) 1052 goto reset_hw_out; 1053 1054 /* flush pending Tx transactions */ 1055 ixgbe_clear_tx_pending(hw); 1056 1057 /* PHY ops must be identified and initialized prior to reset */ 1058 1059 /* Identify PHY and related function pointers */ 1060 status = hw->phy.ops.init(hw); 1061 1062 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1063 goto reset_hw_out; 1064 1065 /* Setup SFP module if there is one present. */ 1066 if (hw->phy.sfp_setup_needed) { 1067 status = hw->mac.ops.setup_sfp(hw); 1068 hw->phy.sfp_setup_needed = false; 1069 } 1070 1071 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1072 goto reset_hw_out; 1073 1074 /* Reset PHY */ 1075 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 1076 hw->phy.ops.reset(hw); 1077 1078 /* remember AUTOC from before we reset */ 1079 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1080 1081 mac_reset_top: 1082 /* 1083 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1084 * If link reset is used when link is up, it might reset the PHY when 1085 * mng is using it. If link is down or the flag to force full link 1086 * reset is set, then perform link reset. 1087 */ 1088 ctrl = IXGBE_CTRL_LNK_RST; 1089 if (!hw->force_full_reset) { 1090 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1091 if (link_up) 1092 ctrl = IXGBE_CTRL_RST; 1093 } 1094 1095 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1096 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1097 IXGBE_WRITE_FLUSH(hw); 1098 1099 /* Poll for reset bit to self-clear meaning reset is complete */ 1100 for (i = 0; i < 10; i++) { 1101 usec_delay(1); 1102 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1103 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1104 break; 1105 } 1106 1107 if (ctrl & IXGBE_CTRL_RST_MASK) { 1108 status = IXGBE_ERR_RESET_FAILED; 1109 DEBUGOUT("Reset polling failed to complete.\n"); 1110 } 1111 1112 msec_delay(50); 1113 1114 /* 1115 * Double resets are required for recovery from certain error 1116 * conditions. Between resets, it is necessary to stall to 1117 * allow time for any pending HW events to complete. 1118 */ 1119 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1120 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1121 goto mac_reset_top; 1122 } 1123 1124 /* 1125 * Store the original AUTOC/AUTOC2 values if they have not been 1126 * stored off yet. Otherwise restore the stored original 1127 * values since the reset operation sets back to defaults. 1128 */ 1129 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1130 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1131 1132 /* Enable link if disabled in NVM */ 1133 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1134 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1135 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1136 IXGBE_WRITE_FLUSH(hw); 1137 } 1138 1139 if (hw->mac.orig_link_settings_stored == false) { 1140 hw->mac.orig_autoc = autoc; 1141 hw->mac.orig_autoc2 = autoc2; 1142 hw->mac.orig_link_settings_stored = true; 1143 } else { 1144 1145 /* If MNG FW is running on a multi-speed device that 1146 * doesn't autoneg with out driver support we need to 1147 * leave LMS in the state it was before we MAC reset. 1148 * Likewise if we support WoL we don't want change the 1149 * LMS state. 1150 */ 1151 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1152 hw->wol_enabled) 1153 hw->mac.orig_autoc = 1154 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1155 curr_lms; 1156 1157 if (autoc != hw->mac.orig_autoc) { 1158 status = hw->mac.ops.prot_autoc_write(hw, 1159 hw->mac.orig_autoc, 1160 false); 1161 if (status != IXGBE_SUCCESS) 1162 goto reset_hw_out; 1163 } 1164 1165 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1166 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1167 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1168 autoc2 |= (hw->mac.orig_autoc2 & 1169 IXGBE_AUTOC2_UPPER_MASK); 1170 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1171 } 1172 } 1173 1174 /* Store the permanent mac address */ 1175 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1176 1177 /* 1178 * Store MAC address from RAR0, clear receive address registers, and 1179 * clear the multicast table. Also reset num_rar_entries to 128, 1180 * since we modify this value when programming the SAN MAC address. 1181 */ 1182 hw->mac.num_rar_entries = 128; 1183 hw->mac.ops.init_rx_addrs(hw); 1184 1185 /* Store the permanent SAN mac address */ 1186 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1187 1188 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1189 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1190 /* Save the SAN MAC RAR index */ 1191 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1192 1193 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1194 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1195 1196 /* clear VMDq pool/queue selection for this RAR */ 1197 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1198 IXGBE_CLEAR_VMDQ_ALL); 1199 1200 /* Reserve the last RAR for the SAN MAC address */ 1201 hw->mac.num_rar_entries--; 1202 } 1203 1204 /* Store the alternative WWNN/WWPN prefix */ 1205 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1206 &hw->mac.wwpn_prefix); 1207 1208 reset_hw_out: 1209 return status; 1210 } 1211 1212 /** 1213 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1214 * @hw: pointer to hardware structure 1215 * @fdircmd: current value of FDIRCMD register 1216 */ 1217 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1218 { 1219 int i; 1220 1221 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1222 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1223 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1224 return IXGBE_SUCCESS; 1225 usec_delay(10); 1226 } 1227 1228 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1229 } 1230 1231 /** 1232 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1233 * @hw: pointer to hardware structure 1234 **/ 1235 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1236 { 1237 s32 err; 1238 int i; 1239 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1240 u32 fdircmd; 1241 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1242 1243 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1244 1245 /* 1246 * Before starting reinitialization process, 1247 * FDIRCMD.CMD must be zero. 1248 */ 1249 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1250 if (err) { 1251 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); 1252 return err; 1253 } 1254 1255 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1256 IXGBE_WRITE_FLUSH(hw); 1257 /* 1258 * 82599 adapters flow director init flow cannot be restarted, 1259 * Workaround 82599 silicon errata by performing the following steps 1260 * before re-writing the FDIRCTRL control register with the same value. 1261 * - write 1 to bit 8 of FDIRCMD register & 1262 * - write 0 to bit 8 of FDIRCMD register 1263 */ 1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1265 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1266 IXGBE_FDIRCMD_CLEARHT)); 1267 IXGBE_WRITE_FLUSH(hw); 1268 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1269 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1270 ~IXGBE_FDIRCMD_CLEARHT)); 1271 IXGBE_WRITE_FLUSH(hw); 1272 /* 1273 * Clear FDIR Hash register to clear any leftover hashes 1274 * waiting to be programmed. 1275 */ 1276 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1277 IXGBE_WRITE_FLUSH(hw); 1278 1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1280 IXGBE_WRITE_FLUSH(hw); 1281 1282 /* Poll init-done after we write FDIRCTRL register */ 1283 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1284 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1285 IXGBE_FDIRCTRL_INIT_DONE) 1286 break; 1287 msec_delay(1); 1288 } 1289 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1290 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1291 return IXGBE_ERR_FDIR_REINIT_FAILED; 1292 } 1293 1294 /* Clear FDIR statistics registers (read to clear) */ 1295 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1296 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1297 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1298 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1299 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1300 1301 return IXGBE_SUCCESS; 1302 } 1303 1304 /** 1305 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1306 * @hw: pointer to hardware structure 1307 * @fdirctrl: value to write to flow director control register 1308 **/ 1309 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1310 { 1311 int i; 1312 1313 DEBUGFUNC("ixgbe_fdir_enable_82599"); 1314 1315 /* Prime the keys for hashing */ 1316 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1317 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1318 1319 /* 1320 * Poll init-done after we write the register. Estimated times: 1321 * 10G: PBALLOC = 11b, timing is 60us 1322 * 1G: PBALLOC = 11b, timing is 600us 1323 * 100M: PBALLOC = 11b, timing is 6ms 1324 * 1325 * Multiple these timings by 4 if under full Rx load 1326 * 1327 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1328 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1329 * this might not finish in our poll time, but we can live with that 1330 * for now. 1331 */ 1332 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1333 IXGBE_WRITE_FLUSH(hw); 1334 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1335 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1336 IXGBE_FDIRCTRL_INIT_DONE) 1337 break; 1338 msec_delay(1); 1339 } 1340 1341 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1342 DEBUGOUT("Flow Director poll time exceeded!\n"); 1343 } 1344 1345 /** 1346 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1347 * @hw: pointer to hardware structure 1348 * @fdirctrl: value to write to flow director control register, initially 1349 * contains just the value of the Rx packet buffer allocation 1350 **/ 1351 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1352 { 1353 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1354 1355 /* 1356 * Continue setup of fdirctrl register bits: 1357 * Move the flexible bytes to use the ethertype - shift 6 words 1358 * Set the maximum length per hash bucket to 0xA filters 1359 * Send interrupt when 64 filters are left 1360 */ 1361 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1362 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1363 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1364 1365 /* write hashes and fdirctrl register, poll for completion */ 1366 ixgbe_fdir_enable_82599(hw, fdirctrl); 1367 1368 return IXGBE_SUCCESS; 1369 } 1370 1371 /** 1372 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1373 * @hw: pointer to hardware structure 1374 * @fdirctrl: value to write to flow director control register, initially 1375 * contains just the value of the Rx packet buffer allocation 1376 * @cloud_mode: true - cloud mode, false - other mode 1377 **/ 1378 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 1379 bool cloud_mode) 1380 { 1381 UNREFERENCED_1PARAMETER(cloud_mode); 1382 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1383 1384 /* 1385 * Continue setup of fdirctrl register bits: 1386 * Turn perfect match filtering on 1387 * Report hash in RSS field of Rx wb descriptor 1388 * Initialize the drop queue to queue 127 1389 * Move the flexible bytes to use the ethertype - shift 6 words 1390 * Set the maximum length per hash bucket to 0xA filters 1391 * Send interrupt when 64 (0x4 * 16) filters are left 1392 */ 1393 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1394 IXGBE_FDIRCTRL_REPORT_STATUS | 1395 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1396 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1397 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1398 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1399 1400 if (cloud_mode) 1401 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << 1402 IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 1403 1404 /* write hashes and fdirctrl register, poll for completion */ 1405 ixgbe_fdir_enable_82599(hw, fdirctrl); 1406 1407 return IXGBE_SUCCESS; 1408 } 1409 1410 /** 1411 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue 1412 * @hw: pointer to hardware structure 1413 * @dropqueue: Rx queue index used for the dropped packets 1414 **/ 1415 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) 1416 { 1417 u32 fdirctrl; 1418 1419 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); 1420 /* Clear init done bit and drop queue field */ 1421 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1422 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); 1423 1424 /* Set drop queue */ 1425 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1426 if ((hw->mac.type == ixgbe_mac_X550) || 1427 (hw->mac.type == ixgbe_mac_X550EM_x) || 1428 (hw->mac.type == ixgbe_mac_X550EM_a)) 1429 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1430 1431 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1432 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1433 IXGBE_FDIRCMD_CLEARHT)); 1434 IXGBE_WRITE_FLUSH(hw); 1435 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1436 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1437 ~IXGBE_FDIRCMD_CLEARHT)); 1438 IXGBE_WRITE_FLUSH(hw); 1439 1440 /* write hashes and fdirctrl register, poll for completion */ 1441 ixgbe_fdir_enable_82599(hw, fdirctrl); 1442 } 1443 1444 /* 1445 * These defines allow us to quickly generate all of the necessary instructions 1446 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1447 * for values 0 through 15 1448 */ 1449 #define IXGBE_ATR_COMMON_HASH_KEY \ 1450 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1451 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1452 do { \ 1453 u32 n = (_n); \ 1454 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1455 common_hash ^= lo_hash_dword >> n; \ 1456 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1457 bucket_hash ^= lo_hash_dword >> n; \ 1458 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1459 sig_hash ^= lo_hash_dword << (16 - n); \ 1460 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1461 common_hash ^= hi_hash_dword >> n; \ 1462 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1463 bucket_hash ^= hi_hash_dword >> n; \ 1464 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1465 sig_hash ^= hi_hash_dword << (16 - n); \ 1466 } while (0) 1467 1468 /** 1469 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1470 * @input: input bitstream to compute the hash on 1471 * @common: compressed common input dword 1472 * 1473 * This function is almost identical to the function above but contains 1474 * several optimizations such as unwinding all of the loops, letting the 1475 * compiler work out all of the conditional ifs since the keys are static 1476 * defines, and computing two keys at once since the hashed dword stream 1477 * will be the same for both keys. 1478 **/ 1479 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1480 union ixgbe_atr_hash_dword common) 1481 { 1482 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1483 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1484 1485 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1486 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1487 1488 /* generate common hash dword */ 1489 hi_hash_dword = IXGBE_NTOHL(common.dword); 1490 1491 /* low dword is word swapped version of common */ 1492 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1493 1494 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1495 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1496 1497 /* Process bits 0 and 16 */ 1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1499 1500 /* 1501 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1502 * delay this because bit 0 of the stream should not be processed 1503 * so we do not add the VLAN until after bit 0 was processed 1504 */ 1505 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1506 1507 /* Process remaining 30 bit of the key */ 1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1510 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1519 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1520 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1521 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1522 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1523 1524 /* combine common_hash result with signature and bucket hashes */ 1525 bucket_hash ^= common_hash; 1526 bucket_hash &= IXGBE_ATR_HASH_MASK; 1527 1528 sig_hash ^= common_hash << 16; 1529 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1530 1531 /* return completed signature hash */ 1532 return sig_hash ^ bucket_hash; 1533 } 1534 1535 /** 1536 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1537 * @hw: pointer to hardware structure 1538 * @input: unique input dword 1539 * @common: compressed common input dword 1540 * @queue: queue index to direct traffic to 1541 * 1542 * Note that the tunnel bit in input must not be set when the hardware 1543 * tunneling support does not exist. 1544 **/ 1545 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1546 union ixgbe_atr_hash_dword input, 1547 union ixgbe_atr_hash_dword common, 1548 u8 queue) 1549 { 1550 u64 fdirhashcmd; 1551 u8 flow_type; 1552 bool tunnel; 1553 u32 fdircmd; 1554 1555 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1556 1557 /* 1558 * Get the flow_type in order to program FDIRCMD properly 1559 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1560 * fifth is FDIRCMD.TUNNEL_FILTER 1561 */ 1562 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1563 flow_type = input.formatted.flow_type & 1564 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1565 switch (flow_type) { 1566 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1567 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1568 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1569 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1570 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1571 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1572 break; 1573 default: 1574 DEBUGOUT(" Error on flow type input\n"); 1575 return; 1576 } 1577 1578 /* configure FDIRCMD register */ 1579 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1580 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1581 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1582 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1583 if (tunnel) 1584 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1585 1586 /* 1587 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1588 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1589 */ 1590 fdirhashcmd = (u64)fdircmd << 32; 1591 fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common); 1592 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1593 1594 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1595 1596 return; 1597 } 1598 1599 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1600 do { \ 1601 u32 n = (_n); \ 1602 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1603 bucket_hash ^= lo_hash_dword >> n; \ 1604 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1605 bucket_hash ^= hi_hash_dword >> n; \ 1606 } while (0) 1607 1608 /** 1609 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1610 * @input: input bitstream to compute the hash on 1611 * @input_mask: mask for the input bitstream 1612 * 1613 * This function serves two main purposes. First it applies the input_mask 1614 * to the atr_input resulting in a cleaned up atr_input data stream. 1615 * Secondly it computes the hash and stores it in the bkt_hash field at 1616 * the end of the input byte stream. This way it will be available for 1617 * future use without needing to recompute the hash. 1618 **/ 1619 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1620 union ixgbe_atr_input *input_mask) 1621 { 1622 1623 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1624 u32 bucket_hash = 0; 1625 u32 hi_dword = 0; 1626 u32 i = 0; 1627 1628 /* Apply masks to input data */ 1629 for (i = 0; i < 14; i++) 1630 input->dword_stream[i] &= input_mask->dword_stream[i]; 1631 1632 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1633 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1634 1635 /* generate common hash dword */ 1636 for (i = 1; i <= 13; i++) 1637 hi_dword ^= input->dword_stream[i]; 1638 hi_hash_dword = IXGBE_NTOHL(hi_dword); 1639 1640 /* low dword is word swapped version of common */ 1641 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1642 1643 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1644 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1645 1646 /* Process bits 0 and 16 */ 1647 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1648 1649 /* 1650 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1651 * delay this because bit 0 of the stream should not be processed 1652 * so we do not add the VLAN until after bit 0 was processed 1653 */ 1654 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1655 1656 /* Process remaining 30 bit of the key */ 1657 for (i = 1; i <= 15; i++) 1658 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1659 1660 /* 1661 * Limit hash to 13 bits since max bucket count is 8K. 1662 * Store result at the end of the input stream. 1663 */ 1664 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1665 } 1666 1667 /** 1668 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks 1669 * @input_mask: mask to be bit swapped 1670 * 1671 * The source and destination port masks for flow director are bit swapped 1672 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1673 * generate a correctly swapped value we need to bit swap the mask and that 1674 * is what is accomplished by this function. 1675 **/ 1676 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1677 { 1678 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1679 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1680 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port); 1681 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1682 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1683 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1684 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1685 } 1686 1687 /* 1688 * These two macros are meant to address the fact that we have registers 1689 * that are either all or in part big-endian. As a result on big-endian 1690 * systems we will end up byte swapping the value to little-endian before 1691 * it is byte swapped again and written to the hardware in the original 1692 * big-endian format. 1693 */ 1694 #define IXGBE_STORE_AS_BE32(_value) \ 1695 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1696 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1697 1698 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1699 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1700 1701 #define IXGBE_STORE_AS_BE16(_value) \ 1702 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1703 1704 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1705 union ixgbe_atr_input *input_mask, bool cloud_mode) 1706 { 1707 /* mask IPv6 since it is currently not supported */ 1708 u32 fdirm = IXGBE_FDIRM_DIPv6; 1709 u32 fdirtcpm; 1710 u32 fdirip6m; 1711 UNREFERENCED_1PARAMETER(cloud_mode); 1712 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1713 1714 /* 1715 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1716 * are zero, then assume a full mask for that field. Also assume that 1717 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1718 * cannot be masked out in this implementation. 1719 * 1720 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1721 * point in time. 1722 */ 1723 1724 /* verify bucket hash is cleared on hash generation */ 1725 if (input_mask->formatted.bkt_hash) 1726 DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1727 1728 /* Program FDIRM and verify partial masks */ 1729 switch (input_mask->formatted.vm_pool & 0x7F) { 1730 case 0x0: 1731 fdirm |= IXGBE_FDIRM_POOL; 1732 case 0x7F: 1733 break; 1734 default: 1735 DEBUGOUT(" Error on vm pool mask\n"); 1736 return IXGBE_ERR_CONFIG; 1737 } 1738 1739 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1740 case 0x0: 1741 fdirm |= IXGBE_FDIRM_L4P; 1742 if (input_mask->formatted.dst_port || 1743 input_mask->formatted.src_port) { 1744 DEBUGOUT(" Error on src/dst port mask\n"); 1745 return IXGBE_ERR_CONFIG; 1746 } 1747 case IXGBE_ATR_L4TYPE_MASK: 1748 break; 1749 default: 1750 DEBUGOUT(" Error on flow type mask\n"); 1751 return IXGBE_ERR_CONFIG; 1752 } 1753 1754 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1755 case 0x0000: 1756 /* mask VLAN ID */ 1757 fdirm |= IXGBE_FDIRM_VLANID; 1758 /* FALLTHROUGH */ 1759 case 0x0FFF: 1760 /* mask VLAN priority */ 1761 fdirm |= IXGBE_FDIRM_VLANP; 1762 break; 1763 case 0xE000: 1764 /* mask VLAN ID only */ 1765 fdirm |= IXGBE_FDIRM_VLANID; 1766 /* fall through */ 1767 case 0xEFFF: 1768 /* no VLAN fields masked */ 1769 break; 1770 default: 1771 DEBUGOUT(" Error on VLAN mask\n"); 1772 return IXGBE_ERR_CONFIG; 1773 } 1774 1775 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1776 case 0x0000: 1777 /* Mask Flex Bytes */ 1778 fdirm |= IXGBE_FDIRM_FLEX; 1779 /* fall through */ 1780 case 0xFFFF: 1781 break; 1782 default: 1783 DEBUGOUT(" Error on flexible byte mask\n"); 1784 return IXGBE_ERR_CONFIG; 1785 } 1786 1787 if (cloud_mode) { 1788 fdirm |= IXGBE_FDIRM_L3P; 1789 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 1790 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 1791 1792 switch (input_mask->formatted.inner_mac[0] & 0xFF) { 1793 case 0x00: 1794 /* Mask inner MAC, fall through */ 1795 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; 1796 case 0xFF: 1797 break; 1798 default: 1799 DEBUGOUT(" Error on inner_mac byte mask\n"); 1800 return IXGBE_ERR_CONFIG; 1801 } 1802 1803 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { 1804 case 0x0: 1805 /* Mask vxlan id */ 1806 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; 1807 break; 1808 case 0x00FFFFFF: 1809 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 1810 break; 1811 case 0xFFFFFFFF: 1812 break; 1813 default: 1814 DEBUGOUT(" Error on TNI/VNI byte mask\n"); 1815 return IXGBE_ERR_CONFIG; 1816 } 1817 1818 switch (input_mask->formatted.tunnel_type & 0xFFFF) { 1819 case 0x0: 1820 /* Mask turnnel type, fall through */ 1821 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 1822 case 0xFFFF: 1823 break; 1824 default: 1825 DEBUGOUT(" Error on tunnel type byte mask\n"); 1826 return IXGBE_ERR_CONFIG; 1827 } 1828 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); 1829 1830 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, 1831 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow 1832 * L3/L3 packets to tunnel. 1833 */ 1834 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 1835 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 1836 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 1837 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 1838 switch (hw->mac.type) { 1839 case ixgbe_mac_X550: 1840 case ixgbe_mac_X550EM_x: 1841 case ixgbe_mac_X550EM_a: 1842 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); 1843 break; 1844 default: 1845 break; 1846 } 1847 } 1848 1849 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1850 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1851 1852 if (!cloud_mode) { 1853 /* store the TCP/UDP port masks, bit reversed from port 1854 * layout */ 1855 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1856 1857 /* write both the same so that UDP and TCP use the same mask */ 1858 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1859 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1860 /* also use it for SCTP */ 1861 switch (hw->mac.type) { 1862 case ixgbe_mac_X550: 1863 case ixgbe_mac_X550EM_x: 1864 case ixgbe_mac_X550EM_a: 1865 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1866 break; 1867 default: 1868 break; 1869 } 1870 1871 /* store source and destination IP masks (big-enian) */ 1872 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1873 ~input_mask->formatted.src_ip[0]); 1874 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1875 ~input_mask->formatted.dst_ip[0]); 1876 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF); 1877 } 1878 return IXGBE_SUCCESS; 1879 } 1880 1881 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1882 union ixgbe_atr_input *input, 1883 u16 soft_id, u8 queue, bool cloud_mode) 1884 { 1885 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1886 u32 addr_low, addr_high; 1887 u32 cloud_type = 0; 1888 s32 err; 1889 UNREFERENCED_1PARAMETER(cloud_mode); 1890 1891 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1892 if (!cloud_mode) { 1893 /* currently IPv6 is not supported, must be programmed with 0 */ 1894 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1895 input->formatted.src_ip[0]); 1896 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1897 input->formatted.src_ip[1]); 1898 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1899 input->formatted.src_ip[2]); 1900 1901 /* record the source address (big-endian) */ 1902 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, 1903 input->formatted.src_ip[0]); 1904 1905 /* record the first 32 bits of the destination address 1906 * (big-endian) */ 1907 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, 1908 input->formatted.dst_ip[0]); 1909 1910 /* record source and destination port (little-endian)*/ 1911 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1912 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1913 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port); 1914 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1915 } 1916 1917 /* record VLAN (little-endian) and flex_bytes(big-endian) */ 1918 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1919 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1920 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id); 1921 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1922 1923 if (cloud_mode) { 1924 if (input->formatted.tunnel_type != 0) 1925 cloud_type = 0x80000000; 1926 1927 addr_low = ((u32)input->formatted.inner_mac[0] | 1928 ((u32)input->formatted.inner_mac[1] << 8) | 1929 ((u32)input->formatted.inner_mac[2] << 16) | 1930 ((u32)input->formatted.inner_mac[3] << 24)); 1931 addr_high = ((u32)input->formatted.inner_mac[4] | 1932 ((u32)input->formatted.inner_mac[5] << 8)); 1933 cloud_type |= addr_high; 1934 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); 1935 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); 1936 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); 1937 } 1938 1939 /* configure FDIRHASH register */ 1940 fdirhash = input->formatted.bkt_hash; 1941 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1942 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1943 1944 /* 1945 * flush all previous writes to make certain registers are 1946 * programmed prior to issuing the command 1947 */ 1948 IXGBE_WRITE_FLUSH(hw); 1949 1950 /* configure FDIRCMD register */ 1951 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1952 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1953 if (queue == IXGBE_FDIR_DROP_QUEUE) 1954 fdircmd |= IXGBE_FDIRCMD_DROP; 1955 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) 1956 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1957 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1958 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1959 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1960 1961 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1962 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1963 if (err) { 1964 DEBUGOUT("Flow Director command did not complete!\n"); 1965 return err; 1966 } 1967 1968 return IXGBE_SUCCESS; 1969 } 1970 1971 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1972 union ixgbe_atr_input *input, 1973 u16 soft_id) 1974 { 1975 u32 fdirhash; 1976 u32 fdircmd; 1977 s32 err; 1978 1979 /* configure FDIRHASH register */ 1980 fdirhash = input->formatted.bkt_hash; 1981 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1982 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1983 1984 /* flush hash to HW */ 1985 IXGBE_WRITE_FLUSH(hw); 1986 1987 /* Query if filter is present */ 1988 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1989 1990 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1991 if (err) { 1992 DEBUGOUT("Flow Director command did not complete!\n"); 1993 return err; 1994 } 1995 1996 /* if filter exists in hardware then remove it */ 1997 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1998 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1999 IXGBE_WRITE_FLUSH(hw); 2000 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 2001 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 2002 } 2003 2004 return IXGBE_SUCCESS; 2005 } 2006 2007 /** 2008 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 2009 * @hw: pointer to hardware structure 2010 * @input: input bitstream 2011 * @input_mask: mask for the input bitstream 2012 * @soft_id: software index for the filters 2013 * @queue: queue index to direct traffic to 2014 * @cloud_mode: unused 2015 * 2016 * Note that the caller to this function must lock before calling, since the 2017 * hardware writes must be protected from one another. 2018 **/ 2019 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 2020 union ixgbe_atr_input *input, 2021 union ixgbe_atr_input *input_mask, 2022 u16 soft_id, u8 queue, bool cloud_mode) 2023 { 2024 s32 err = IXGBE_ERR_CONFIG; 2025 UNREFERENCED_1PARAMETER(cloud_mode); 2026 2027 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 2028 2029 /* 2030 * Check flow_type formatting, and bail out before we touch the hardware 2031 * if there's a configuration issue 2032 */ 2033 switch (input->formatted.flow_type) { 2034 case IXGBE_ATR_FLOW_TYPE_IPV4: 2035 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: 2036 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 2037 if (input->formatted.dst_port || input->formatted.src_port) { 2038 DEBUGOUT(" Error on src/dst port\n"); 2039 return IXGBE_ERR_CONFIG; 2040 } 2041 break; 2042 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2043 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: 2044 if (input->formatted.dst_port || input->formatted.src_port) { 2045 DEBUGOUT(" Error on src/dst port\n"); 2046 return IXGBE_ERR_CONFIG; 2047 } 2048 /* FALLTHROUGH */ 2049 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2050 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: 2051 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2052 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: 2053 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2054 IXGBE_ATR_L4TYPE_MASK; 2055 break; 2056 default: 2057 DEBUGOUT(" Error on flow type input\n"); 2058 return err; 2059 } 2060 2061 /* program input mask into the HW */ 2062 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); 2063 if (err) 2064 return err; 2065 2066 /* apply mask and compute/store hash */ 2067 ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 2068 2069 /* program filters to filter memory */ 2070 return ixgbe_fdir_write_perfect_filter_82599(hw, input, 2071 soft_id, queue, cloud_mode); 2072 } 2073 2074 /** 2075 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2076 * @hw: pointer to hardware structure 2077 * @reg: analog register to read 2078 * @val: read value 2079 * 2080 * Performs read operation to Omer analog register specified. 2081 **/ 2082 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2083 { 2084 u32 core_ctl; 2085 2086 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2087 2088 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2089 (reg << 8)); 2090 IXGBE_WRITE_FLUSH(hw); 2091 usec_delay(10); 2092 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2093 *val = (u8)core_ctl; 2094 2095 return IXGBE_SUCCESS; 2096 } 2097 2098 /** 2099 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2100 * @hw: pointer to hardware structure 2101 * @reg: atlas register to write 2102 * @val: value to write 2103 * 2104 * Performs write operation to Omer analog register specified. 2105 **/ 2106 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2107 { 2108 u32 core_ctl; 2109 2110 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2111 2112 core_ctl = (reg << 8) | val; 2113 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2114 IXGBE_WRITE_FLUSH(hw); 2115 usec_delay(10); 2116 2117 return IXGBE_SUCCESS; 2118 } 2119 2120 /** 2121 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 2122 * @hw: pointer to hardware structure 2123 * 2124 * Starts the hardware using the generic start_hw function 2125 * and the generation start_hw function. 2126 * Then performs revision-specific operations, if any. 2127 **/ 2128 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 2129 { 2130 s32 ret_val = IXGBE_SUCCESS; 2131 2132 DEBUGFUNC("ixgbe_start_hw_82599"); 2133 2134 ret_val = ixgbe_start_hw_generic(hw); 2135 if (ret_val != IXGBE_SUCCESS) 2136 goto out; 2137 2138 ixgbe_start_hw_gen2(hw); 2139 2140 /* We need to run link autotry after the driver loads */ 2141 hw->mac.autotry_restart = true; 2142 2143 if (ret_val == IXGBE_SUCCESS) 2144 ret_val = ixgbe_verify_fw_version_82599(hw); 2145 out: 2146 return ret_val; 2147 } 2148 2149 /** 2150 * ixgbe_identify_phy_82599 - Get physical layer module 2151 * @hw: pointer to hardware structure 2152 * 2153 * Determines the physical layer module found on the current adapter. 2154 * If PHY already detected, maintains current PHY type in hw struct, 2155 * otherwise executes the PHY detection routine. 2156 **/ 2157 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2158 { 2159 s32 status; 2160 2161 DEBUGFUNC("ixgbe_identify_phy_82599"); 2162 2163 /* Detect PHY if not unknown - returns success if already detected. */ 2164 status = ixgbe_identify_phy_generic(hw); 2165 if (status != IXGBE_SUCCESS) { 2166 /* 82599 10GBASE-T requires an external PHY */ 2167 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 2168 return status; 2169 else 2170 status = ixgbe_identify_module_generic(hw); 2171 } 2172 2173 /* Set PHY type none if no PHY detected */ 2174 if (hw->phy.type == ixgbe_phy_unknown) { 2175 hw->phy.type = ixgbe_phy_none; 2176 return IXGBE_SUCCESS; 2177 } 2178 2179 /* Return error if SFP module has been detected but is not supported */ 2180 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2181 return IXGBE_ERR_SFP_NOT_SUPPORTED; 2182 2183 return status; 2184 } 2185 2186 /** 2187 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2188 * @hw: pointer to hardware structure 2189 * 2190 * Determines physical layer capabilities of the current configuration. 2191 **/ 2192 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2193 { 2194 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2195 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2196 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2197 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2198 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2199 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2200 u16 ext_ability = 0; 2201 2202 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2203 2204 hw->phy.ops.identify(hw); 2205 2206 switch (hw->phy.type) { 2207 case ixgbe_phy_tn: 2208 case ixgbe_phy_cu_unknown: 2209 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2210 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2211 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2212 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2213 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2214 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2215 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2216 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2217 goto out; 2218 default: 2219 break; 2220 } 2221 2222 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2223 case IXGBE_AUTOC_LMS_1G_AN: 2224 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2225 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2226 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2227 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2228 goto out; 2229 } else 2230 /* SFI mode so read SFP module */ 2231 goto sfp_check; 2232 break; 2233 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2234 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2235 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2236 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2237 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2238 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2239 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2240 goto out; 2241 break; 2242 case IXGBE_AUTOC_LMS_10G_SERIAL: 2243 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2244 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2245 goto out; 2246 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2247 goto sfp_check; 2248 break; 2249 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2250 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2251 if (autoc & IXGBE_AUTOC_KX_SUPP) 2252 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2253 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2254 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2255 if (autoc & IXGBE_AUTOC_KR_SUPP) 2256 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2257 goto out; 2258 break; 2259 default: 2260 goto out; 2261 break; 2262 } 2263 2264 sfp_check: 2265 /* SFP check must be done last since DA modules are sometimes used to 2266 * test KR mode - we need to id KR mode correctly before SFP module. 2267 * Call identify_sfp because the pluggable module may have changed */ 2268 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2269 out: 2270 return physical_layer; 2271 } 2272 2273 /** 2274 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2275 * @hw: pointer to hardware structure 2276 * @regval: register value to write to RXCTRL 2277 * 2278 * Enables the Rx DMA unit for 82599 2279 **/ 2280 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2281 { 2282 2283 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2284 2285 /* 2286 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2287 * If traffic is incoming before we enable the Rx unit, it could hang 2288 * the Rx DMA unit. Therefore, make sure the security engine is 2289 * completely disabled prior to enabling the Rx unit. 2290 */ 2291 2292 hw->mac.ops.disable_sec_rx_path(hw); 2293 2294 if (regval & IXGBE_RXCTRL_RXEN) 2295 ixgbe_enable_rx(hw); 2296 else 2297 ixgbe_disable_rx(hw); 2298 2299 hw->mac.ops.enable_sec_rx_path(hw); 2300 2301 return IXGBE_SUCCESS; 2302 } 2303 2304 /** 2305 * ixgbe_verify_fw_version_82599 - verify FW version for 82599 2306 * @hw: pointer to hardware structure 2307 * 2308 * Verifies that installed the firmware version is 0.6 or higher 2309 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2310 * 2311 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2312 * if the FW version is not supported. 2313 **/ 2314 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2315 { 2316 s32 status = IXGBE_ERR_EEPROM_VERSION; 2317 u16 fw_offset, fw_ptp_cfg_offset; 2318 u16 fw_version; 2319 2320 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2321 2322 /* firmware check is only necessary for SFI devices */ 2323 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2324 status = IXGBE_SUCCESS; 2325 goto fw_version_out; 2326 } 2327 2328 /* get the offset to the Firmware Module block */ 2329 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 2330 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2331 "eeprom read at offset %d failed", IXGBE_FW_PTR); 2332 return IXGBE_ERR_EEPROM_VERSION; 2333 } 2334 2335 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2336 goto fw_version_out; 2337 2338 /* get the offset to the Pass Through Patch Configuration block */ 2339 if (hw->eeprom.ops.read(hw, (fw_offset + 2340 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2341 &fw_ptp_cfg_offset)) { 2342 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2343 "eeprom read at offset %d failed", 2344 fw_offset + 2345 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 2346 return IXGBE_ERR_EEPROM_VERSION; 2347 } 2348 2349 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2350 goto fw_version_out; 2351 2352 /* get the firmware version */ 2353 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2354 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 2355 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2356 "eeprom read at offset %d failed", 2357 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 2358 return IXGBE_ERR_EEPROM_VERSION; 2359 } 2360 2361 if (fw_version > 0x5) 2362 status = IXGBE_SUCCESS; 2363 2364 fw_version_out: 2365 return status; 2366 } 2367 2368 /** 2369 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2370 * @hw: pointer to hardware structure 2371 * 2372 * Returns true if the LESM FW module is present and enabled. Otherwise 2373 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2374 **/ 2375 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2376 { 2377 bool lesm_enabled = false; 2378 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2379 s32 status; 2380 2381 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2382 2383 /* get the offset to the Firmware Module block */ 2384 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2385 2386 if ((status != IXGBE_SUCCESS) || 2387 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2388 goto out; 2389 2390 /* get the offset to the LESM Parameters block */ 2391 status = hw->eeprom.ops.read(hw, (fw_offset + 2392 IXGBE_FW_LESM_PARAMETERS_PTR), 2393 &fw_lesm_param_offset); 2394 2395 if ((status != IXGBE_SUCCESS) || 2396 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2397 goto out; 2398 2399 /* get the LESM state word */ 2400 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2401 IXGBE_FW_LESM_STATE_1), 2402 &fw_lesm_state); 2403 2404 if ((status == IXGBE_SUCCESS) && 2405 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2406 lesm_enabled = true; 2407 2408 out: 2409 return lesm_enabled; 2410 } 2411 2412 /** 2413 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2414 * fastest available method 2415 * 2416 * @hw: pointer to hardware structure 2417 * @offset: offset of word in EEPROM to read 2418 * @words: number of words 2419 * @data: word(s) read from the EEPROM 2420 * 2421 * Retrieves 16 bit word(s) read from EEPROM 2422 **/ 2423 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2424 u16 words, u16 *data) 2425 { 2426 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2427 s32 ret_val = IXGBE_ERR_CONFIG; 2428 2429 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2430 2431 /* 2432 * If EEPROM is detected and can be addressed using 14 bits, 2433 * use EERD otherwise use bit bang 2434 */ 2435 if ((eeprom->type == ixgbe_eeprom_spi) && 2436 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2437 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2438 data); 2439 else 2440 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2441 words, 2442 data); 2443 2444 return ret_val; 2445 } 2446 2447 /** 2448 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2449 * fastest available method 2450 * 2451 * @hw: pointer to hardware structure 2452 * @offset: offset of word in the EEPROM to read 2453 * @data: word read from the EEPROM 2454 * 2455 * Reads a 16 bit word from the EEPROM 2456 **/ 2457 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2458 u16 offset, u16 *data) 2459 { 2460 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2461 s32 ret_val = IXGBE_ERR_CONFIG; 2462 2463 DEBUGFUNC("ixgbe_read_eeprom_82599"); 2464 2465 /* 2466 * If EEPROM is detected and can be addressed using 14 bits, 2467 * use EERD otherwise use bit bang 2468 */ 2469 if ((eeprom->type == ixgbe_eeprom_spi) && 2470 (offset <= IXGBE_EERD_MAX_ADDR)) 2471 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2472 else 2473 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2474 2475 return ret_val; 2476 } 2477 2478 /** 2479 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2480 * 2481 * @hw: pointer to hardware structure 2482 * 2483 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2484 * full pipeline reset. This function assumes the SW/FW lock is held. 2485 **/ 2486 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2487 { 2488 s32 ret_val; 2489 u32 anlp1_reg = 0; 2490 u32 i, autoc_reg, autoc2_reg; 2491 2492 /* Enable link if disabled in NVM */ 2493 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2494 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2495 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2496 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2497 IXGBE_WRITE_FLUSH(hw); 2498 } 2499 2500 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2501 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2502 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2503 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2504 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2505 /* Wait for AN to leave state 0 */ 2506 for (i = 0; i < 10; i++) { 2507 msec_delay(4); 2508 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2509 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2510 break; 2511 } 2512 2513 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2514 DEBUGOUT("auto negotiation not completed\n"); 2515 ret_val = IXGBE_ERR_RESET_FAILED; 2516 goto reset_pipeline_out; 2517 } 2518 2519 ret_val = IXGBE_SUCCESS; 2520 2521 reset_pipeline_out: 2522 /* Write AUTOC register with original LMS field and Restart_AN */ 2523 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2524 IXGBE_WRITE_FLUSH(hw); 2525 2526 return ret_val; 2527 } 2528 2529 /** 2530 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2531 * @hw: pointer to hardware structure 2532 * @byte_offset: byte offset to read 2533 * @dev_addr: address to read from 2534 * @data: value read 2535 * 2536 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2537 * a specified device address. 2538 **/ 2539 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2540 u8 dev_addr, u8 *data) 2541 { 2542 u32 esdp; 2543 s32 status; 2544 s32 timeout = 200; 2545 2546 DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 2547 2548 if (hw->phy.qsfp_shared_i2c_bus == true) { 2549 /* Acquire I2C bus ownership. */ 2550 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2551 esdp |= IXGBE_ESDP_SDP0; 2552 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2553 IXGBE_WRITE_FLUSH(hw); 2554 2555 while (timeout) { 2556 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2557 if (esdp & IXGBE_ESDP_SDP1) 2558 break; 2559 2560 msec_delay(5); 2561 timeout--; 2562 } 2563 2564 if (!timeout) { 2565 DEBUGOUT("Driver can't access resource," 2566 " acquiring I2C bus timeout.\n"); 2567 status = IXGBE_ERR_I2C; 2568 goto release_i2c_access; 2569 } 2570 } 2571 2572 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2573 2574 release_i2c_access: 2575 2576 if (hw->phy.qsfp_shared_i2c_bus == true) { 2577 /* Release I2C bus ownership. */ 2578 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2579 esdp &= ~IXGBE_ESDP_SDP0; 2580 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2581 IXGBE_WRITE_FLUSH(hw); 2582 } 2583 2584 return status; 2585 } 2586 2587 /** 2588 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2589 * @hw: pointer to hardware structure 2590 * @byte_offset: byte offset to write 2591 * @dev_addr: address to read from 2592 * @data: value to write 2593 * 2594 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2595 * a specified device address. 2596 **/ 2597 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2598 u8 dev_addr, u8 data) 2599 { 2600 u32 esdp; 2601 s32 status; 2602 s32 timeout = 200; 2603 2604 DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 2605 2606 if (hw->phy.qsfp_shared_i2c_bus == true) { 2607 /* Acquire I2C bus ownership. */ 2608 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2609 esdp |= IXGBE_ESDP_SDP0; 2610 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2611 IXGBE_WRITE_FLUSH(hw); 2612 2613 while (timeout) { 2614 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2615 if (esdp & IXGBE_ESDP_SDP1) 2616 break; 2617 2618 msec_delay(5); 2619 timeout--; 2620 } 2621 2622 if (!timeout) { 2623 DEBUGOUT("Driver can't access resource," 2624 " acquiring I2C bus timeout.\n"); 2625 status = IXGBE_ERR_I2C; 2626 goto release_i2c_access; 2627 } 2628 } 2629 2630 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2631 2632 release_i2c_access: 2633 2634 if (hw->phy.qsfp_shared_i2c_bus == true) { 2635 /* Release I2C bus ownership. */ 2636 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2637 esdp &= ~IXGBE_ESDP_SDP0; 2638 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2639 IXGBE_WRITE_FLUSH(hw); 2640 } 2641 2642 return status; 2643 }
Cache object: d2717997cb939d041b974099c94884a1
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