Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ixgbe/ixgbe_api.h
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1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _IXGBE_API_H_ 37 #define _IXGBE_API_H_ 38 39 #include "ixgbe_type.h" 40 41 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map); 42 43 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw); 44 45 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 46 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 47 extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw); 48 extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw); 49 extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw); 50 extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw); 51 extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw); 52 extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw); 53 54 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw); 55 s32 ixgbe_init_hw(struct ixgbe_hw *hw); 56 s32 ixgbe_reset_hw(struct ixgbe_hw *hw); 57 s32 ixgbe_start_hw(struct ixgbe_hw *hw); 58 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw); 59 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); 60 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw); 61 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr); 62 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw); 63 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw); 64 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw); 65 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw); 66 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num); 67 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size); 68 69 s32 ixgbe_identify_phy(struct ixgbe_hw *hw); 70 s32 ixgbe_reset_phy(struct ixgbe_hw *hw); 71 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 72 u16 *phy_data); 73 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 74 u16 phy_data); 75 76 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw); 77 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw); 78 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, 79 ixgbe_link_speed *speed, 80 bool *link_up); 81 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, 82 ixgbe_link_speed speed, 83 bool autoneg_wait_to_complete); 84 s32 ixgbe_set_phy_power(struct ixgbe_hw *, bool on); 85 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw); 86 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw); 87 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw); 88 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 89 bool autoneg_wait_to_complete); 90 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 91 bool autoneg_wait_to_complete); 92 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 93 bool *link_up, bool link_up_wait_to_complete); 94 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 95 bool *autoneg); 96 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index); 97 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index); 98 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index); 99 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index); 100 101 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw); 102 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data); 103 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 104 u16 words, u16 *data); 105 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data); 106 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 107 u16 words, u16 *data); 108 109 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val); 110 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw); 111 112 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 113 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 114 u32 enable_addr); 115 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index); 116 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 117 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq); 118 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 119 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); 120 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw); 121 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 122 u32 addr_count, ixgbe_mc_addr_itr func); 123 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 124 u32 mc_addr_count, ixgbe_mc_addr_itr func, 125 bool clear); 126 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq); 127 s32 ixgbe_enable_mc(struct ixgbe_hw *hw); 128 s32 ixgbe_disable_mc(struct ixgbe_hw *hw); 129 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); 130 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, 131 u32 vind, bool vlan_on, bool vlvf_bypass); 132 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, 133 bool vlan_on, u32 *vfta_delta, u32 vfta, 134 bool vlvf_bypass); 135 s32 ixgbe_fc_enable(struct ixgbe_hw *hw); 136 s32 ixgbe_setup_fc(struct ixgbe_hw *hw); 137 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 138 u8 ver, u16 len, char *driver_ver); 139 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw); 140 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw); 141 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr); 142 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, 143 u16 *firmware_version); 144 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val); 145 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val); 146 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw); 147 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data); 148 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw); 149 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval); 150 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw); 151 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw); 152 s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw); 153 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 154 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 155 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 156 bool cloud_mode); 157 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 158 union ixgbe_atr_hash_dword input, 159 union ixgbe_atr_hash_dword common, 160 u8 queue); 161 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 162 union ixgbe_atr_input *input_mask, bool cloud_mode); 163 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 164 union ixgbe_atr_input *input, 165 u16 soft_id, u8 queue, bool cloud_mode); 166 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 167 union ixgbe_atr_input *input, 168 u16 soft_id); 169 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 170 union ixgbe_atr_input *input, 171 union ixgbe_atr_input *mask, 172 u16 soft_id, 173 u8 queue, 174 bool cloud_mode); 175 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 176 union ixgbe_atr_input *mask); 177 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 178 union ixgbe_atr_hash_dword common); 179 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 180 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 181 u8 *data); 182 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 183 u8 dev_addr, u8 *data); 184 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val); 185 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val); 186 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 187 u8 data); 188 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue); 189 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 190 u8 dev_addr, u8 data); 191 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val); 192 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val); 193 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data); 194 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); 195 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); 196 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps); 197 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask); 198 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask); 199 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw); 200 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 201 u16 *wwpn_prefix); 202 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs); 203 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status); 204 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action); 205 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value); 206 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg); 207 s32 ixgbe_dmac_config(struct ixgbe_hw *hw); 208 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw); 209 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw); 210 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee); 211 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 212 unsigned int vf); 213 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, 214 int vf); 215 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 216 u32 device_type, u32 *phy_data); 217 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 218 u32 device_type, u32 phy_data); 219 void ixgbe_disable_mdd(struct ixgbe_hw *hw); 220 void ixgbe_enable_mdd(struct ixgbe_hw *hw); 221 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap); 222 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf); 223 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw); 224 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw); 225 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw); 226 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed); 227 void ixgbe_disable_rx(struct ixgbe_hw *hw); 228 void ixgbe_enable_rx(struct ixgbe_hw *hw); 229 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 230 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 231 232 #endif /* _IXGBE_API_H_ */
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