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sys/dev/ixgbe/ixgbe_phy.c
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1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 ixgbe_clock_in_i2c_byte(hw, byte); 81 /* ACK */ 82 return ixgbe_clock_out_i2c_bit(hw, false); 83 } 84 85 /** 86 * ixgbe_ones_comp_byte_add - Perform one's complement addition 87 * @add1: addend 1 88 * @add2: addend 2 89 * 90 * Returns one's complement 8-bit sum. 91 */ 92 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 93 { 94 u16 sum = add1 + add2; 95 96 sum = (sum & 0xFF) + (sum >> 8); 97 return sum & 0xFF; 98 } 99 100 /** 101 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 102 * @hw: pointer to the hardware structure 103 * @addr: I2C bus address to read from 104 * @reg: I2C device register to read from 105 * @val: pointer to location to receive read value 106 * @lock: true if to take and release semaphore 107 * 108 * Returns an error code on error. 109 */ 110 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 111 u16 *val, bool lock) 112 { 113 u32 swfw_mask = hw->phy.phy_semaphore_mask; 114 int max_retry = 3; 115 int retry = 0; 116 u8 csum_byte; 117 u8 high_bits; 118 u8 low_bits; 119 u8 reg_high; 120 u8 csum; 121 122 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 123 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 124 csum = ~csum; 125 do { 126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 127 return IXGBE_ERR_SWFW_SYNC; 128 ixgbe_i2c_start(hw); 129 /* Device Address and write indication */ 130 if (ixgbe_out_i2c_byte_ack(hw, addr)) 131 goto fail; 132 /* Write bits 14:8 */ 133 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 134 goto fail; 135 /* Write bits 7:0 */ 136 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 137 goto fail; 138 /* Write csum */ 139 if (ixgbe_out_i2c_byte_ack(hw, csum)) 140 goto fail; 141 /* Re-start condition */ 142 ixgbe_i2c_start(hw); 143 /* Device Address and read indication */ 144 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 145 goto fail; 146 /* Get upper bits */ 147 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 148 goto fail; 149 /* Get low bits */ 150 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 151 goto fail; 152 /* Get csum */ 153 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 154 /* NACK */ 155 if (ixgbe_clock_out_i2c_bit(hw, false)) 156 goto fail; 157 ixgbe_i2c_stop(hw); 158 if (lock) 159 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 160 *val = (high_bits << 8) | low_bits; 161 return 0; 162 163 fail: 164 ixgbe_i2c_bus_clear(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 if (retry < max_retry) 168 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 169 else 170 DEBUGOUT("I2C byte read combined error.\n"); 171 retry++; 172 } while (retry <= max_retry); 173 174 return IXGBE_ERR_I2C; 175 } 176 177 /** 178 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 179 * @hw: pointer to the hardware structure 180 * @addr: I2C bus address to write to 181 * @reg: I2C device register to write to 182 * @val: value to write 183 * @lock: true if to take and release semaphore 184 * 185 * Returns an error code on error. 186 */ 187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 188 u16 val, bool lock) 189 { 190 u32 swfw_mask = hw->phy.phy_semaphore_mask; 191 int max_retry = 1; 192 int retry = 0; 193 u8 reg_high; 194 u8 csum; 195 196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 200 csum = ~csum; 201 do { 202 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 203 return IXGBE_ERR_SWFW_SYNC; 204 ixgbe_i2c_start(hw); 205 /* Device Address and write indication */ 206 if (ixgbe_out_i2c_byte_ack(hw, addr)) 207 goto fail; 208 /* Write bits 14:8 */ 209 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 210 goto fail; 211 /* Write bits 7:0 */ 212 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 213 goto fail; 214 /* Write data 15:8 */ 215 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 216 goto fail; 217 /* Write data 7:0 */ 218 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 219 goto fail; 220 /* Write csum */ 221 if (ixgbe_out_i2c_byte_ack(hw, csum)) 222 goto fail; 223 ixgbe_i2c_stop(hw); 224 if (lock) 225 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 226 return 0; 227 228 fail: 229 ixgbe_i2c_bus_clear(hw); 230 if (lock) 231 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 232 if (retry < max_retry) 233 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 234 else 235 DEBUGOUT("I2C byte write combined error.\n"); 236 retry++; 237 } while (retry <= max_retry); 238 239 return IXGBE_ERR_I2C; 240 } 241 242 /** 243 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 244 * @hw: pointer to the hardware structure 245 * 246 * Initialize the function pointers. 247 **/ 248 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 249 { 250 struct ixgbe_phy_info *phy = &hw->phy; 251 252 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 253 254 /* PHY */ 255 phy->ops.identify = ixgbe_identify_phy_generic; 256 phy->ops.reset = ixgbe_reset_phy_generic; 257 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 258 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 259 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 260 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 261 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 262 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 263 phy->ops.check_link = NULL; 264 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 265 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 266 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 267 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 268 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 269 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 270 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 271 phy->ops.identify_sfp = ixgbe_identify_module_generic; 272 phy->sfp_type = ixgbe_sfp_type_unknown; 273 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 274 phy->ops.write_i2c_byte_unlocked = 275 ixgbe_write_i2c_byte_generic_unlocked; 276 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 277 return IXGBE_SUCCESS; 278 } 279 280 /** 281 * ixgbe_probe_phy - Probe a single address for a PHY 282 * @hw: pointer to hardware structure 283 * @phy_addr: PHY address to probe 284 * 285 * Returns true if PHY found 286 */ 287 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 288 { 289 u16 ext_ability = 0; 290 291 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 292 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 293 phy_addr); 294 return false; 295 } 296 297 if (ixgbe_get_phy_id(hw)) 298 return false; 299 300 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 301 302 if (hw->phy.type == ixgbe_phy_unknown) { 303 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 305 if (ext_ability & 306 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 307 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 308 hw->phy.type = ixgbe_phy_cu_unknown; 309 else 310 hw->phy.type = ixgbe_phy_generic; 311 } 312 313 return true; 314 } 315 316 /** 317 * ixgbe_identify_phy_generic - Get physical layer module 318 * @hw: pointer to hardware structure 319 * 320 * Determines the physical layer module found on the current adapter. 321 **/ 322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 323 { 324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 325 u16 phy_addr; 326 327 DEBUGFUNC("ixgbe_identify_phy_generic"); 328 329 if (!hw->phy.phy_semaphore_mask) { 330 if (hw->bus.lan_id) 331 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 332 else 333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 334 } 335 336 if (hw->phy.type != ixgbe_phy_unknown) 337 return IXGBE_SUCCESS; 338 339 if (hw->phy.nw_mng_if_sel) { 340 phy_addr = (hw->phy.nw_mng_if_sel & 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 342 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 343 if (ixgbe_probe_phy(hw, phy_addr)) 344 return IXGBE_SUCCESS; 345 else 346 return IXGBE_ERR_PHY_ADDR_INVALID; 347 } 348 349 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 350 if (ixgbe_probe_phy(hw, phy_addr)) { 351 status = IXGBE_SUCCESS; 352 break; 353 } 354 } 355 356 /* Certain media types do not have a phy so an address will not 357 * be found and the code will take this path. Caller has to 358 * decide if it is an error or not. 359 */ 360 if (status != IXGBE_SUCCESS) 361 hw->phy.addr = 0; 362 363 return status; 364 } 365 366 /** 367 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 368 * @hw: pointer to the hardware structure 369 * 370 * This function checks the MMNGC.MNG_VETO bit to see if there are 371 * any constraints on link from manageability. For MAC's that don't 372 * have this bit just return faluse since the link can not be blocked 373 * via this method. 374 **/ 375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 376 { 377 u32 mmngc; 378 379 DEBUGFUNC("ixgbe_check_reset_blocked"); 380 381 /* If we don't have this bit, it can't be blocking */ 382 if (hw->mac.type == ixgbe_mac_82598EB) 383 return false; 384 385 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 386 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 387 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 388 "MNG_VETO bit detected.\n"); 389 return true; 390 } 391 392 return false; 393 } 394 395 /** 396 * ixgbe_validate_phy_addr - Determines phy address is valid 397 * @hw: pointer to hardware structure 398 * @phy_addr: PHY address 399 * 400 **/ 401 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 402 { 403 u16 phy_id = 0; 404 bool valid = false; 405 406 DEBUGFUNC("ixgbe_validate_phy_addr"); 407 408 hw->phy.addr = phy_addr; 409 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 410 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 411 412 if (phy_id != 0xFFFF && phy_id != 0x0) 413 valid = true; 414 415 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 416 417 return valid; 418 } 419 420 /** 421 * ixgbe_get_phy_id - Get the phy type 422 * @hw: pointer to hardware structure 423 * 424 **/ 425 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 426 { 427 u32 status; 428 u16 phy_id_high = 0; 429 u16 phy_id_low = 0; 430 431 DEBUGFUNC("ixgbe_get_phy_id"); 432 433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 434 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 435 &phy_id_high); 436 437 if (status == IXGBE_SUCCESS) { 438 hw->phy.id = (u32)(phy_id_high << 16); 439 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 440 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 441 &phy_id_low); 442 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 443 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 444 } 445 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 446 phy_id_high, phy_id_low); 447 448 return status; 449 } 450 451 /** 452 * ixgbe_get_phy_type_from_id - Get the phy type 453 * @phy_id: PHY ID information 454 * 455 **/ 456 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 457 { 458 enum ixgbe_phy_type phy_type; 459 460 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 461 462 switch (phy_id) { 463 case TN1010_PHY_ID: 464 phy_type = ixgbe_phy_tn; 465 break; 466 case X550_PHY_ID2: 467 case X550_PHY_ID3: 468 case X540_PHY_ID: 469 phy_type = ixgbe_phy_aq; 470 break; 471 case QT2022_PHY_ID: 472 phy_type = ixgbe_phy_qt; 473 break; 474 case ATH_PHY_ID: 475 phy_type = ixgbe_phy_nl; 476 break; 477 case X557_PHY_ID: 478 case X557_PHY_ID2: 479 phy_type = ixgbe_phy_x550em_ext_t; 480 break; 481 case IXGBE_M88E1500_E_PHY_ID: 482 case IXGBE_M88E1543_E_PHY_ID: 483 phy_type = ixgbe_phy_ext_1g_t; 484 break; 485 default: 486 phy_type = ixgbe_phy_unknown; 487 break; 488 } 489 return phy_type; 490 } 491 492 /** 493 * ixgbe_reset_phy_generic - Performs a PHY reset 494 * @hw: pointer to hardware structure 495 **/ 496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 497 { 498 u32 i; 499 u16 ctrl = 0; 500 s32 status = IXGBE_SUCCESS; 501 502 DEBUGFUNC("ixgbe_reset_phy_generic"); 503 504 if (hw->phy.type == ixgbe_phy_unknown) 505 status = ixgbe_identify_phy_generic(hw); 506 507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 508 goto out; 509 510 /* Don't reset PHY if it's shut down due to overtemp. */ 511 if (!hw->phy.reset_if_overtemp && 512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 513 goto out; 514 515 /* Blocked by MNG FW so bail */ 516 if (ixgbe_check_reset_blocked(hw)) 517 goto out; 518 519 /* 520 * Perform soft PHY reset to the PHY_XS. 521 * This will cause a soft reset to the PHY 522 */ 523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 524 IXGBE_MDIO_PHY_XS_DEV_TYPE, 525 IXGBE_MDIO_PHY_XS_RESET); 526 527 /* 528 * Poll for reset bit to self-clear indicating reset is complete. 529 * Some PHYs could take up to 3 seconds to complete and need about 530 * 1.7 usec delay after the reset is complete. 531 */ 532 for (i = 0; i < 30; i++) { 533 msec_delay(100); 534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 535 status = hw->phy.ops.read_reg(hw, 536 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 537 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 538 &ctrl); 539 if (status != IXGBE_SUCCESS) 540 return status; 541 542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 543 usec_delay(2); 544 break; 545 } 546 } else { 547 status = hw->phy.ops.read_reg(hw, 548 IXGBE_MDIO_PHY_XS_CONTROL, 549 IXGBE_MDIO_PHY_XS_DEV_TYPE, 550 &ctrl); 551 if (status != IXGBE_SUCCESS) 552 return status; 553 554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 555 usec_delay(2); 556 break; 557 } 558 } 559 } 560 561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 562 status = IXGBE_ERR_RESET_FAILED; 563 ERROR_REPORT1(IXGBE_ERROR_POLLING, 564 "PHY reset polling failed to complete.\n"); 565 } 566 567 out: 568 return status; 569 } 570 571 /** 572 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 573 * @hw: pointer to hardware structure 574 **/ 575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 576 { 577 u16 autoneg_reg; 578 579 /* Check if PHY reset is blocked by MNG FW */ 580 if (ixgbe_check_reset_blocked(hw)) 581 return; 582 583 /* Restart PHY auto-negotiation. */ 584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 586 autoneg_reg |= IXGBE_MII_RESTART; 587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 589 } 590 591 /** 592 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 593 * the SWFW lock 594 * @hw: pointer to hardware structure 595 * @reg_addr: 32 bit address of PHY register to read 596 * @device_type: 5 bit device type 597 * @phy_data: Pointer to read data from PHY register 598 **/ 599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 600 u16 *phy_data) 601 { 602 u32 i, data, command; 603 604 /* Setup and write the address cycle command */ 605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 609 610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 611 612 /* 613 * Check every 10 usec to see if the address cycle completed. 614 * The MDI Command bit will clear when the operation is 615 * complete 616 */ 617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 618 usec_delay(10); 619 620 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 622 break; 623 } 624 625 626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 629 return IXGBE_ERR_PHY; 630 } 631 632 /* 633 * Address cycle complete, setup and write the read 634 * command 635 */ 636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 640 641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 642 643 /* 644 * Check every 10 usec to see if the address cycle 645 * completed. The MDI Command bit will clear when the 646 * operation is complete 647 */ 648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 649 usec_delay(10); 650 651 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 653 break; 654 } 655 656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 659 return IXGBE_ERR_PHY; 660 } 661 662 /* 663 * Read operation is complete. Get the data 664 * from MSRWD 665 */ 666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 668 *phy_data = (u16)(data); 669 670 return IXGBE_SUCCESS; 671 } 672 673 /** 674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 675 * using the SWFW lock - this function is needed in most cases 676 * @hw: pointer to hardware structure 677 * @reg_addr: 32 bit address of PHY register to read 678 * @device_type: 5 bit device type 679 * @phy_data: Pointer to read data from PHY register 680 **/ 681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 682 u32 device_type, u16 *phy_data) 683 { 684 s32 status; 685 u32 gssr = hw->phy.phy_semaphore_mask; 686 687 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 688 689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 690 return IXGBE_ERR_SWFW_SYNC; 691 692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 693 694 hw->mac.ops.release_swfw_sync(hw, gssr); 695 696 return status; 697 } 698 699 /** 700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 701 * without SWFW lock 702 * @hw: pointer to hardware structure 703 * @reg_addr: 32 bit PHY register to write 704 * @device_type: 5 bit device type 705 * @phy_data: Data to write to the PHY register 706 **/ 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 708 u32 device_type, u16 phy_data) 709 { 710 u32 i, command; 711 712 /* Put the data in the MDI single read and write data register*/ 713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 714 715 /* Setup and write the address cycle command */ 716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 720 721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 722 723 /* 724 * Check every 10 usec to see if the address cycle completed. 725 * The MDI Command bit will clear when the operation is 726 * complete 727 */ 728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 729 usec_delay(10); 730 731 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 733 break; 734 } 735 736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 738 return IXGBE_ERR_PHY; 739 } 740 741 /* 742 * Address cycle complete, setup and write the write 743 * command 744 */ 745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 749 750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 751 752 /* 753 * Check every 10 usec to see if the address cycle 754 * completed. The MDI Command bit will clear when the 755 * operation is complete 756 */ 757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 758 usec_delay(10); 759 760 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 762 break; 763 } 764 765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 767 return IXGBE_ERR_PHY; 768 } 769 770 return IXGBE_SUCCESS; 771 } 772 773 /** 774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 775 * using SWFW lock- this function is needed in most cases 776 * @hw: pointer to hardware structure 777 * @reg_addr: 32 bit PHY register to write 778 * @device_type: 5 bit device type 779 * @phy_data: Data to write to the PHY register 780 **/ 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 782 u32 device_type, u16 phy_data) 783 { 784 s32 status; 785 u32 gssr = hw->phy.phy_semaphore_mask; 786 787 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 788 789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 791 phy_data); 792 hw->mac.ops.release_swfw_sync(hw, gssr); 793 } else { 794 status = IXGBE_ERR_SWFW_SYNC; 795 } 796 797 return status; 798 } 799 800 /** 801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 802 * @hw: pointer to hardware structure 803 * 804 * Restart auto-negotiation and PHY and waits for completion. 805 **/ 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 807 { 808 s32 status = IXGBE_SUCCESS; 809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 810 bool autoneg = false; 811 ixgbe_link_speed speed; 812 813 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 814 815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 816 817 /* Set or unset auto-negotiation 10G advertisement */ 818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 820 &autoneg_reg); 821 822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 824 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 826 827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 829 autoneg_reg); 830 831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 833 &autoneg_reg); 834 835 if (hw->mac.type == ixgbe_mac_X550) { 836 /* Set or unset auto-negotiation 5G advertisement */ 837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 839 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 841 842 /* Set or unset auto-negotiation 2.5G advertisement */ 843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 844 if ((hw->phy.autoneg_advertised & 845 IXGBE_LINK_SPEED_2_5GB_FULL) && 846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 848 } 849 850 /* Set or unset auto-negotiation 1G advertisement */ 851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 853 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 855 856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 autoneg_reg); 859 860 /* Set or unset auto-negotiation 100M advertisement */ 861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 863 &autoneg_reg); 864 865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 866 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 868 (speed & IXGBE_LINK_SPEED_100_FULL)) 869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 870 871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 873 autoneg_reg); 874 875 ixgbe_restart_auto_neg(hw); 876 return status; 877 } 878 879 /** 880 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 881 * @hw: pointer to hardware structure 882 * @speed: new link speed 883 * @autoneg_wait_to_complete: unused 884 **/ 885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 886 ixgbe_link_speed speed, 887 bool autoneg_wait_to_complete) 888 { 889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 890 891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 892 893 /* 894 * Clear autoneg_advertised and set new values based on input link 895 * speed. 896 */ 897 hw->phy.autoneg_advertised = 0; 898 899 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 901 902 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 904 905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 907 908 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 910 911 if (speed & IXGBE_LINK_SPEED_100_FULL) 912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 913 914 if (speed & IXGBE_LINK_SPEED_10_FULL) 915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 916 917 /* Setup link based on the new speed settings */ 918 ixgbe_setup_phy_link(hw); 919 920 return IXGBE_SUCCESS; 921 } 922 923 /** 924 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 925 * @hw: pointer to hardware structure 926 * 927 * Determines the supported link capabilities by reading the PHY auto 928 * negotiation register. 929 **/ 930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 931 { 932 s32 status; 933 u16 speed_ability; 934 935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 936 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 937 &speed_ability); 938 if (status) 939 return status; 940 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 947 948 switch (hw->mac.type) { 949 case ixgbe_mac_X550: 950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 952 break; 953 case ixgbe_mac_X550EM_x: 954 case ixgbe_mac_X550EM_a: 955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 956 break; 957 default: 958 break; 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 966 * @hw: pointer to hardware structure 967 * @speed: pointer to link speed 968 * @autoneg: boolean auto-negotiation value 969 **/ 970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 971 ixgbe_link_speed *speed, 972 bool *autoneg) 973 { 974 s32 status = IXGBE_SUCCESS; 975 976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 977 978 *autoneg = true; 979 if (!hw->phy.speeds_supported) 980 status = ixgbe_get_copper_speeds_supported(hw); 981 982 *speed = hw->phy.speeds_supported; 983 return status; 984 } 985 986 /** 987 * ixgbe_check_phy_link_tnx - Determine link and speed status 988 * @hw: pointer to hardware structure 989 * @speed: current link speed 990 * @link_up: true is link is up, false otherwise 991 * 992 * Reads the VS1 register to determine if link is up and the current speed for 993 * the PHY. 994 **/ 995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 996 bool *link_up) 997 { 998 s32 status = IXGBE_SUCCESS; 999 u32 time_out; 1000 u32 max_time_out = 10; 1001 u16 phy_link = 0; 1002 u16 phy_speed = 0; 1003 u16 phy_data = 0; 1004 1005 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1006 1007 /* Initialize speed and link to default case */ 1008 *link_up = false; 1009 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1010 1011 /* 1012 * Check current speed and link status of the PHY register. 1013 * This is a vendor specific register and may have to 1014 * be changed for other copper PHYs. 1015 */ 1016 for (time_out = 0; time_out < max_time_out; time_out++) { 1017 usec_delay(10); 1018 status = hw->phy.ops.read_reg(hw, 1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1021 &phy_data); 1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1023 phy_speed = phy_data & 1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1026 *link_up = true; 1027 if (phy_speed == 1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1029 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1030 break; 1031 } 1032 } 1033 1034 return status; 1035 } 1036 1037 /** 1038 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1039 * @hw: pointer to hardware structure 1040 * 1041 * Restart auto-negotiation and PHY and waits for completion. 1042 **/ 1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1044 { 1045 s32 status = IXGBE_SUCCESS; 1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1047 bool autoneg = false; 1048 ixgbe_link_speed speed; 1049 1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1051 1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1053 1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1055 /* Set or unset auto-negotiation 10G advertisement */ 1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1058 &autoneg_reg); 1059 1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1063 1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1066 autoneg_reg); 1067 } 1068 1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1070 /* Set or unset auto-negotiation 1G advertisement */ 1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1073 &autoneg_reg); 1074 1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1078 1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1081 autoneg_reg); 1082 } 1083 1084 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1085 /* Set or unset auto-negotiation 100M advertisement */ 1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 &autoneg_reg); 1089 1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1093 1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1096 autoneg_reg); 1097 } 1098 1099 ixgbe_restart_auto_neg(hw); 1100 return status; 1101 } 1102 1103 /** 1104 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1105 * @hw: pointer to hardware structure 1106 * @firmware_version: pointer to the PHY Firmware Version 1107 **/ 1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1109 u16 *firmware_version) 1110 { 1111 s32 status; 1112 1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1114 1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1117 firmware_version); 1118 1119 return status; 1120 } 1121 1122 /** 1123 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1124 * @hw: pointer to hardware structure 1125 * @firmware_version: pointer to the PHY Firmware Version 1126 **/ 1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1128 u16 *firmware_version) 1129 { 1130 s32 status; 1131 1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1133 1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1136 firmware_version); 1137 1138 return status; 1139 } 1140 1141 /** 1142 * ixgbe_reset_phy_nl - Performs a PHY reset 1143 * @hw: pointer to hardware structure 1144 **/ 1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1146 { 1147 u16 phy_offset, control, eword, edata, block_crc; 1148 bool end_data = false; 1149 u16 list_offset, data_offset; 1150 u16 phy_data = 0; 1151 s32 ret_val = IXGBE_SUCCESS; 1152 u32 i; 1153 1154 DEBUGFUNC("ixgbe_reset_phy_nl"); 1155 1156 /* Blocked by MNG FW so bail */ 1157 if (ixgbe_check_reset_blocked(hw)) 1158 goto out; 1159 1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1162 1163 /* reset the PHY and poll for completion */ 1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1165 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1167 1168 for (i = 0; i < 100; i++) { 1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1172 break; 1173 msec_delay(10); 1174 } 1175 1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1177 DEBUGOUT("PHY reset did not complete.\n"); 1178 ret_val = IXGBE_ERR_PHY; 1179 goto out; 1180 } 1181 1182 /* Get init offsets */ 1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1184 &data_offset); 1185 if (ret_val != IXGBE_SUCCESS) 1186 goto out; 1187 1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1189 data_offset++; 1190 while (!end_data) { 1191 /* 1192 * Read control word from PHY init contents offset 1193 */ 1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1195 if (ret_val) 1196 goto err_eeprom; 1197 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1198 IXGBE_CONTROL_SHIFT_NL; 1199 edata = eword & IXGBE_DATA_MASK_NL; 1200 switch (control) { 1201 case IXGBE_DELAY_NL: 1202 data_offset++; 1203 DEBUGOUT1("DELAY: %d MS\n", edata); 1204 msec_delay(edata); 1205 break; 1206 case IXGBE_DATA_NL: 1207 DEBUGOUT("DATA:\n"); 1208 data_offset++; 1209 ret_val = hw->eeprom.ops.read(hw, data_offset, 1210 &phy_offset); 1211 if (ret_val) 1212 goto err_eeprom; 1213 data_offset++; 1214 for (i = 0; i < edata; i++) { 1215 ret_val = hw->eeprom.ops.read(hw, data_offset, 1216 &eword); 1217 if (ret_val) 1218 goto err_eeprom; 1219 hw->phy.ops.write_reg(hw, phy_offset, 1220 IXGBE_TWINAX_DEV, eword); 1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1222 phy_offset); 1223 data_offset++; 1224 phy_offset++; 1225 } 1226 break; 1227 case IXGBE_CONTROL_NL: 1228 data_offset++; 1229 DEBUGOUT("CONTROL:\n"); 1230 if (edata == IXGBE_CONTROL_EOL_NL) { 1231 DEBUGOUT("EOL\n"); 1232 end_data = true; 1233 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1234 DEBUGOUT("SOL\n"); 1235 } else { 1236 DEBUGOUT("Bad control value\n"); 1237 ret_val = IXGBE_ERR_PHY; 1238 goto out; 1239 } 1240 break; 1241 default: 1242 DEBUGOUT("Bad control type\n"); 1243 ret_val = IXGBE_ERR_PHY; 1244 goto out; 1245 } 1246 } 1247 1248 out: 1249 return ret_val; 1250 1251 err_eeprom: 1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1253 "eeprom read at offset %d failed", data_offset); 1254 return IXGBE_ERR_PHY; 1255 } 1256 1257 /** 1258 * ixgbe_identify_module_generic - Identifies module type 1259 * @hw: pointer to hardware structure 1260 * 1261 * Determines HW type and calls appropriate function. 1262 **/ 1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1264 { 1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1266 1267 DEBUGFUNC("ixgbe_identify_module_generic"); 1268 1269 switch (hw->mac.ops.get_media_type(hw)) { 1270 case ixgbe_media_type_fiber: 1271 status = ixgbe_identify_sfp_module_generic(hw); 1272 break; 1273 1274 case ixgbe_media_type_fiber_qsfp: 1275 status = ixgbe_identify_qsfp_module_generic(hw); 1276 break; 1277 1278 default: 1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1280 status = IXGBE_ERR_SFP_NOT_PRESENT; 1281 break; 1282 } 1283 1284 return status; 1285 } 1286 1287 /** 1288 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1289 * @hw: pointer to hardware structure 1290 * 1291 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1292 **/ 1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1294 { 1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1296 u32 vendor_oui = 0; 1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1298 u8 identifier = 0; 1299 u8 comp_codes_1g = 0; 1300 u8 comp_codes_10g = 0; 1301 u8 oui_bytes[3] = {0, 0, 0}; 1302 u8 cable_tech = 0; 1303 u8 cable_spec = 0; 1304 u16 enforce_sfp = 0; 1305 1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1307 1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1310 status = IXGBE_ERR_SFP_NOT_PRESENT; 1311 goto out; 1312 } 1313 1314 /* LAN ID is needed for I2C access */ 1315 hw->mac.ops.set_lan_id(hw); 1316 1317 status = hw->phy.ops.read_i2c_eeprom(hw, 1318 IXGBE_SFF_IDENTIFIER, 1319 &identifier); 1320 1321 if (status != IXGBE_SUCCESS) 1322 goto err_read_i2c_eeprom; 1323 1324 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1325 hw->phy.type = ixgbe_phy_sfp_unsupported; 1326 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1327 } else { 1328 status = hw->phy.ops.read_i2c_eeprom(hw, 1329 IXGBE_SFF_1GBE_COMP_CODES, 1330 &comp_codes_1g); 1331 1332 if (status != IXGBE_SUCCESS) 1333 goto err_read_i2c_eeprom; 1334 1335 status = hw->phy.ops.read_i2c_eeprom(hw, 1336 IXGBE_SFF_10GBE_COMP_CODES, 1337 &comp_codes_10g); 1338 1339 if (status != IXGBE_SUCCESS) 1340 goto err_read_i2c_eeprom; 1341 status = hw->phy.ops.read_i2c_eeprom(hw, 1342 IXGBE_SFF_CABLE_TECHNOLOGY, 1343 &cable_tech); 1344 1345 if (status != IXGBE_SUCCESS) 1346 goto err_read_i2c_eeprom; 1347 1348 /* ID Module 1349 * ========= 1350 * 0 SFP_DA_CU 1351 * 1 SFP_SR 1352 * 2 SFP_LR 1353 * 3 SFP_DA_CORE0 - 82599-specific 1354 * 4 SFP_DA_CORE1 - 82599-specific 1355 * 5 SFP_SR/LR_CORE0 - 82599-specific 1356 * 6 SFP_SR/LR_CORE1 - 82599-specific 1357 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1358 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1359 * 9 SFP_1g_cu_CORE0 - 82599-specific 1360 * 10 SFP_1g_cu_CORE1 - 82599-specific 1361 * 11 SFP_1g_sx_CORE0 - 82599-specific 1362 * 12 SFP_1g_sx_CORE1 - 82599-specific 1363 */ 1364 if (hw->mac.type == ixgbe_mac_82598EB) { 1365 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1366 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1367 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1368 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1369 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1370 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1371 else 1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1373 } else { 1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1375 if (hw->bus.lan_id == 0) 1376 hw->phy.sfp_type = 1377 ixgbe_sfp_type_da_cu_core0; 1378 else 1379 hw->phy.sfp_type = 1380 ixgbe_sfp_type_da_cu_core1; 1381 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1382 hw->phy.ops.read_i2c_eeprom( 1383 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1384 &cable_spec); 1385 if (cable_spec & 1386 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1387 if (hw->bus.lan_id == 0) 1388 hw->phy.sfp_type = 1389 ixgbe_sfp_type_da_act_lmt_core0; 1390 else 1391 hw->phy.sfp_type = 1392 ixgbe_sfp_type_da_act_lmt_core1; 1393 } else { 1394 hw->phy.sfp_type = 1395 ixgbe_sfp_type_unknown; 1396 } 1397 } else if (comp_codes_10g & 1398 (IXGBE_SFF_10GBASESR_CAPABLE | 1399 IXGBE_SFF_10GBASELR_CAPABLE)) { 1400 if (hw->bus.lan_id == 0) 1401 hw->phy.sfp_type = 1402 ixgbe_sfp_type_srlr_core0; 1403 else 1404 hw->phy.sfp_type = 1405 ixgbe_sfp_type_srlr_core1; 1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1407 if (hw->bus.lan_id == 0) 1408 hw->phy.sfp_type = 1409 ixgbe_sfp_type_1g_cu_core0; 1410 else 1411 hw->phy.sfp_type = 1412 ixgbe_sfp_type_1g_cu_core1; 1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1414 if (hw->bus.lan_id == 0) 1415 hw->phy.sfp_type = 1416 ixgbe_sfp_type_1g_sx_core0; 1417 else 1418 hw->phy.sfp_type = 1419 ixgbe_sfp_type_1g_sx_core1; 1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_1g_lx_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_1g_lx_core1; 1427 } else { 1428 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1429 } 1430 } 1431 1432 if (hw->phy.sfp_type != stored_sfp_type) 1433 hw->phy.sfp_setup_needed = true; 1434 1435 /* Determine if the SFP+ PHY is dual speed or not. */ 1436 hw->phy.multispeed_fiber = false; 1437 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1438 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1439 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1440 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1441 hw->phy.multispeed_fiber = true; 1442 1443 /* Determine PHY vendor */ 1444 if (hw->phy.type != ixgbe_phy_nl) { 1445 hw->phy.id = identifier; 1446 status = hw->phy.ops.read_i2c_eeprom(hw, 1447 IXGBE_SFF_VENDOR_OUI_BYTE0, 1448 &oui_bytes[0]); 1449 1450 if (status != IXGBE_SUCCESS) 1451 goto err_read_i2c_eeprom; 1452 1453 status = hw->phy.ops.read_i2c_eeprom(hw, 1454 IXGBE_SFF_VENDOR_OUI_BYTE1, 1455 &oui_bytes[1]); 1456 1457 if (status != IXGBE_SUCCESS) 1458 goto err_read_i2c_eeprom; 1459 1460 status = hw->phy.ops.read_i2c_eeprom(hw, 1461 IXGBE_SFF_VENDOR_OUI_BYTE2, 1462 &oui_bytes[2]); 1463 1464 if (status != IXGBE_SUCCESS) 1465 goto err_read_i2c_eeprom; 1466 1467 vendor_oui = 1468 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1469 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1470 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1471 1472 switch (vendor_oui) { 1473 case IXGBE_SFF_VENDOR_OUI_TYCO: 1474 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1475 hw->phy.type = 1476 ixgbe_phy_sfp_passive_tyco; 1477 break; 1478 case IXGBE_SFF_VENDOR_OUI_FTL: 1479 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1480 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1481 else 1482 hw->phy.type = ixgbe_phy_sfp_ftl; 1483 break; 1484 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1485 hw->phy.type = ixgbe_phy_sfp_avago; 1486 break; 1487 case IXGBE_SFF_VENDOR_OUI_INTEL: 1488 hw->phy.type = ixgbe_phy_sfp_intel; 1489 break; 1490 default: 1491 hw->phy.type = ixgbe_phy_sfp_unknown; 1492 break; 1493 } 1494 } 1495 1496 /* Allow any DA cable vendor */ 1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1498 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1502 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1503 status = IXGBE_SUCCESS; 1504 goto out; 1505 } 1506 1507 /* Verify supported 1G SFP modules */ 1508 if (comp_codes_10g == 0 && 1509 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1515 hw->phy.type = ixgbe_phy_sfp_unsupported; 1516 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1517 goto out; 1518 } 1519 1520 /* Anything else 82598-based is supported */ 1521 if (hw->mac.type == ixgbe_mac_82598EB) { 1522 status = IXGBE_SUCCESS; 1523 goto out; 1524 } 1525 1526 ixgbe_get_device_caps(hw, &enforce_sfp); 1527 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1528 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1534 /* Make sure we're a supported PHY type */ 1535 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1536 status = IXGBE_SUCCESS; 1537 } else { 1538 if (hw->allow_unsupported_sfp == true) { 1539 EWARN(hw, 1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1543 status = IXGBE_SUCCESS; 1544 } else { 1545 DEBUGOUT("SFP+ module not supported\n"); 1546 hw->phy.type = 1547 ixgbe_phy_sfp_unsupported; 1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1549 } 1550 } 1551 } else { 1552 status = IXGBE_SUCCESS; 1553 } 1554 } 1555 1556 out: 1557 return status; 1558 1559 err_read_i2c_eeprom: 1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1561 if (hw->phy.type != ixgbe_phy_nl) { 1562 hw->phy.id = 0; 1563 hw->phy.type = ixgbe_phy_unknown; 1564 } 1565 return IXGBE_ERR_SFP_NOT_PRESENT; 1566 } 1567 1568 /** 1569 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1570 * @hw: pointer to hardware structure 1571 * 1572 * Determines physical layer capabilities of the current SFP. 1573 */ 1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1575 { 1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1577 u8 comp_codes_10g = 0; 1578 u8 comp_codes_1g = 0; 1579 1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1581 1582 hw->phy.ops.identify_sfp(hw); 1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1584 return physical_layer; 1585 1586 switch (hw->phy.type) { 1587 case ixgbe_phy_sfp_passive_tyco: 1588 case ixgbe_phy_sfp_passive_unknown: 1589 case ixgbe_phy_qsfp_passive_unknown: 1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1591 break; 1592 case ixgbe_phy_sfp_ftl_active: 1593 case ixgbe_phy_sfp_active_unknown: 1594 case ixgbe_phy_qsfp_active_unknown: 1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1596 break; 1597 case ixgbe_phy_sfp_avago: 1598 case ixgbe_phy_sfp_ftl: 1599 case ixgbe_phy_sfp_intel: 1600 case ixgbe_phy_sfp_unknown: 1601 hw->phy.ops.read_i2c_eeprom(hw, 1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1603 hw->phy.ops.read_i2c_eeprom(hw, 1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1613 break; 1614 case ixgbe_phy_qsfp_intel: 1615 case ixgbe_phy_qsfp_unknown: 1616 hw->phy.ops.read_i2c_eeprom(hw, 1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 return physical_layer; 1628 } 1629 1630 /** 1631 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1632 * @hw: pointer to hardware structure 1633 * 1634 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1635 **/ 1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1637 { 1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1639 u32 vendor_oui = 0; 1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1641 u8 identifier = 0; 1642 u8 comp_codes_1g = 0; 1643 u8 comp_codes_10g = 0; 1644 u8 oui_bytes[3] = {0, 0, 0}; 1645 u16 enforce_sfp = 0; 1646 u8 connector = 0; 1647 u8 cable_length = 0; 1648 u8 device_tech = 0; 1649 bool active_cable = false; 1650 1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1652 1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1655 status = IXGBE_ERR_SFP_NOT_PRESENT; 1656 goto out; 1657 } 1658 1659 /* LAN ID is needed for I2C access */ 1660 hw->mac.ops.set_lan_id(hw); 1661 1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1663 &identifier); 1664 1665 if (status != IXGBE_SUCCESS) 1666 goto err_read_i2c_eeprom; 1667 1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1669 hw->phy.type = ixgbe_phy_sfp_unsupported; 1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1671 goto out; 1672 } 1673 1674 hw->phy.id = identifier; 1675 1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1677 &comp_codes_10g); 1678 1679 if (status != IXGBE_SUCCESS) 1680 goto err_read_i2c_eeprom; 1681 1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1683 &comp_codes_1g); 1684 1685 if (status != IXGBE_SUCCESS) 1686 goto err_read_i2c_eeprom; 1687 1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1690 if (hw->bus.lan_id == 0) 1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1692 else 1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1695 IXGBE_SFF_10GBASELR_CAPABLE)) { 1696 if (hw->bus.lan_id == 0) 1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1698 else 1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1700 } else { 1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1702 active_cable = true; 1703 1704 if (!active_cable) { 1705 /* check for active DA cables that pre-date 1706 * SFF-8436 v3.6 */ 1707 hw->phy.ops.read_i2c_eeprom(hw, 1708 IXGBE_SFF_QSFP_CONNECTOR, 1709 &connector); 1710 1711 hw->phy.ops.read_i2c_eeprom(hw, 1712 IXGBE_SFF_QSFP_CABLE_LENGTH, 1713 &cable_length); 1714 1715 hw->phy.ops.read_i2c_eeprom(hw, 1716 IXGBE_SFF_QSFP_DEVICE_TECH, 1717 &device_tech); 1718 1719 if ((connector == 1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1721 (cable_length > 0) && 1722 ((device_tech >> 4) == 1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1724 active_cable = true; 1725 } 1726 1727 if (active_cable) { 1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1729 if (hw->bus.lan_id == 0) 1730 hw->phy.sfp_type = 1731 ixgbe_sfp_type_da_act_lmt_core0; 1732 else 1733 hw->phy.sfp_type = 1734 ixgbe_sfp_type_da_act_lmt_core1; 1735 } else { 1736 /* unsupported module type */ 1737 hw->phy.type = ixgbe_phy_sfp_unsupported; 1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1739 goto out; 1740 } 1741 } 1742 1743 if (hw->phy.sfp_type != stored_sfp_type) 1744 hw->phy.sfp_setup_needed = true; 1745 1746 /* Determine if the QSFP+ PHY is dual speed or not. */ 1747 hw->phy.multispeed_fiber = false; 1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1752 hw->phy.multispeed_fiber = true; 1753 1754 /* Determine PHY vendor for optical modules */ 1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1756 IXGBE_SFF_10GBASELR_CAPABLE)) { 1757 status = hw->phy.ops.read_i2c_eeprom(hw, 1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1759 &oui_bytes[0]); 1760 1761 if (status != IXGBE_SUCCESS) 1762 goto err_read_i2c_eeprom; 1763 1764 status = hw->phy.ops.read_i2c_eeprom(hw, 1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1766 &oui_bytes[1]); 1767 1768 if (status != IXGBE_SUCCESS) 1769 goto err_read_i2c_eeprom; 1770 1771 status = hw->phy.ops.read_i2c_eeprom(hw, 1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1773 &oui_bytes[2]); 1774 1775 if (status != IXGBE_SUCCESS) 1776 goto err_read_i2c_eeprom; 1777 1778 vendor_oui = 1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1782 1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1784 hw->phy.type = ixgbe_phy_qsfp_intel; 1785 else 1786 hw->phy.type = ixgbe_phy_qsfp_unknown; 1787 1788 ixgbe_get_device_caps(hw, &enforce_sfp); 1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1790 /* Make sure we're a supported PHY type */ 1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1792 status = IXGBE_SUCCESS; 1793 } else { 1794 if (hw->allow_unsupported_sfp == true) { 1795 EWARN(hw, 1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1799 status = IXGBE_SUCCESS; 1800 } else { 1801 DEBUGOUT("QSFP module not supported\n"); 1802 hw->phy.type = 1803 ixgbe_phy_sfp_unsupported; 1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1805 } 1806 } 1807 } else { 1808 status = IXGBE_SUCCESS; 1809 } 1810 } 1811 1812 out: 1813 return status; 1814 1815 err_read_i2c_eeprom: 1816 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1817 hw->phy.id = 0; 1818 hw->phy.type = ixgbe_phy_unknown; 1819 1820 return IXGBE_ERR_SFP_NOT_PRESENT; 1821 } 1822 1823 /** 1824 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1825 * @hw: pointer to hardware structure 1826 * @list_offset: offset to the SFP ID list 1827 * @data_offset: offset to the SFP data block 1828 * 1829 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1830 * so it returns the offsets to the phy init sequence block. 1831 **/ 1832 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1833 u16 *list_offset, 1834 u16 *data_offset) 1835 { 1836 u16 sfp_id; 1837 u16 sfp_type = hw->phy.sfp_type; 1838 1839 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1840 1841 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1842 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1843 1844 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1845 return IXGBE_ERR_SFP_NOT_PRESENT; 1846 1847 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1848 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1849 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1850 1851 /* 1852 * Limiting active cables and 1G Phys must be initialized as 1853 * SR modules 1854 */ 1855 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1856 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1857 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1858 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1859 sfp_type = ixgbe_sfp_type_srlr_core0; 1860 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1861 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1862 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1863 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1864 sfp_type = ixgbe_sfp_type_srlr_core1; 1865 1866 /* Read offset to PHY init contents */ 1867 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1868 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1869 "eeprom read at offset %d failed", 1870 IXGBE_PHY_INIT_OFFSET_NL); 1871 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1872 } 1873 1874 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1875 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1876 1877 /* Shift offset to first ID word */ 1878 (*list_offset)++; 1879 1880 /* 1881 * Find the matching SFP ID in the EEPROM 1882 * and program the init sequence 1883 */ 1884 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1885 goto err_phy; 1886 1887 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1888 if (sfp_id == sfp_type) { 1889 (*list_offset)++; 1890 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1891 goto err_phy; 1892 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1893 DEBUGOUT("SFP+ module not supported\n"); 1894 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1895 } else { 1896 break; 1897 } 1898 } else { 1899 (*list_offset) += 2; 1900 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1901 goto err_phy; 1902 } 1903 } 1904 1905 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1906 DEBUGOUT("No matching SFP+ module found\n"); 1907 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1908 } 1909 1910 return IXGBE_SUCCESS; 1911 1912 err_phy: 1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1914 "eeprom read at offset %d failed", *list_offset); 1915 return IXGBE_ERR_PHY; 1916 } 1917 1918 /** 1919 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1920 * @hw: pointer to hardware structure 1921 * @byte_offset: EEPROM byte offset to read 1922 * @eeprom_data: value read 1923 * 1924 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1925 **/ 1926 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1927 u8 *eeprom_data) 1928 { 1929 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1930 1931 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1932 IXGBE_I2C_EEPROM_DEV_ADDR, 1933 eeprom_data); 1934 } 1935 1936 /** 1937 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1938 * @hw: pointer to hardware structure 1939 * @byte_offset: byte offset at address 0xA2 1940 * @sff8472_data: value read 1941 * 1942 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1943 **/ 1944 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1945 u8 *sff8472_data) 1946 { 1947 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1948 IXGBE_I2C_EEPROM_DEV_ADDR2, 1949 sff8472_data); 1950 } 1951 1952 /** 1953 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1954 * @hw: pointer to hardware structure 1955 * @byte_offset: EEPROM byte offset to write 1956 * @eeprom_data: value to write 1957 * 1958 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1959 **/ 1960 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1961 u8 eeprom_data) 1962 { 1963 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1964 1965 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1966 IXGBE_I2C_EEPROM_DEV_ADDR, 1967 eeprom_data); 1968 } 1969 1970 /** 1971 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1972 * @hw: pointer to hardware structure 1973 * @offset: eeprom offset to be read 1974 * @addr: I2C address to be read 1975 */ 1976 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1977 { 1978 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1979 offset == IXGBE_SFF_IDENTIFIER && 1980 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1981 return true; 1982 return false; 1983 } 1984 1985 /** 1986 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1987 * @hw: pointer to hardware structure 1988 * @byte_offset: byte offset to read 1989 * @dev_addr: address to read from 1990 * @data: value read 1991 * @lock: true if to take and release semaphore 1992 * 1993 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1994 * a specified device address. 1995 **/ 1996 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1997 u8 dev_addr, u8 *data, bool lock) 1998 { 1999 s32 status; 2000 u32 max_retry = 10; 2001 u32 retry = 0; 2002 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2003 bool nack = 1; 2004 *data = 0; 2005 2006 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2007 2008 if (hw->mac.type >= ixgbe_mac_X550) 2009 max_retry = 3; 2010 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2011 max_retry = IXGBE_SFP_DETECT_RETRIES; 2012 2013 do { 2014 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2015 return IXGBE_ERR_SWFW_SYNC; 2016 2017 ixgbe_i2c_start(hw); 2018 2019 /* Device Address and write indication */ 2020 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2021 if (status != IXGBE_SUCCESS) 2022 goto fail; 2023 2024 status = ixgbe_get_i2c_ack(hw); 2025 if (status != IXGBE_SUCCESS) 2026 goto fail; 2027 2028 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2029 if (status != IXGBE_SUCCESS) 2030 goto fail; 2031 2032 status = ixgbe_get_i2c_ack(hw); 2033 if (status != IXGBE_SUCCESS) 2034 goto fail; 2035 2036 ixgbe_i2c_start(hw); 2037 2038 /* Device Address and read indication */ 2039 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2040 if (status != IXGBE_SUCCESS) 2041 goto fail; 2042 2043 status = ixgbe_get_i2c_ack(hw); 2044 if (status != IXGBE_SUCCESS) 2045 goto fail; 2046 2047 ixgbe_clock_in_i2c_byte(hw, data); 2048 2049 status = ixgbe_clock_out_i2c_bit(hw, nack); 2050 if (status != IXGBE_SUCCESS) 2051 goto fail; 2052 2053 ixgbe_i2c_stop(hw); 2054 if (lock) 2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2056 return IXGBE_SUCCESS; 2057 2058 fail: 2059 ixgbe_i2c_bus_clear(hw); 2060 if (lock) { 2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2062 msec_delay(100); 2063 } 2064 if (retry < max_retry) 2065 DEBUGOUT("I2C byte read error - Retrying.\n"); 2066 else 2067 DEBUGOUT("I2C byte read error.\n"); 2068 retry++; 2069 } while (retry <= max_retry); 2070 2071 return status; 2072 } 2073 2074 /** 2075 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2076 * @hw: pointer to hardware structure 2077 * @byte_offset: byte offset to read 2078 * @dev_addr: address to read from 2079 * @data: value read 2080 * 2081 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2082 * a specified device address. 2083 **/ 2084 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2085 u8 dev_addr, u8 *data) 2086 { 2087 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2088 data, true); 2089 } 2090 2091 /** 2092 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2093 * @hw: pointer to hardware structure 2094 * @byte_offset: byte offset to read 2095 * @dev_addr: address to read from 2096 * @data: value read 2097 * 2098 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2099 * a specified device address. 2100 **/ 2101 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2102 u8 dev_addr, u8 *data) 2103 { 2104 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2105 data, false); 2106 } 2107 2108 /** 2109 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2110 * @hw: pointer to hardware structure 2111 * @byte_offset: byte offset to write 2112 * @dev_addr: address to write to 2113 * @data: value to write 2114 * @lock: true if to take and release semaphore 2115 * 2116 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2117 * a specified device address. 2118 **/ 2119 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2120 u8 dev_addr, u8 data, bool lock) 2121 { 2122 s32 status; 2123 u32 max_retry = 1; 2124 u32 retry = 0; 2125 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2126 2127 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2128 2129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2130 IXGBE_SUCCESS) 2131 return IXGBE_ERR_SWFW_SYNC; 2132 2133 do { 2134 ixgbe_i2c_start(hw); 2135 2136 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2137 if (status != IXGBE_SUCCESS) 2138 goto fail; 2139 2140 status = ixgbe_get_i2c_ack(hw); 2141 if (status != IXGBE_SUCCESS) 2142 goto fail; 2143 2144 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2145 if (status != IXGBE_SUCCESS) 2146 goto fail; 2147 2148 status = ixgbe_get_i2c_ack(hw); 2149 if (status != IXGBE_SUCCESS) 2150 goto fail; 2151 2152 status = ixgbe_clock_out_i2c_byte(hw, data); 2153 if (status != IXGBE_SUCCESS) 2154 goto fail; 2155 2156 status = ixgbe_get_i2c_ack(hw); 2157 if (status != IXGBE_SUCCESS) 2158 goto fail; 2159 2160 ixgbe_i2c_stop(hw); 2161 if (lock) 2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2163 return IXGBE_SUCCESS; 2164 2165 fail: 2166 ixgbe_i2c_bus_clear(hw); 2167 if (retry < max_retry) 2168 DEBUGOUT("I2C byte write error - Retrying.\n"); 2169 else 2170 DEBUGOUT("I2C byte write error.\n"); 2171 retry++; 2172 } while (retry <= max_retry); 2173 2174 if (lock) 2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2176 2177 return status; 2178 } 2179 2180 /** 2181 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2182 * @hw: pointer to hardware structure 2183 * @byte_offset: byte offset to write 2184 * @dev_addr: address to write to 2185 * @data: value to write 2186 * 2187 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2188 * a specified device address. 2189 **/ 2190 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2191 u8 dev_addr, u8 data) 2192 { 2193 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2194 data, true); 2195 } 2196 2197 /** 2198 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2199 * @hw: pointer to hardware structure 2200 * @byte_offset: byte offset to write 2201 * @dev_addr: address to write to 2202 * @data: value to write 2203 * 2204 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2205 * a specified device address. 2206 **/ 2207 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2208 u8 dev_addr, u8 data) 2209 { 2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2211 data, false); 2212 } 2213 2214 /** 2215 * ixgbe_i2c_start - Sets I2C start condition 2216 * @hw: pointer to hardware structure 2217 * 2218 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2219 * Set bit-bang mode on X550 hardware. 2220 **/ 2221 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2222 { 2223 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2224 2225 DEBUGFUNC("ixgbe_i2c_start"); 2226 2227 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2228 2229 /* Start condition must begin with data and clock high */ 2230 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2231 ixgbe_raise_i2c_clk(hw, &i2cctl); 2232 2233 /* Setup time for start condition (4.7us) */ 2234 usec_delay(IXGBE_I2C_T_SU_STA); 2235 2236 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2237 2238 /* Hold time for start condition (4us) */ 2239 usec_delay(IXGBE_I2C_T_HD_STA); 2240 2241 ixgbe_lower_i2c_clk(hw, &i2cctl); 2242 2243 /* Minimum low period of clock is 4.7 us */ 2244 usec_delay(IXGBE_I2C_T_LOW); 2245 2246 } 2247 2248 /** 2249 * ixgbe_i2c_stop - Sets I2C stop condition 2250 * @hw: pointer to hardware structure 2251 * 2252 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2253 * Disables bit-bang mode and negates data output enable on X550 2254 * hardware. 2255 **/ 2256 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2257 { 2258 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2259 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2260 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2261 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2262 2263 DEBUGFUNC("ixgbe_i2c_stop"); 2264 2265 /* Stop condition must begin with data low and clock high */ 2266 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2267 ixgbe_raise_i2c_clk(hw, &i2cctl); 2268 2269 /* Setup time for stop condition (4us) */ 2270 usec_delay(IXGBE_I2C_T_SU_STO); 2271 2272 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2273 2274 /* bus free time between stop and start (4.7us)*/ 2275 usec_delay(IXGBE_I2C_T_BUF); 2276 2277 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2278 i2cctl &= ~bb_en_bit; 2279 i2cctl |= data_oe_bit | clk_oe_bit; 2280 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2281 IXGBE_WRITE_FLUSH(hw); 2282 } 2283 } 2284 2285 /** 2286 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2287 * @hw: pointer to hardware structure 2288 * @data: data byte to clock in 2289 * 2290 * Clocks in one byte data via I2C data/clock 2291 **/ 2292 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2293 { 2294 s32 i; 2295 bool bit = 0; 2296 2297 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2298 2299 *data = 0; 2300 for (i = 7; i >= 0; i--) { 2301 ixgbe_clock_in_i2c_bit(hw, &bit); 2302 *data |= bit << i; 2303 } 2304 } 2305 2306 /** 2307 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2308 * @hw: pointer to hardware structure 2309 * @data: data byte clocked out 2310 * 2311 * Clocks out one byte data via I2C data/clock 2312 **/ 2313 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2314 { 2315 s32 status = IXGBE_SUCCESS; 2316 s32 i; 2317 u32 i2cctl; 2318 bool bit; 2319 2320 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2321 2322 for (i = 7; i >= 0; i--) { 2323 bit = (data >> i) & 0x1; 2324 status = ixgbe_clock_out_i2c_bit(hw, bit); 2325 2326 if (status != IXGBE_SUCCESS) 2327 break; 2328 } 2329 2330 /* Release SDA line (set high) */ 2331 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2332 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2333 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2334 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2335 IXGBE_WRITE_FLUSH(hw); 2336 2337 return status; 2338 } 2339 2340 /** 2341 * ixgbe_get_i2c_ack - Polls for I2C ACK 2342 * @hw: pointer to hardware structure 2343 * 2344 * Clocks in/out one bit via I2C data/clock 2345 **/ 2346 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2347 { 2348 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2349 s32 status = IXGBE_SUCCESS; 2350 u32 i = 0; 2351 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2352 u32 timeout = 10; 2353 bool ack = 1; 2354 2355 DEBUGFUNC("ixgbe_get_i2c_ack"); 2356 2357 if (data_oe_bit) { 2358 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2359 i2cctl |= data_oe_bit; 2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2361 IXGBE_WRITE_FLUSH(hw); 2362 } 2363 ixgbe_raise_i2c_clk(hw, &i2cctl); 2364 2365 /* Minimum high period of clock is 4us */ 2366 usec_delay(IXGBE_I2C_T_HIGH); 2367 2368 /* Poll for ACK. Note that ACK in I2C spec is 2369 * transition from 1 to 0 */ 2370 for (i = 0; i < timeout; i++) { 2371 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2372 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2373 2374 usec_delay(1); 2375 if (!ack) 2376 break; 2377 } 2378 2379 if (ack) { 2380 DEBUGOUT("I2C ack was not received.\n"); 2381 status = IXGBE_ERR_I2C; 2382 } 2383 2384 ixgbe_lower_i2c_clk(hw, &i2cctl); 2385 2386 /* Minimum low period of clock is 4.7 us */ 2387 usec_delay(IXGBE_I2C_T_LOW); 2388 2389 return status; 2390 } 2391 2392 /** 2393 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2394 * @hw: pointer to hardware structure 2395 * @data: read data value 2396 * 2397 * Clocks in one bit via I2C data/clock 2398 **/ 2399 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2400 { 2401 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2402 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2403 2404 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2405 2406 if (data_oe_bit) { 2407 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2408 i2cctl |= data_oe_bit; 2409 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2410 IXGBE_WRITE_FLUSH(hw); 2411 } 2412 ixgbe_raise_i2c_clk(hw, &i2cctl); 2413 2414 /* Minimum high period of clock is 4us */ 2415 usec_delay(IXGBE_I2C_T_HIGH); 2416 2417 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2418 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2419 2420 ixgbe_lower_i2c_clk(hw, &i2cctl); 2421 2422 /* Minimum low period of clock is 4.7 us */ 2423 usec_delay(IXGBE_I2C_T_LOW); 2424 } 2425 2426 /** 2427 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2428 * @hw: pointer to hardware structure 2429 * @data: data value to write 2430 * 2431 * Clocks out one bit via I2C data/clock 2432 **/ 2433 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2434 { 2435 s32 status; 2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2437 2438 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2439 2440 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2441 if (status == IXGBE_SUCCESS) { 2442 ixgbe_raise_i2c_clk(hw, &i2cctl); 2443 2444 /* Minimum high period of clock is 4us */ 2445 usec_delay(IXGBE_I2C_T_HIGH); 2446 2447 ixgbe_lower_i2c_clk(hw, &i2cctl); 2448 2449 /* Minimum low period of clock is 4.7 us. 2450 * This also takes care of the data hold time. 2451 */ 2452 usec_delay(IXGBE_I2C_T_LOW); 2453 } else { 2454 status = IXGBE_ERR_I2C; 2455 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2456 "I2C data was not set to %X\n", data); 2457 } 2458 2459 return status; 2460 } 2461 2462 /** 2463 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2464 * @hw: pointer to hardware structure 2465 * @i2cctl: Current value of I2CCTL register 2466 * 2467 * Raises the I2C clock line ''->'1' 2468 * Negates the I2C clock output enable on X550 hardware. 2469 **/ 2470 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2471 { 2472 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2473 u32 i = 0; 2474 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2475 u32 i2cctl_r = 0; 2476 2477 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2478 2479 if (clk_oe_bit) { 2480 *i2cctl |= clk_oe_bit; 2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2482 } 2483 2484 for (i = 0; i < timeout; i++) { 2485 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2486 2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2488 IXGBE_WRITE_FLUSH(hw); 2489 /* SCL rise time (1000ns) */ 2490 usec_delay(IXGBE_I2C_T_RISE); 2491 2492 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2493 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2494 break; 2495 } 2496 } 2497 2498 /** 2499 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2500 * @hw: pointer to hardware structure 2501 * @i2cctl: Current value of I2CCTL register 2502 * 2503 * Lowers the I2C clock line '1'->'' 2504 * Asserts the I2C clock output enable on X550 hardware. 2505 **/ 2506 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2507 { 2508 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2509 2510 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2512 2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2514 IXGBE_WRITE_FLUSH(hw); 2515 2516 /* SCL fall time (300ns) */ 2517 usec_delay(IXGBE_I2C_T_FALL); 2518 } 2519 2520 /** 2521 * ixgbe_set_i2c_data - Sets the I2C data bit 2522 * @hw: pointer to hardware structure 2523 * @i2cctl: Current value of I2CCTL register 2524 * @data: I2C data value (0 or 1) to set 2525 * 2526 * Sets the I2C data bit 2527 * Asserts the I2C data output enable on X550 hardware. 2528 **/ 2529 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2530 { 2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2532 s32 status = IXGBE_SUCCESS; 2533 2534 DEBUGFUNC("ixgbe_set_i2c_data"); 2535 2536 if (data) 2537 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2538 else 2539 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2540 *i2cctl &= ~data_oe_bit; 2541 2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2543 IXGBE_WRITE_FLUSH(hw); 2544 2545 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2546 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2547 2548 if (!data) /* Can't verify data in this case */ 2549 return IXGBE_SUCCESS; 2550 if (data_oe_bit) { 2551 *i2cctl |= data_oe_bit; 2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2553 IXGBE_WRITE_FLUSH(hw); 2554 } 2555 2556 /* Verify data was set correctly */ 2557 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2558 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2559 status = IXGBE_ERR_I2C; 2560 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2561 "Error - I2C data was not set to %X.\n", 2562 data); 2563 } 2564 2565 return status; 2566 } 2567 2568 /** 2569 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2570 * @hw: pointer to hardware structure 2571 * @i2cctl: Current value of I2CCTL register 2572 * 2573 * Returns the I2C data bit value 2574 * Negates the I2C data output enable on X550 hardware. 2575 **/ 2576 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2577 { 2578 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2579 bool data; 2580 2581 DEBUGFUNC("ixgbe_get_i2c_data"); 2582 2583 if (data_oe_bit) { 2584 *i2cctl |= data_oe_bit; 2585 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2586 IXGBE_WRITE_FLUSH(hw); 2587 usec_delay(IXGBE_I2C_T_FALL); 2588 } 2589 2590 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2591 data = 1; 2592 else 2593 data = 0; 2594 2595 return data; 2596 } 2597 2598 /** 2599 * ixgbe_i2c_bus_clear - Clears the I2C bus 2600 * @hw: pointer to hardware structure 2601 * 2602 * Clears the I2C bus by sending nine clock pulses. 2603 * Used when data line is stuck low. 2604 **/ 2605 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2606 { 2607 u32 i2cctl; 2608 u32 i; 2609 2610 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2611 2612 ixgbe_i2c_start(hw); 2613 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2614 2615 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2616 2617 for (i = 0; i < 9; i++) { 2618 ixgbe_raise_i2c_clk(hw, &i2cctl); 2619 2620 /* Min high period of clock is 4us */ 2621 usec_delay(IXGBE_I2C_T_HIGH); 2622 2623 ixgbe_lower_i2c_clk(hw, &i2cctl); 2624 2625 /* Min low period of clock is 4.7us*/ 2626 usec_delay(IXGBE_I2C_T_LOW); 2627 } 2628 2629 ixgbe_i2c_start(hw); 2630 2631 /* Put the i2c bus back to default state */ 2632 ixgbe_i2c_stop(hw); 2633 } 2634 2635 /** 2636 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2637 * @hw: pointer to hardware structure 2638 * 2639 * Checks if the LASI temp alarm status was triggered due to overtemp 2640 **/ 2641 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2642 { 2643 s32 status = IXGBE_SUCCESS; 2644 u16 phy_data = 0; 2645 2646 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2647 2648 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2649 goto out; 2650 2651 /* Check that the LASI temp alarm status was triggered */ 2652 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2653 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2654 2655 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2656 goto out; 2657 2658 status = IXGBE_ERR_OVERTEMP; 2659 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2660 out: 2661 return status; 2662 } 2663 2664 /** 2665 * ixgbe_set_copper_phy_power - Control power for copper phy 2666 * @hw: pointer to hardware structure 2667 * @on: true for on, false for off 2668 */ 2669 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2670 { 2671 u32 status; 2672 u16 reg; 2673 2674 if (!on && ixgbe_mng_present(hw)) 2675 return 0; 2676 2677 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2678 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2679 ®); 2680 if (status) 2681 return status; 2682 2683 if (on) { 2684 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2685 } else { 2686 if (ixgbe_check_reset_blocked(hw)) 2687 return 0; 2688 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2689 } 2690 2691 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2692 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2693 reg); 2694 return status; 2695 }
Cache object: 473dfa2e158c0013182f3ae6072e969d
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