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sys/dev/ixl/i40e_adminq_cmd.h
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1 /****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 45 #define I40E_FW_API_VERSION_MAJOR 0x0001 46 #define I40E_FW_API_VERSION_MINOR_X722 0x000C 47 #define I40E_FW_API_VERSION_MINOR_X710 0x000E 48 49 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 50 I40E_FW_API_VERSION_MINOR_X710 : \ 51 I40E_FW_API_VERSION_MINOR_X722) 52 53 /* API version 1.7 implements additional link and PHY-specific APIs */ 54 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 56 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 57 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 58 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 59 /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 60 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 61 62 struct i40e_aq_desc { 63 __le16 flags; 64 __le16 opcode; 65 __le16 datalen; 66 __le16 retval; 67 __le32 cookie_high; 68 __le32 cookie_low; 69 union { 70 struct { 71 __le32 param0; 72 __le32 param1; 73 __le32 param2; 74 __le32 param3; 75 } internal; 76 struct { 77 __le32 param0; 78 __le32 param1; 79 __le32 addr_high; 80 __le32 addr_low; 81 } external; 82 u8 raw[16]; 83 } params; 84 }; 85 86 /* Flags sub-structure 87 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 88 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 89 */ 90 91 /* command flags and offsets*/ 92 #define I40E_AQ_FLAG_DD_SHIFT 0 93 #define I40E_AQ_FLAG_CMP_SHIFT 1 94 #define I40E_AQ_FLAG_ERR_SHIFT 2 95 #define I40E_AQ_FLAG_VFE_SHIFT 3 96 #define I40E_AQ_FLAG_LB_SHIFT 9 97 #define I40E_AQ_FLAG_RD_SHIFT 10 98 #define I40E_AQ_FLAG_VFC_SHIFT 11 99 #define I40E_AQ_FLAG_BUF_SHIFT 12 100 #define I40E_AQ_FLAG_SI_SHIFT 13 101 #define I40E_AQ_FLAG_EI_SHIFT 14 102 #define I40E_AQ_FLAG_FE_SHIFT 15 103 104 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 105 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 106 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 107 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 108 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 109 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 110 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 111 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 112 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 113 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 114 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 115 116 /* error codes */ 117 enum i40e_admin_queue_err { 118 I40E_AQ_RC_OK = 0, /* success */ 119 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 120 I40E_AQ_RC_ENOENT = 2, /* No such element */ 121 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 122 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 123 I40E_AQ_RC_EIO = 5, /* I/O error */ 124 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 125 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 126 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 127 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 128 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 129 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 130 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 131 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 132 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 133 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 134 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 135 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 136 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 137 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 138 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 139 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 140 I40E_AQ_RC_EFBIG = 22, /* File too large */ 141 }; 142 143 /* Admin Queue command opcodes */ 144 enum i40e_admin_queue_opc { 145 /* aq commands */ 146 i40e_aqc_opc_get_version = 0x0001, 147 i40e_aqc_opc_driver_version = 0x0002, 148 i40e_aqc_opc_queue_shutdown = 0x0003, 149 i40e_aqc_opc_set_pf_context = 0x0004, 150 151 /* resource ownership */ 152 i40e_aqc_opc_request_resource = 0x0008, 153 i40e_aqc_opc_release_resource = 0x0009, 154 155 i40e_aqc_opc_list_func_capabilities = 0x000A, 156 i40e_aqc_opc_list_dev_capabilities = 0x000B, 157 158 /* Proxy commands */ 159 i40e_aqc_opc_set_proxy_config = 0x0104, 160 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 161 162 /* LAA */ 163 i40e_aqc_opc_mac_address_read = 0x0107, 164 i40e_aqc_opc_mac_address_write = 0x0108, 165 166 /* PXE */ 167 i40e_aqc_opc_clear_pxe_mode = 0x0110, 168 169 /* WoL commands */ 170 i40e_aqc_opc_set_wol_filter = 0x0120, 171 i40e_aqc_opc_get_wake_reason = 0x0121, 172 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 173 174 /* internal switch commands */ 175 i40e_aqc_opc_get_switch_config = 0x0200, 176 i40e_aqc_opc_add_statistics = 0x0201, 177 i40e_aqc_opc_remove_statistics = 0x0202, 178 i40e_aqc_opc_set_port_parameters = 0x0203, 179 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 180 i40e_aqc_opc_set_switch_config = 0x0205, 181 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 182 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 183 184 i40e_aqc_opc_add_vsi = 0x0210, 185 i40e_aqc_opc_update_vsi_parameters = 0x0211, 186 i40e_aqc_opc_get_vsi_parameters = 0x0212, 187 188 i40e_aqc_opc_add_pv = 0x0220, 189 i40e_aqc_opc_update_pv_parameters = 0x0221, 190 i40e_aqc_opc_get_pv_parameters = 0x0222, 191 192 i40e_aqc_opc_add_veb = 0x0230, 193 i40e_aqc_opc_update_veb_parameters = 0x0231, 194 i40e_aqc_opc_get_veb_parameters = 0x0232, 195 196 i40e_aqc_opc_delete_element = 0x0243, 197 198 i40e_aqc_opc_add_macvlan = 0x0250, 199 i40e_aqc_opc_remove_macvlan = 0x0251, 200 i40e_aqc_opc_add_vlan = 0x0252, 201 i40e_aqc_opc_remove_vlan = 0x0253, 202 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 203 i40e_aqc_opc_add_tag = 0x0255, 204 i40e_aqc_opc_remove_tag = 0x0256, 205 i40e_aqc_opc_add_multicast_etag = 0x0257, 206 i40e_aqc_opc_remove_multicast_etag = 0x0258, 207 i40e_aqc_opc_update_tag = 0x0259, 208 i40e_aqc_opc_add_control_packet_filter = 0x025A, 209 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 210 i40e_aqc_opc_add_cloud_filters = 0x025C, 211 i40e_aqc_opc_remove_cloud_filters = 0x025D, 212 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 213 i40e_aqc_opc_replace_cloud_filters = 0x025F, 214 215 i40e_aqc_opc_add_mirror_rule = 0x0260, 216 i40e_aqc_opc_delete_mirror_rule = 0x0261, 217 218 /* DCB commands */ 219 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 220 i40e_aqc_opc_dcb_updated = 0x0302, 221 i40e_aqc_opc_set_dcb_parameters = 0x0303, 222 223 /* TX scheduler */ 224 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 225 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 226 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 227 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 228 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 229 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 230 231 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 232 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 233 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 234 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 235 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 236 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 237 i40e_aqc_opc_query_port_ets_config = 0x0419, 238 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 239 i40e_aqc_opc_suspend_port_tx = 0x041B, 240 i40e_aqc_opc_resume_port_tx = 0x041C, 241 i40e_aqc_opc_configure_partition_bw = 0x041D, 242 /* hmc */ 243 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 244 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 245 246 /* phy commands*/ 247 i40e_aqc_opc_get_phy_abilities = 0x0600, 248 i40e_aqc_opc_set_phy_config = 0x0601, 249 i40e_aqc_opc_set_mac_config = 0x0603, 250 i40e_aqc_opc_set_link_restart_an = 0x0605, 251 i40e_aqc_opc_get_link_status = 0x0607, 252 i40e_aqc_opc_set_phy_int_mask = 0x0613, 253 i40e_aqc_opc_get_local_advt_reg = 0x0614, 254 i40e_aqc_opc_set_local_advt_reg = 0x0615, 255 i40e_aqc_opc_get_partner_advt = 0x0616, 256 i40e_aqc_opc_set_lb_modes = 0x0618, 257 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 258 i40e_aqc_opc_set_phy_debug = 0x0622, 259 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 260 i40e_aqc_opc_run_phy_activity = 0x0626, 261 i40e_aqc_opc_set_phy_register = 0x0628, 262 i40e_aqc_opc_get_phy_register = 0x0629, 263 264 /* NVM commands */ 265 i40e_aqc_opc_nvm_read = 0x0701, 266 i40e_aqc_opc_nvm_erase = 0x0702, 267 i40e_aqc_opc_nvm_update = 0x0703, 268 i40e_aqc_opc_nvm_config_read = 0x0704, 269 i40e_aqc_opc_nvm_config_write = 0x0705, 270 i40e_aqc_opc_nvm_update_in_process = 0x0706, 271 i40e_aqc_opc_rollback_revision_update = 0x0707, 272 i40e_aqc_opc_oem_post_update = 0x0720, 273 i40e_aqc_opc_thermal_sensor = 0x0721, 274 275 /* virtualization commands */ 276 i40e_aqc_opc_send_msg_to_pf = 0x0801, 277 i40e_aqc_opc_send_msg_to_vf = 0x0802, 278 i40e_aqc_opc_send_msg_to_peer = 0x0803, 279 280 /* alternate structure */ 281 i40e_aqc_opc_alternate_write = 0x0900, 282 i40e_aqc_opc_alternate_write_indirect = 0x0901, 283 i40e_aqc_opc_alternate_read = 0x0902, 284 i40e_aqc_opc_alternate_read_indirect = 0x0903, 285 i40e_aqc_opc_alternate_write_done = 0x0904, 286 i40e_aqc_opc_alternate_set_mode = 0x0905, 287 i40e_aqc_opc_alternate_clear_port = 0x0906, 288 289 /* LLDP commands */ 290 i40e_aqc_opc_lldp_get_mib = 0x0A00, 291 i40e_aqc_opc_lldp_update_mib = 0x0A01, 292 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 293 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 294 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 295 i40e_aqc_opc_lldp_stop = 0x0A05, 296 i40e_aqc_opc_lldp_start = 0x0A06, 297 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 298 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 299 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 300 i40e_aqc_opc_lldp_restore = 0x0A0A, 301 302 /* Tunnel commands */ 303 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 304 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 305 i40e_aqc_opc_set_rss_key = 0x0B02, 306 i40e_aqc_opc_set_rss_lut = 0x0B03, 307 i40e_aqc_opc_get_rss_key = 0x0B04, 308 i40e_aqc_opc_get_rss_lut = 0x0B05, 309 310 /* Async Events */ 311 i40e_aqc_opc_event_lan_overflow = 0x1001, 312 313 /* OEM commands */ 314 i40e_aqc_opc_oem_parameter_change = 0xFE00, 315 i40e_aqc_opc_oem_device_status_change = 0xFE01, 316 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 317 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 318 319 /* debug commands */ 320 i40e_aqc_opc_debug_read_reg = 0xFF03, 321 i40e_aqc_opc_debug_write_reg = 0xFF04, 322 i40e_aqc_opc_debug_modify_reg = 0xFF07, 323 i40e_aqc_opc_debug_dump_internals = 0xFF08, 324 }; 325 326 /* command structures and indirect data structures */ 327 328 /* Structure naming conventions: 329 * - no suffix for direct command descriptor structures 330 * - _data for indirect sent data 331 * - _resp for indirect return data (data which is both will use _data) 332 * - _completion for direct return data 333 * - _element_ for repeated elements (may also be _data or _resp) 334 * 335 * Command structures are expected to overlay the params.raw member of the basic 336 * descriptor, and as such cannot exceed 16 bytes in length. 337 */ 338 339 /* This macro is used to generate a compilation error if a structure 340 * is not exactly the correct length. It gives a divide by zero error if the 341 * structure is not of the correct size, otherwise it creates an enum that is 342 * never used. 343 */ 344 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 345 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 346 347 /* This macro is used extensively to ensure that command structures are 16 348 * bytes in length as they have to map to the raw array of that size. 349 */ 350 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 351 352 /* internal (0x00XX) commands */ 353 354 /* Get version (direct 0x0001) */ 355 struct i40e_aqc_get_version { 356 __le32 rom_ver; 357 __le32 fw_build; 358 __le16 fw_major; 359 __le16 fw_minor; 360 __le16 api_major; 361 __le16 api_minor; 362 }; 363 364 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 365 366 /* Send driver version (indirect 0x0002) */ 367 struct i40e_aqc_driver_version { 368 u8 driver_major_ver; 369 u8 driver_minor_ver; 370 u8 driver_build_ver; 371 u8 driver_subbuild_ver; 372 u8 reserved[4]; 373 __le32 address_high; 374 __le32 address_low; 375 }; 376 377 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 378 379 /* Queue Shutdown (direct 0x0003) */ 380 struct i40e_aqc_queue_shutdown { 381 __le32 driver_unloading; 382 #define I40E_AQ_DRIVER_UNLOADING 0x1 383 u8 reserved[12]; 384 }; 385 386 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 387 388 /* Set PF context (0x0004, direct) */ 389 struct i40e_aqc_set_pf_context { 390 u8 pf_id; 391 u8 reserved[15]; 392 }; 393 394 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 395 396 /* Request resource ownership (direct 0x0008) 397 * Release resource ownership (direct 0x0009) 398 */ 399 #define I40E_AQ_RESOURCE_NVM 1 400 #define I40E_AQ_RESOURCE_SDP 2 401 #define I40E_AQ_RESOURCE_ACCESS_READ 1 402 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 403 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 404 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 405 406 struct i40e_aqc_request_resource { 407 __le16 resource_id; 408 __le16 access_type; 409 __le32 timeout; 410 __le32 resource_number; 411 u8 reserved[4]; 412 }; 413 414 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 415 416 /* Get function capabilities (indirect 0x000A) 417 * Get device capabilities (indirect 0x000B) 418 */ 419 struct i40e_aqc_list_capabilites { 420 u8 command_flags; 421 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 422 u8 pf_index; 423 u8 reserved[2]; 424 __le32 count; 425 __le32 addr_high; 426 __le32 addr_low; 427 }; 428 429 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 430 431 struct i40e_aqc_list_capabilities_element_resp { 432 __le16 id; 433 u8 major_rev; 434 u8 minor_rev; 435 __le32 number; 436 __le32 logical_id; 437 __le32 phys_id; 438 u8 reserved[16]; 439 }; 440 441 /* list of caps */ 442 443 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 444 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 445 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 446 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 447 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 448 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 449 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 450 #define I40E_AQ_CAP_ID_SRIOV 0x0012 451 #define I40E_AQ_CAP_ID_VF 0x0013 452 #define I40E_AQ_CAP_ID_VMDQ 0x0014 453 #define I40E_AQ_CAP_ID_8021QBG 0x0015 454 #define I40E_AQ_CAP_ID_8021QBR 0x0016 455 #define I40E_AQ_CAP_ID_VSI 0x0017 456 #define I40E_AQ_CAP_ID_DCB 0x0018 457 #define I40E_AQ_CAP_ID_FCOE 0x0021 458 #define I40E_AQ_CAP_ID_ISCSI 0x0022 459 #define I40E_AQ_CAP_ID_RSS 0x0040 460 #define I40E_AQ_CAP_ID_RXQ 0x0041 461 #define I40E_AQ_CAP_ID_TXQ 0x0042 462 #define I40E_AQ_CAP_ID_MSIX 0x0043 463 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 464 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 465 #define I40E_AQ_CAP_ID_1588 0x0046 466 #define I40E_AQ_CAP_ID_IWARP 0x0051 467 #define I40E_AQ_CAP_ID_LED 0x0061 468 #define I40E_AQ_CAP_ID_SDP 0x0062 469 #define I40E_AQ_CAP_ID_MDIO 0x0063 470 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 471 #define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067 472 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 473 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 474 #define I40E_AQ_CAP_ID_CEM 0x00F2 475 476 /* Set CPPM Configuration (direct 0x0103) */ 477 struct i40e_aqc_cppm_configuration { 478 __le16 command_flags; 479 #define I40E_AQ_CPPM_EN_LTRC 0x0800 480 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 481 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 482 #define I40E_AQ_CPPM_EN_HPTC 0x4000 483 #define I40E_AQ_CPPM_EN_DMARC 0x8000 484 __le16 ttlx; 485 __le32 dmacr; 486 __le16 dmcth; 487 u8 hptc; 488 u8 reserved; 489 __le32 pfltrc; 490 }; 491 492 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 493 494 /* Set ARP Proxy command / response (indirect 0x0104) */ 495 struct i40e_aqc_arp_proxy_data { 496 __le16 command_flags; 497 #define I40E_AQ_ARP_INIT_IPV4 0x0800 498 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 499 #define I40E_AQ_ARP_ENA 0x2000 500 #define I40E_AQ_ARP_ADD_IPV4 0x4000 501 #define I40E_AQ_ARP_DEL_IPV4 0x8000 502 __le16 table_id; 503 __le32 enabled_offloads; 504 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 505 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 506 __le32 ip_addr; 507 u8 mac_addr[6]; 508 u8 reserved[2]; 509 }; 510 511 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 512 513 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 514 struct i40e_aqc_ns_proxy_data { 515 __le16 table_idx_mac_addr_0; 516 __le16 table_idx_mac_addr_1; 517 __le16 table_idx_ipv6_0; 518 __le16 table_idx_ipv6_1; 519 __le16 control; 520 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 521 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 522 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 523 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 524 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 525 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 526 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 527 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 528 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 529 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 530 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 531 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 532 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 533 u8 mac_addr_0[6]; 534 u8 mac_addr_1[6]; 535 u8 local_mac_addr[6]; 536 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 537 u8 ipv6_addr_1[16]; 538 }; 539 540 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 541 542 /* Manage LAA Command (0x0106) - obsolete */ 543 struct i40e_aqc_mng_laa { 544 __le16 command_flags; 545 #define I40E_AQ_LAA_FLAG_WR 0x8000 546 u8 reserved[2]; 547 __le32 sal; 548 __le16 sah; 549 u8 reserved2[6]; 550 }; 551 552 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 553 554 /* Manage MAC Address Read Command (indirect 0x0107) */ 555 struct i40e_aqc_mac_address_read { 556 __le16 command_flags; 557 #define I40E_AQC_LAN_ADDR_VALID 0x10 558 #define I40E_AQC_SAN_ADDR_VALID 0x20 559 #define I40E_AQC_PORT_ADDR_VALID 0x40 560 #define I40E_AQC_WOL_ADDR_VALID 0x80 561 #define I40E_AQC_MC_MAG_EN_VALID 0x100 562 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 563 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 564 u8 reserved[6]; 565 __le32 addr_high; 566 __le32 addr_low; 567 }; 568 569 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 570 571 struct i40e_aqc_mac_address_read_data { 572 u8 pf_lan_mac[6]; 573 u8 pf_san_mac[6]; 574 u8 port_mac[6]; 575 u8 pf_wol_mac[6]; 576 }; 577 578 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 579 580 /* Manage MAC Address Write Command (0x0108) */ 581 struct i40e_aqc_mac_address_write { 582 __le16 command_flags; 583 #define I40E_AQC_MC_MAG_EN 0x0100 584 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 585 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 586 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 587 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 588 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 589 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 590 591 __le16 mac_sah; 592 __le32 mac_sal; 593 u8 reserved[8]; 594 }; 595 596 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 597 598 /* PXE commands (0x011x) */ 599 600 /* Clear PXE Command and response (direct 0x0110) */ 601 struct i40e_aqc_clear_pxe { 602 u8 rx_cnt; 603 u8 reserved[15]; 604 }; 605 606 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 607 608 /* Set WoL Filter (0x0120) */ 609 610 struct i40e_aqc_set_wol_filter { 611 __le16 filter_index; 612 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 613 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 614 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 615 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 616 617 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 618 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 619 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 620 __le16 cmd_flags; 621 #define I40E_AQC_SET_WOL_FILTER 0x8000 622 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 623 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 624 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 625 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 626 __le16 valid_flags; 627 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 628 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 629 u8 reserved[2]; 630 __le32 address_high; 631 __le32 address_low; 632 }; 633 634 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 635 636 struct i40e_aqc_set_wol_filter_data { 637 u8 filter[128]; 638 u8 mask[16]; 639 }; 640 641 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 642 643 /* Get Wake Reason (0x0121) */ 644 645 struct i40e_aqc_get_wake_reason_completion { 646 u8 reserved_1[2]; 647 __le16 wake_reason; 648 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 649 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 650 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 651 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 652 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 653 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 654 u8 reserved_2[12]; 655 }; 656 657 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 658 659 /* Switch configuration commands (0x02xx) */ 660 661 /* Used by many indirect commands that only pass an seid and a buffer in the 662 * command 663 */ 664 struct i40e_aqc_switch_seid { 665 __le16 seid; 666 u8 reserved[6]; 667 __le32 addr_high; 668 __le32 addr_low; 669 }; 670 671 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 672 673 /* Get Switch Configuration command (indirect 0x0200) 674 * uses i40e_aqc_switch_seid for the descriptor 675 */ 676 struct i40e_aqc_get_switch_config_header_resp { 677 __le16 num_reported; 678 __le16 num_total; 679 u8 reserved[12]; 680 }; 681 682 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 683 684 struct i40e_aqc_switch_config_element_resp { 685 u8 element_type; 686 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 687 #define I40E_AQ_SW_ELEM_TYPE_PF 2 688 #define I40E_AQ_SW_ELEM_TYPE_VF 3 689 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 690 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 691 #define I40E_AQ_SW_ELEM_TYPE_PV 16 692 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 693 #define I40E_AQ_SW_ELEM_TYPE_PA 18 694 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 695 u8 revision; 696 #define I40E_AQ_SW_ELEM_REV_1 1 697 __le16 seid; 698 __le16 uplink_seid; 699 __le16 downlink_seid; 700 u8 reserved[3]; 701 u8 connection_type; 702 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 703 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 704 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 705 __le16 scheduler_id; 706 __le16 element_info; 707 }; 708 709 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 710 711 /* Get Switch Configuration (indirect 0x0200) 712 * an array of elements are returned in the response buffer 713 * the first in the array is the header, remainder are elements 714 */ 715 struct i40e_aqc_get_switch_config_resp { 716 struct i40e_aqc_get_switch_config_header_resp header; 717 struct i40e_aqc_switch_config_element_resp element[1]; 718 }; 719 720 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 721 722 /* Add Statistics (direct 0x0201) 723 * Remove Statistics (direct 0x0202) 724 */ 725 struct i40e_aqc_add_remove_statistics { 726 __le16 seid; 727 __le16 vlan; 728 __le16 stat_index; 729 u8 reserved[10]; 730 }; 731 732 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 733 734 /* Set Port Parameters command (direct 0x0203) */ 735 struct i40e_aqc_set_port_parameters { 736 __le16 command_flags; 737 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 738 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 739 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 740 __le16 bad_frame_vsi; 741 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 742 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 743 __le16 default_seid; /* reserved for command */ 744 u8 reserved[10]; 745 }; 746 747 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 748 749 /* Get Switch Resource Allocation (indirect 0x0204) */ 750 struct i40e_aqc_get_switch_resource_alloc { 751 u8 num_entries; /* reserved for command */ 752 u8 reserved[7]; 753 __le32 addr_high; 754 __le32 addr_low; 755 }; 756 757 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 758 759 /* expect an array of these structs in the response buffer */ 760 struct i40e_aqc_switch_resource_alloc_element_resp { 761 u8 resource_type; 762 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 763 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 764 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 765 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 766 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 767 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 768 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 769 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 770 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 771 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 772 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 773 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 774 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 775 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 776 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 777 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 778 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 779 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 780 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 781 u8 reserved1; 782 __le16 guaranteed; 783 __le16 total; 784 __le16 used; 785 __le16 total_unalloced; 786 u8 reserved2[6]; 787 }; 788 789 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 790 791 /* Set Switch Configuration (direct 0x0205) */ 792 struct i40e_aqc_set_switch_config { 793 __le16 flags; 794 /* flags used for both fields below */ 795 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 796 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 797 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 798 #define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008 799 __le16 valid_flags; 800 /* The ethertype in switch_tag is dropped on ingress and used 801 * internally by the switch. Set this to zero for the default 802 * of 0x88a8 (802.1ad). Should be zero for firmware API 803 * versions lower than 1.7. 804 */ 805 __le16 switch_tag; 806 /* The ethertypes in first_tag and second_tag are used to 807 * match the outer and inner VLAN tags (respectively) when HW 808 * double VLAN tagging is enabled via the set port parameters 809 * AQ command. Otherwise these are both ignored. Set them to 810 * zero for their defaults of 0x8100 (802.1Q). Should be zero 811 * for firmware API versions lower than 1.7. 812 */ 813 __le16 first_tag; 814 __le16 second_tag; 815 /* Next byte is split into following: 816 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 817 * Bit 6 : 0 : Destination Port, 1: source port 818 * Bit 5..4 : L4 type 819 * 0: rsvd 820 * 1: TCP 821 * 2: UDP 822 * 3: Both TCP and UDP 823 * Bits 3:0 Mode 824 * 0: default mode 825 * 1: L4 port only mode 826 * 2: non-tunneled mode 827 * 3: tunneled mode 828 */ 829 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 830 831 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 832 833 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 834 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 835 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 836 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 837 838 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 839 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 840 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 841 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 842 u8 mode; 843 u8 rsvd5[5]; 844 }; 845 846 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 847 848 /* Read Receive control registers (direct 0x0206) 849 * Write Receive control registers (direct 0x0207) 850 * used for accessing Rx control registers that can be 851 * slow and need special handling when under high Rx load 852 */ 853 struct i40e_aqc_rx_ctl_reg_read_write { 854 __le32 reserved1; 855 __le32 address; 856 __le32 reserved2; 857 __le32 value; 858 }; 859 860 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 861 862 /* Add VSI (indirect 0x0210) 863 * this indirect command uses struct i40e_aqc_vsi_properties_data 864 * as the indirect buffer (128 bytes) 865 * 866 * Update VSI (indirect 0x211) 867 * uses the same data structure as Add VSI 868 * 869 * Get VSI (indirect 0x0212) 870 * uses the same completion and data structure as Add VSI 871 */ 872 struct i40e_aqc_add_get_update_vsi { 873 __le16 uplink_seid; 874 u8 connection_type; 875 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 876 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 877 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 878 u8 reserved1; 879 u8 vf_id; 880 u8 reserved2; 881 __le16 vsi_flags; 882 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 883 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 884 #define I40E_AQ_VSI_TYPE_VF 0x0 885 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 886 #define I40E_AQ_VSI_TYPE_PF 0x2 887 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 888 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 889 __le32 addr_high; 890 __le32 addr_low; 891 }; 892 893 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 894 895 struct i40e_aqc_add_get_update_vsi_completion { 896 __le16 seid; 897 __le16 vsi_number; 898 __le16 vsi_used; 899 __le16 vsi_free; 900 __le32 addr_high; 901 __le32 addr_low; 902 }; 903 904 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 905 906 struct i40e_aqc_vsi_properties_data { 907 /* first 96 byte are written by SW */ 908 __le16 valid_sections; 909 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 910 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 911 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 912 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 913 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 914 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 915 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 916 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 917 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 918 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 919 /* switch section */ 920 __le16 switch_id; /* 12bit id combined with flags below */ 921 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 922 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 923 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 924 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 925 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 926 u8 sw_reserved[2]; 927 /* security section */ 928 u8 sec_flags; 929 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 930 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 931 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 932 u8 sec_reserved; 933 /* VLAN section */ 934 __le16 pvid; /* VLANS include priority bits */ 935 __le16 outer_vlan; 936 u8 port_vlan_flags; 937 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 938 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 939 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 940 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 941 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 942 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 943 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 944 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 945 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 946 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 947 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 948 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 949 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 950 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 951 u8 outer_vlan_flags; 952 #define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00 953 #define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \ 954 I40E_AQ_VSI_OVLAN_MODE_SHIFT) 955 #define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01 956 #define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02 957 #define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03 958 #define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04 959 #define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03 960 #define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\ 961 I40E_AQ_VSI_OVLAN_EMOD_SHIFT) 962 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00 963 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01 964 #define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02 965 #define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03 966 #define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04 967 968 u8 pvlan_reserved[2]; 969 /* ingress egress up sections */ 970 __le32 ingress_table; /* bitmap, 3 bits per up */ 971 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 972 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 973 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 974 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 975 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 976 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 977 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 978 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 979 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 980 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 981 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 982 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 983 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 984 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 985 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 986 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 987 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 988 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 989 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 990 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 991 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 992 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 993 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 994 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 995 __le32 egress_table; /* same defines as for ingress table */ 996 /* cascaded PV section */ 997 __le16 cas_pv_tag; 998 u8 cas_pv_flags; 999 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 1000 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 1001 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 1002 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 1003 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 1004 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 1005 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 1006 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 1007 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 1008 u8 cas_pv_reserved; 1009 /* queue mapping section */ 1010 __le16 mapping_flags; 1011 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 1012 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 1013 __le16 queue_mapping[16]; 1014 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 1015 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 1016 __le16 tc_mapping[8]; 1017 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 1018 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 1019 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 1020 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 1021 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 1022 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 1023 /* queueing option section */ 1024 u8 queueing_opt_flags; 1025 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 1026 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1027 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1028 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1029 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1030 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1031 u8 queueing_opt_reserved[3]; 1032 /* scheduler section */ 1033 u8 up_enable_bits; 1034 u8 sched_reserved; 1035 /* outer up section */ 1036 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1037 u8 cmd_reserved[8]; 1038 /* last 32 bytes are written by FW */ 1039 __le16 qs_handle[8]; 1040 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1041 __le16 stat_counter_idx; 1042 __le16 sched_id; 1043 u8 resp_reserved[12]; 1044 }; 1045 1046 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1047 1048 /* Add Port Virtualizer (direct 0x0220) 1049 * also used for update PV (direct 0x0221) but only flags are used 1050 * (IS_CTRL_PORT only works on add PV) 1051 */ 1052 struct i40e_aqc_add_update_pv { 1053 __le16 command_flags; 1054 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1055 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1056 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1057 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1058 __le16 uplink_seid; 1059 __le16 connected_seid; 1060 u8 reserved[10]; 1061 }; 1062 1063 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1064 1065 struct i40e_aqc_add_update_pv_completion { 1066 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1067 __le16 pv_seid; 1068 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1069 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1070 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1071 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1072 u8 reserved[14]; 1073 }; 1074 1075 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1076 1077 /* Get PV Params (direct 0x0222) 1078 * uses i40e_aqc_switch_seid for the descriptor 1079 */ 1080 1081 struct i40e_aqc_get_pv_params_completion { 1082 __le16 seid; 1083 __le16 default_stag; 1084 __le16 pv_flags; /* same flags as add_pv */ 1085 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1086 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1087 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1088 u8 reserved[8]; 1089 __le16 default_port_seid; 1090 }; 1091 1092 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1093 1094 /* Add VEB (direct 0x0230) */ 1095 struct i40e_aqc_add_veb { 1096 __le16 uplink_seid; 1097 __le16 downlink_seid; 1098 __le16 veb_flags; 1099 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1100 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1101 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1102 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1103 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1104 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1105 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1106 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1107 u8 enable_tcs; 1108 u8 reserved[9]; 1109 }; 1110 1111 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1112 1113 struct i40e_aqc_add_veb_completion { 1114 u8 reserved[6]; 1115 __le16 switch_seid; 1116 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1117 __le16 veb_seid; 1118 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1119 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1120 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1121 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1122 __le16 statistic_index; 1123 __le16 vebs_used; 1124 __le16 vebs_free; 1125 }; 1126 1127 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1128 1129 /* Get VEB Parameters (direct 0x0232) 1130 * uses i40e_aqc_switch_seid for the descriptor 1131 */ 1132 struct i40e_aqc_get_veb_parameters_completion { 1133 __le16 seid; 1134 __le16 switch_id; 1135 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1136 __le16 statistic_index; 1137 __le16 vebs_used; 1138 __le16 vebs_free; 1139 u8 reserved[4]; 1140 }; 1141 1142 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1143 1144 /* Delete Element (direct 0x0243) 1145 * uses the generic i40e_aqc_switch_seid 1146 */ 1147 1148 /* Add MAC-VLAN (indirect 0x0250) */ 1149 1150 /* used for the command for most vlan commands */ 1151 struct i40e_aqc_macvlan { 1152 __le16 num_addresses; 1153 __le16 seid[3]; 1154 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1155 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1156 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1157 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1158 __le32 addr_high; 1159 __le32 addr_low; 1160 }; 1161 1162 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1163 1164 /* indirect data for command and response */ 1165 struct i40e_aqc_add_macvlan_element_data { 1166 u8 mac_addr[6]; 1167 __le16 vlan_tag; 1168 __le16 flags; 1169 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1170 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1171 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1172 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1173 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1174 __le16 queue_number; 1175 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1176 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1177 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1178 /* response section */ 1179 u8 match_method; 1180 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1181 #define I40E_AQC_MM_HASH_MATCH 0x02 1182 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1183 u8 reserved1[3]; 1184 }; 1185 1186 struct i40e_aqc_add_remove_macvlan_completion { 1187 __le16 perfect_mac_used; 1188 __le16 perfect_mac_free; 1189 __le16 unicast_hash_free; 1190 __le16 multicast_hash_free; 1191 __le32 addr_high; 1192 __le32 addr_low; 1193 }; 1194 1195 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1196 1197 /* Remove MAC-VLAN (indirect 0x0251) 1198 * uses i40e_aqc_macvlan for the descriptor 1199 * data points to an array of num_addresses of elements 1200 */ 1201 1202 struct i40e_aqc_remove_macvlan_element_data { 1203 u8 mac_addr[6]; 1204 __le16 vlan_tag; 1205 u8 flags; 1206 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1207 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1208 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1209 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1210 u8 reserved[3]; 1211 /* reply section */ 1212 u8 error_code; 1213 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1214 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1215 u8 reply_reserved[3]; 1216 }; 1217 1218 /* Add VLAN (indirect 0x0252) 1219 * Remove VLAN (indirect 0x0253) 1220 * use the generic i40e_aqc_macvlan for the command 1221 */ 1222 struct i40e_aqc_add_remove_vlan_element_data { 1223 __le16 vlan_tag; 1224 u8 vlan_flags; 1225 /* flags for add VLAN */ 1226 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1227 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1228 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1229 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1230 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1231 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1232 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1233 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1234 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1235 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1236 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1237 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1238 /* flags for remove VLAN */ 1239 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1240 u8 reserved; 1241 u8 result; 1242 /* flags for add VLAN */ 1243 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1244 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1245 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1246 /* flags for remove VLAN */ 1247 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1248 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1249 u8 reserved1[3]; 1250 }; 1251 1252 struct i40e_aqc_add_remove_vlan_completion { 1253 u8 reserved[4]; 1254 __le16 vlans_used; 1255 __le16 vlans_free; 1256 __le32 addr_high; 1257 __le32 addr_low; 1258 }; 1259 1260 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1261 struct i40e_aqc_set_vsi_promiscuous_modes { 1262 __le16 promiscuous_flags; 1263 __le16 valid_flags; 1264 /* flags used for both fields above */ 1265 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1266 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1267 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1268 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1269 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1270 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000 1271 __le16 seid; 1272 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1273 __le16 vlan_tag; 1274 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1275 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1276 u8 reserved[8]; 1277 }; 1278 1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1280 1281 /* Add S/E-tag command (direct 0x0255) 1282 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1283 */ 1284 struct i40e_aqc_add_tag { 1285 __le16 flags; 1286 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1287 __le16 seid; 1288 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1289 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1290 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1291 __le16 tag; 1292 __le16 queue_number; 1293 u8 reserved[8]; 1294 }; 1295 1296 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1297 1298 struct i40e_aqc_add_remove_tag_completion { 1299 u8 reserved[12]; 1300 __le16 tags_used; 1301 __le16 tags_free; 1302 }; 1303 1304 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1305 1306 /* Remove S/E-tag command (direct 0x0256) 1307 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1308 */ 1309 struct i40e_aqc_remove_tag { 1310 __le16 seid; 1311 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1312 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1313 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1314 __le16 tag; 1315 u8 reserved[12]; 1316 }; 1317 1318 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1319 1320 /* Add multicast E-Tag (direct 0x0257) 1321 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1322 * and no external data 1323 */ 1324 struct i40e_aqc_add_remove_mcast_etag { 1325 __le16 pv_seid; 1326 __le16 etag; 1327 u8 num_unicast_etags; 1328 u8 reserved[3]; 1329 __le32 addr_high; /* address of array of 2-byte s-tags */ 1330 __le32 addr_low; 1331 }; 1332 1333 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1334 1335 struct i40e_aqc_add_remove_mcast_etag_completion { 1336 u8 reserved[4]; 1337 __le16 mcast_etags_used; 1338 __le16 mcast_etags_free; 1339 __le32 addr_high; 1340 __le32 addr_low; 1341 1342 }; 1343 1344 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1345 1346 /* Update S/E-Tag (direct 0x0259) */ 1347 struct i40e_aqc_update_tag { 1348 __le16 seid; 1349 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1350 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1351 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1352 __le16 old_tag; 1353 __le16 new_tag; 1354 u8 reserved[10]; 1355 }; 1356 1357 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1358 1359 struct i40e_aqc_update_tag_completion { 1360 u8 reserved[12]; 1361 __le16 tags_used; 1362 __le16 tags_free; 1363 }; 1364 1365 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1366 1367 /* Add Control Packet filter (direct 0x025A) 1368 * Remove Control Packet filter (direct 0x025B) 1369 * uses the i40e_aqc_add_oveb_cloud, 1370 * and the generic direct completion structure 1371 */ 1372 struct i40e_aqc_add_remove_control_packet_filter { 1373 u8 mac[6]; 1374 __le16 etype; 1375 __le16 flags; 1376 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1377 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1378 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1379 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1380 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1381 __le16 seid; 1382 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1383 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1384 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1385 __le16 queue; 1386 u8 reserved[2]; 1387 }; 1388 1389 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1390 1391 struct i40e_aqc_add_remove_control_packet_filter_completion { 1392 __le16 mac_etype_used; 1393 __le16 etype_used; 1394 __le16 mac_etype_free; 1395 __le16 etype_free; 1396 u8 reserved[8]; 1397 }; 1398 1399 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1400 1401 /* Add Cloud filters (indirect 0x025C) 1402 * Remove Cloud filters (indirect 0x025D) 1403 * uses the i40e_aqc_add_remove_cloud_filters, 1404 * and the generic indirect completion structure 1405 */ 1406 struct i40e_aqc_add_remove_cloud_filters { 1407 u8 num_filters; 1408 u8 reserved; 1409 __le16 seid; 1410 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1411 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1412 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1413 u8 big_buffer_flag; 1414 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1415 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1416 u8 reserved2[3]; 1417 __le32 addr_high; 1418 __le32 addr_low; 1419 }; 1420 1421 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1422 1423 struct i40e_aqc_cloud_filters_element_data { 1424 u8 outer_mac[6]; 1425 u8 inner_mac[6]; 1426 __le16 inner_vlan; 1427 union { 1428 struct { 1429 u8 reserved[12]; 1430 u8 data[4]; 1431 } v4; 1432 struct { 1433 u8 data[16]; 1434 } v6; 1435 struct { 1436 __le16 data[8]; 1437 } raw_v6; 1438 } ipaddr; 1439 __le16 flags; 1440 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1441 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1442 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1443 /* 0x0000 reserved */ 1444 /* 0x0001 reserved */ 1445 /* 0x0002 reserved */ 1446 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1447 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1448 /* 0x0005 reserved */ 1449 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1450 /* 0x0007 reserved */ 1451 /* 0x0008 reserved */ 1452 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1453 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1454 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1455 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1456 #define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010 1457 #define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012 1458 /* 0x000D reserved */ 1459 /* 0x000E reserved */ 1460 /* 0x000F reserved */ 1461 /* 0x0010 to 0x0017 is for custom filters */ 1462 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1463 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1464 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1465 1466 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1467 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1468 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1469 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1470 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1471 1472 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1473 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1474 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1475 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1476 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1477 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1478 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1479 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1480 1481 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1482 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1483 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1484 1485 __le32 tenant_id; 1486 u8 reserved[4]; 1487 __le16 queue_number; 1488 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1489 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1490 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1491 u8 reserved2[14]; 1492 /* response section */ 1493 u8 allocation_result; 1494 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1495 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1496 u8 response_reserved[7]; 1497 }; 1498 1499 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1500 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. 1501 */ 1502 struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1503 struct i40e_aqc_cloud_filters_element_data element; 1504 u16 general_fields[32]; 1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1520 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1521 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1522 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1523 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1528 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1529 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1530 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1531 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1532 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1533 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1534 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1535 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1536 }; 1537 1538 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1539 1540 /* i40e_aqc_cloud_filters_element_bb is used when 1541 * I40E_AQC_CLOUD_CMD_BB flag is set. 1542 */ 1543 struct i40e_aqc_cloud_filters_element_bb { 1544 struct i40e_aqc_cloud_filters_element_data element; 1545 u16 general_fields[32]; 1546 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1547 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1548 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1549 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1550 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1551 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1552 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1553 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1554 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1555 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1556 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1557 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1558 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1559 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1560 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1561 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1562 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1563 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1564 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1565 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1566 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1567 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1568 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1569 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1570 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1571 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1572 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1573 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1574 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1575 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1576 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1577 }; 1578 1579 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1580 1581 struct i40e_aqc_remove_cloud_filters_completion { 1582 __le16 perfect_ovlan_used; 1583 __le16 perfect_ovlan_free; 1584 __le16 vlan_used; 1585 __le16 vlan_free; 1586 __le32 addr_high; 1587 __le32 addr_low; 1588 }; 1589 1590 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1591 1592 /* Replace filter Command 0x025F 1593 * uses the i40e_aqc_replace_cloud_filters, 1594 * and the generic indirect completion structure 1595 */ 1596 struct i40e_filter_data { 1597 u8 filter_type; 1598 u8 input[3]; 1599 }; 1600 1601 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1602 1603 struct i40e_aqc_replace_cloud_filters_cmd { 1604 u8 valid_flags; 1605 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1606 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1607 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1608 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1609 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1610 u8 old_filter_type; 1611 u8 new_filter_type; 1612 u8 tr_bit; 1613 u8 tr_bit2; 1614 u8 reserved[3]; 1615 __le32 addr_high; 1616 __le32 addr_low; 1617 }; 1618 1619 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1620 1621 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1622 u8 data[32]; 1623 /* Filter type INPUT codes*/ 1624 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1625 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1626 1627 /* Field Vector offsets */ 1628 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1629 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1630 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1631 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1632 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1633 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1634 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1635 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1636 /* big FLU */ 1637 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1638 /* big FLU */ 1639 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1640 1641 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1642 struct i40e_filter_data filters[8]; 1643 }; 1644 1645 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1646 1647 /* Add Mirror Rule (indirect or direct 0x0260) 1648 * Delete Mirror Rule (indirect or direct 0x0261) 1649 * note: some rule types (4,5) do not use an external buffer. 1650 * take care to set the flags correctly. 1651 */ 1652 struct i40e_aqc_add_delete_mirror_rule { 1653 __le16 seid; 1654 __le16 rule_type; 1655 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1656 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1657 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1658 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1659 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1660 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1661 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1662 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1663 __le16 num_entries; 1664 __le16 destination; /* VSI for add, rule id for delete */ 1665 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1666 __le32 addr_low; 1667 }; 1668 1669 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1670 1671 struct i40e_aqc_add_delete_mirror_rule_completion { 1672 u8 reserved[2]; 1673 __le16 rule_id; /* only used on add */ 1674 __le16 mirror_rules_used; 1675 __le16 mirror_rules_free; 1676 __le32 addr_high; 1677 __le32 addr_low; 1678 }; 1679 1680 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1681 1682 /* DCB 0x03xx*/ 1683 1684 /* PFC Ignore (direct 0x0301) 1685 * the command and response use the same descriptor structure 1686 */ 1687 struct i40e_aqc_pfc_ignore { 1688 u8 tc_bitmap; 1689 u8 command_flags; /* unused on response */ 1690 #define I40E_AQC_PFC_IGNORE_SET 0x80 1691 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1692 u8 reserved[14]; 1693 }; 1694 1695 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1696 1697 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1698 * with no parameters 1699 */ 1700 1701 /* TX scheduler 0x04xx */ 1702 1703 /* Almost all the indirect commands use 1704 * this generic struct to pass the SEID in param0 1705 */ 1706 struct i40e_aqc_tx_sched_ind { 1707 __le16 vsi_seid; 1708 u8 reserved[6]; 1709 __le32 addr_high; 1710 __le32 addr_low; 1711 }; 1712 1713 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1714 1715 /* Several commands respond with a set of queue set handles */ 1716 struct i40e_aqc_qs_handles_resp { 1717 __le16 qs_handles[8]; 1718 }; 1719 1720 /* Configure VSI BW limits (direct 0x0400) */ 1721 struct i40e_aqc_configure_vsi_bw_limit { 1722 __le16 vsi_seid; 1723 u8 reserved[2]; 1724 __le16 credit; 1725 u8 reserved1[2]; 1726 u8 max_credit; /* 0-3, limit = 2^max */ 1727 u8 reserved2[7]; 1728 }; 1729 1730 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1731 1732 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1733 * responds with i40e_aqc_qs_handles_resp 1734 */ 1735 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1736 u8 tc_valid_bits; 1737 u8 reserved[15]; 1738 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1739 1740 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1741 __le16 tc_bw_max[2]; 1742 u8 reserved1[28]; 1743 }; 1744 1745 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1746 1747 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1748 * responds with i40e_aqc_qs_handles_resp 1749 */ 1750 struct i40e_aqc_configure_vsi_tc_bw_data { 1751 u8 tc_valid_bits; 1752 u8 reserved[3]; 1753 u8 tc_bw_credits[8]; 1754 u8 reserved1[4]; 1755 __le16 qs_handles[8]; 1756 }; 1757 1758 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1759 1760 /* Query vsi bw configuration (indirect 0x0408) */ 1761 struct i40e_aqc_query_vsi_bw_config_resp { 1762 u8 tc_valid_bits; 1763 u8 tc_suspended_bits; 1764 u8 reserved[14]; 1765 __le16 qs_handles[8]; 1766 u8 reserved1[4]; 1767 __le16 port_bw_limit; 1768 u8 reserved2[2]; 1769 u8 max_bw; /* 0-3, limit = 2^max */ 1770 u8 reserved3[23]; 1771 }; 1772 1773 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1774 1775 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1776 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1777 u8 tc_valid_bits; 1778 u8 reserved[3]; 1779 u8 share_credits[8]; 1780 __le16 credits[8]; 1781 1782 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1783 __le16 tc_bw_max[2]; 1784 }; 1785 1786 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1787 1788 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1789 struct i40e_aqc_configure_switching_comp_bw_limit { 1790 __le16 seid; 1791 u8 reserved[2]; 1792 __le16 credit; 1793 u8 reserved1[2]; 1794 u8 max_bw; /* 0-3, limit = 2^max */ 1795 u8 reserved2[7]; 1796 }; 1797 1798 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1799 1800 /* Enable Physical Port ETS (indirect 0x0413) 1801 * Modify Physical Port ETS (indirect 0x0414) 1802 * Disable Physical Port ETS (indirect 0x0415) 1803 */ 1804 struct i40e_aqc_configure_switching_comp_ets_data { 1805 u8 reserved[4]; 1806 u8 tc_valid_bits; 1807 u8 seepage; 1808 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1809 u8 tc_strict_priority_flags; 1810 u8 reserved1[17]; 1811 u8 tc_bw_share_credits[8]; 1812 u8 reserved2[96]; 1813 }; 1814 1815 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1816 1817 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1818 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1819 u8 tc_valid_bits; 1820 u8 reserved[15]; 1821 __le16 tc_bw_credit[8]; 1822 1823 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1824 __le16 tc_bw_max[2]; 1825 u8 reserved1[28]; 1826 }; 1827 1828 I40E_CHECK_STRUCT_LEN(0x40, 1829 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1830 1831 /* Configure Switching Component Bandwidth Allocation per Tc 1832 * (indirect 0x0417) 1833 */ 1834 struct i40e_aqc_configure_switching_comp_bw_config_data { 1835 u8 tc_valid_bits; 1836 u8 reserved[2]; 1837 u8 absolute_credits; /* bool */ 1838 u8 tc_bw_share_credits[8]; 1839 u8 reserved1[20]; 1840 }; 1841 1842 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1843 1844 /* Query Switching Component Configuration (indirect 0x0418) */ 1845 struct i40e_aqc_query_switching_comp_ets_config_resp { 1846 u8 tc_valid_bits; 1847 u8 reserved[35]; 1848 __le16 port_bw_limit; 1849 u8 reserved1[2]; 1850 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1851 u8 reserved2[23]; 1852 }; 1853 1854 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1855 1856 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1857 struct i40e_aqc_query_port_ets_config_resp { 1858 u8 reserved[4]; 1859 u8 tc_valid_bits; 1860 u8 reserved1; 1861 u8 tc_strict_priority_bits; 1862 u8 reserved2; 1863 u8 tc_bw_share_credits[8]; 1864 __le16 tc_bw_limits[8]; 1865 1866 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1867 __le16 tc_bw_max[2]; 1868 u8 reserved3[32]; 1869 }; 1870 1871 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1872 1873 /* Query Switching Component Bandwidth Allocation per Traffic Type 1874 * (indirect 0x041A) 1875 */ 1876 struct i40e_aqc_query_switching_comp_bw_config_resp { 1877 u8 tc_valid_bits; 1878 u8 reserved[2]; 1879 u8 absolute_credits_enable; /* bool */ 1880 u8 tc_bw_share_credits[8]; 1881 __le16 tc_bw_limits[8]; 1882 1883 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1884 __le16 tc_bw_max[2]; 1885 }; 1886 1887 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1888 1889 /* Suspend/resume port TX traffic 1890 * (direct 0x041B and 0x041C) uses the generic SEID struct 1891 */ 1892 1893 /* Configure partition BW 1894 * (indirect 0x041D) 1895 */ 1896 struct i40e_aqc_configure_partition_bw_data { 1897 __le16 pf_valid_bits; 1898 u8 min_bw[16]; /* guaranteed bandwidth */ 1899 u8 max_bw[16]; /* bandwidth limit */ 1900 }; 1901 1902 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1903 1904 /* Get and set the active HMC resource profile and status. 1905 * (direct 0x0500) and (direct 0x0501) 1906 */ 1907 struct i40e_aq_get_set_hmc_resource_profile { 1908 u8 pm_profile; 1909 u8 pe_vf_enabled; 1910 u8 reserved[14]; 1911 }; 1912 1913 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1914 1915 enum i40e_aq_hmc_profile { 1916 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1917 I40E_HMC_PROFILE_DEFAULT = 1, 1918 I40E_HMC_PROFILE_FAVOR_VF = 2, 1919 I40E_HMC_PROFILE_EQUAL = 3, 1920 }; 1921 1922 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1923 1924 /* set in param0 for get phy abilities to report qualified modules */ 1925 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1926 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1927 1928 enum i40e_aq_phy_type { 1929 I40E_PHY_TYPE_SGMII = 0x0, 1930 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1931 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1932 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1933 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1934 I40E_PHY_TYPE_XAUI = 0x5, 1935 I40E_PHY_TYPE_XFI = 0x6, 1936 I40E_PHY_TYPE_SFI = 0x7, 1937 I40E_PHY_TYPE_XLAUI = 0x8, 1938 I40E_PHY_TYPE_XLPPI = 0x9, 1939 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1940 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1941 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1942 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1943 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1944 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1945 I40E_PHY_TYPE_100BASE_TX = 0x11, 1946 I40E_PHY_TYPE_1000BASE_T = 0x12, 1947 I40E_PHY_TYPE_10GBASE_T = 0x13, 1948 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1949 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1950 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1951 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1952 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1953 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1954 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1955 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1956 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1957 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1958 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1959 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1960 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1961 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1962 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1963 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1964 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1965 I40E_PHY_TYPE_2_5GBASE_T = 0x26, 1966 I40E_PHY_TYPE_5GBASE_T = 0x27, 1967 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30, 1968 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31, 1969 I40E_PHY_TYPE_MAX, 1970 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1971 I40E_PHY_TYPE_EMPTY = 0xFE, 1972 I40E_PHY_TYPE_DEFAULT = 0xFF, 1973 }; 1974 1975 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1976 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1977 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1978 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1979 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1980 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1981 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1982 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1983 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1984 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1985 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1986 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1987 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1988 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1989 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1990 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1991 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1992 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1993 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1994 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1995 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1996 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1997 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1998 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1999 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 2000 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 2001 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 2002 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 2003 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 2004 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 2005 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 2006 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 2007 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 2008 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 2009 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 2010 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 2011 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 2012 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 2013 2014 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 2015 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 2016 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 2017 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 2018 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 2019 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 2020 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 2021 #define I40E_LINK_SPEED_5GB_SHIFT 0x7 2022 2023 enum i40e_aq_link_speed { 2024 I40E_LINK_SPEED_UNKNOWN = 0, 2025 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 2026 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 2027 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 2028 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 2029 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 2030 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 2031 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 2032 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 2033 }; 2034 2035 struct i40e_aqc_module_desc { 2036 u8 oui[3]; 2037 u8 reserved1; 2038 u8 part_number[16]; 2039 u8 revision[4]; 2040 u8 reserved2[8]; 2041 }; 2042 2043 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 2044 2045 struct i40e_aq_get_phy_abilities_resp { 2046 __le32 phy_type; /* bitmap using the above enum for offsets */ 2047 u8 link_speed; /* bitmap using the above enum bit patterns */ 2048 u8 abilities; 2049 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 2050 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 2051 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 2052 #define I40E_AQ_PHY_LINK_ENABLED 0x08 2053 #define I40E_AQ_PHY_AN_ENABLED 0x10 2054 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 2055 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 2056 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 2057 __le16 eee_capability; 2058 #define I40E_AQ_EEE_AUTO 0x0001 2059 #define I40E_AQ_EEE_100BASE_TX 0x0002 2060 #define I40E_AQ_EEE_1000BASE_T 0x0004 2061 #define I40E_AQ_EEE_10GBASE_T 0x0008 2062 #define I40E_AQ_EEE_1000BASE_KX 0x0010 2063 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 2064 #define I40E_AQ_EEE_10GBASE_KR 0x0040 2065 #define I40E_AQ_EEE_2_5GBASE_T 0x0100 2066 #define I40E_AQ_EEE_5GBASE_T 0x0200 2067 __le32 eeer_val; 2068 u8 d3_lpan; 2069 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 2070 u8 phy_type_ext; 2071 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 2072 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 2073 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2074 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2075 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2076 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2077 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2078 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 2079 u8 fec_cfg_curr_mod_ext_info; 2080 #define I40E_AQ_ENABLE_FEC_KR 0x01 2081 #define I40E_AQ_ENABLE_FEC_RS 0x02 2082 #define I40E_AQ_REQUEST_FEC_KR 0x04 2083 #define I40E_AQ_REQUEST_FEC_RS 0x08 2084 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2085 #define I40E_AQ_FEC 2086 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2087 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2088 2089 u8 ext_comp_code; 2090 u8 phy_id[4]; 2091 u8 module_type[3]; 2092 u8 qualified_module_count; 2093 #define I40E_AQ_PHY_MAX_QMS 16 2094 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2095 }; 2096 2097 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2098 2099 /* Set PHY Config (direct 0x0601) */ 2100 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2101 __le32 phy_type; 2102 u8 link_speed; 2103 u8 abilities; 2104 /* bits 0-2 use the values from get_phy_abilities_resp */ 2105 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2106 #define I40E_AQ_PHY_ENABLE_AN 0x10 2107 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2108 __le16 eee_capability; 2109 __le32 eeer; 2110 u8 low_power_ctrl; 2111 u8 phy_type_ext; 2112 u8 fec_config; 2113 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2114 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2115 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2116 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2117 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2118 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2119 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2120 u8 reserved; 2121 }; 2122 2123 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2124 2125 /* Set MAC Config command data structure (direct 0x0603) */ 2126 struct i40e_aq_set_mac_config { 2127 __le16 max_frame_size; 2128 u8 params; 2129 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2130 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2131 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2132 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2133 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2134 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2135 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2136 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2137 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2138 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2139 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2140 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2141 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2142 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2143 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 2144 u8 tx_timer_priority; /* bitmap */ 2145 __le16 tx_timer_value; 2146 __le16 fc_refresh_threshold; 2147 u8 reserved[8]; 2148 }; 2149 2150 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2151 2152 /* Restart Auto-Negotiation (direct 0x605) */ 2153 struct i40e_aqc_set_link_restart_an { 2154 u8 command; 2155 #define I40E_AQ_PHY_RESTART_AN 0x02 2156 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2157 u8 reserved[15]; 2158 }; 2159 2160 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2161 2162 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2163 struct i40e_aqc_get_link_status { 2164 __le16 command_flags; /* only field set on command */ 2165 #define I40E_AQ_LSE_MASK 0x3 2166 #define I40E_AQ_LSE_NOP 0x0 2167 #define I40E_AQ_LSE_DISABLE 0x2 2168 #define I40E_AQ_LSE_ENABLE 0x3 2169 /* only response uses this flag */ 2170 #define I40E_AQ_LSE_IS_ENABLED 0x1 2171 u8 phy_type; /* i40e_aq_phy_type */ 2172 u8 link_speed; /* i40e_aq_link_speed */ 2173 u8 link_info; 2174 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2175 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2176 #define I40E_AQ_LINK_FAULT 0x02 2177 #define I40E_AQ_LINK_FAULT_TX 0x04 2178 #define I40E_AQ_LINK_FAULT_RX 0x08 2179 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2180 #define I40E_AQ_LINK_UP_PORT 0x20 2181 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2182 #define I40E_AQ_SIGNAL_DETECT 0x80 2183 u8 an_info; 2184 #define I40E_AQ_AN_COMPLETED 0x01 2185 #define I40E_AQ_LP_AN_ABILITY 0x02 2186 #define I40E_AQ_PD_FAULT 0x04 2187 #define I40E_AQ_FEC_EN 0x08 2188 #define I40E_AQ_PHY_LOW_POWER 0x10 2189 #define I40E_AQ_LINK_PAUSE_TX 0x20 2190 #define I40E_AQ_LINK_PAUSE_RX 0x40 2191 #define I40E_AQ_QUALIFIED_MODULE 0x80 2192 u8 ext_info; 2193 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2194 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2195 #define I40E_AQ_LINK_TX_SHIFT 0x02 2196 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2197 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2198 #define I40E_AQ_LINK_TX_DRAINED 0x01 2199 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2200 #define I40E_AQ_LINK_FORCED_40G 0x10 2201 /* 25G Error Codes */ 2202 #define I40E_AQ_25G_NO_ERR 0X00 2203 #define I40E_AQ_25G_NOT_PRESENT 0X01 2204 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2205 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2206 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2207 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2208 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2209 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2210 #define I40E_AQ_LOOPBACK_MASK 0x07 2211 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2212 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2213 __le16 max_frame_size; 2214 u8 config; 2215 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2216 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2217 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2218 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2219 union { 2220 struct { 2221 u8 power_desc; 2222 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2223 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2224 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2225 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2226 #define I40E_AQ_PWR_CLASS_MASK 0x03 2227 u8 reserved[4]; 2228 }; 2229 struct { 2230 u8 link_type[4]; 2231 u8 link_type_ext; 2232 }; 2233 }; 2234 }; 2235 2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2237 2238 /* Set event mask command (direct 0x613) */ 2239 struct i40e_aqc_set_phy_int_mask { 2240 u8 reserved[8]; 2241 __le16 event_mask; 2242 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2243 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2244 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2245 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2246 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2247 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2248 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2249 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2250 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2251 u8 reserved1[6]; 2252 }; 2253 2254 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2255 2256 /* Get Local AN advt register (direct 0x0614) 2257 * Set Local AN advt register (direct 0x0615) 2258 * Get Link Partner AN advt register (direct 0x0616) 2259 */ 2260 struct i40e_aqc_an_advt_reg { 2261 __le32 local_an_reg0; 2262 __le16 local_an_reg1; 2263 u8 reserved[10]; 2264 }; 2265 2266 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2267 2268 /* Set Loopback mode (0x0618) */ 2269 struct i40e_aqc_set_lb_mode { 2270 u8 lb_level; 2271 #define I40E_AQ_LB_NONE 0 2272 #define I40E_AQ_LB_MAC 1 2273 #define I40E_AQ_LB_SERDES 2 2274 #define I40E_AQ_LB_PHY_INT 3 2275 #define I40E_AQ_LB_PHY_EXT 4 2276 #define I40E_AQ_LB_BASE_T_PCS 5 2277 #define I40E_AQ_LB_BASE_T_EXT 6 2278 #define I40E_AQ_LB_PHY_LOCAL 0x01 2279 #define I40E_AQ_LB_PHY_REMOTE 0x02 2280 #define I40E_AQ_LB_MAC_LOCAL 0x04 2281 u8 lb_type; 2282 #define I40E_AQ_LB_LOCAL 0 2283 #define I40E_AQ_LB_FAR 0x01 2284 u8 speed; 2285 #define I40E_AQ_LB_SPEED_NONE 0 2286 #define I40E_AQ_LB_SPEED_1G 1 2287 #define I40E_AQ_LB_SPEED_10G 2 2288 #define I40E_AQ_LB_SPEED_40G 3 2289 #define I40E_AQ_LB_SPEED_20G 4 2290 u8 force_speed; 2291 u8 reserved[12]; 2292 }; 2293 2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2295 2296 /* Set PHY Debug command (0x0622) */ 2297 struct i40e_aqc_set_phy_debug { 2298 u8 command_flags; 2299 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2300 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2301 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2302 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2303 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2304 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2305 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2306 /* Disable link manageability on a single port */ 2307 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2308 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2309 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2310 u8 reserved[15]; 2311 }; 2312 2313 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2314 2315 enum i40e_aq_phy_reg_type { 2316 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2317 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2318 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2319 }; 2320 2321 #pragma pack(1) 2322 /* Run PHY Activity (0x0626) */ 2323 struct i40e_aqc_run_phy_activity { 2324 u8 cmd_flags; 2325 __le16 activity_id; 2326 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 2327 u8 reserved; 2328 union { 2329 struct { 2330 __le32 dnl_opcode; 2331 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a 2332 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b 2333 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b 2334 __le32 data; 2335 u8 reserved2[4]; 2336 } cmd; 2337 struct { 2338 __le32 cmd_status; 2339 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 2340 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF 2341 __le32 data0; 2342 __le32 data1; 2343 } resp; 2344 } params; 2345 }; 2346 #pragma pack() 2347 2348 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2349 2350 /* Set PHY Register command (0x0628) */ 2351 /* Get PHY Register command (0x0629) */ 2352 struct i40e_aqc_phy_register_access { 2353 u8 phy_interface; 2354 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2355 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2356 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2357 u8 dev_addres; 2358 u8 cmd_flags; 2359 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 2360 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 2361 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 2362 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ 2363 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) 2364 u8 reserved1; 2365 __le32 reg_address; 2366 __le32 reg_value; 2367 u8 reserved2[4]; 2368 }; 2369 2370 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2371 2372 /* NVM Read command (indirect 0x0701) 2373 * NVM Erase commands (direct 0x0702) 2374 * NVM Update commands (indirect 0x0703) 2375 */ 2376 struct i40e_aqc_nvm_update { 2377 u8 command_flags; 2378 #define I40E_AQ_NVM_LAST_CMD 0x01 2379 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2380 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2381 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2382 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2383 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2384 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2385 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2386 u8 module_pointer; 2387 __le16 length; 2388 __le32 offset; 2389 __le32 addr_high; 2390 __le32 addr_low; 2391 }; 2392 2393 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2394 2395 /* NVM Config Read (indirect 0x0704) */ 2396 struct i40e_aqc_nvm_config_read { 2397 __le16 cmd_flags; 2398 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2399 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2400 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2401 __le16 element_count; 2402 __le16 element_id; /* Feature/field ID */ 2403 __le16 element_id_msw; /* MSWord of field ID */ 2404 __le32 address_high; 2405 __le32 address_low; 2406 }; 2407 2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2409 2410 /* NVM Config Write (indirect 0x0705) */ 2411 struct i40e_aqc_nvm_config_write { 2412 __le16 cmd_flags; 2413 __le16 element_count; 2414 u8 reserved[4]; 2415 __le32 address_high; 2416 __le32 address_low; 2417 }; 2418 2419 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2420 2421 /* Used for 0x0704 as well as for 0x0705 commands */ 2422 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2423 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2424 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2425 #define I40E_AQ_ANVM_FEATURE 0 2426 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2427 struct i40e_aqc_nvm_config_data_feature { 2428 __le16 feature_id; 2429 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2430 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2431 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2432 __le16 feature_options; 2433 __le16 feature_selection; 2434 }; 2435 2436 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2437 2438 /* NVM Update in Process (direct 0x0706) */ 2439 struct i40e_aqc_nvm_update_in_process { 2440 u8 command; 2441 #define I40E_AQ_UPDATE_FLOW_END 0x0 2442 #define I40E_AQ_UPDATE_FLOW_START 0x1 2443 u8 reserved[15]; 2444 }; 2445 2446 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process); 2447 2448 struct i40e_aqc_nvm_config_data_immediate_field { 2449 __le32 field_id; 2450 __le32 field_value; 2451 __le16 field_options; 2452 __le16 reserved; 2453 }; 2454 2455 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2456 2457 /* Minimal Rollback Revision Update (direct 0x0707) */ 2458 struct i40e_aqc_rollback_revision_update { 2459 u8 optin_mode; /* bool */ 2460 #define I40E_AQ_RREV_OPTIN_MODE 0x01 2461 u8 module_selected; 2462 #define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 2463 #define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 2464 #define I40E_AQ_RREV_MODULE_OPTION_ROM 2 2465 #define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 2466 #define I40E_AQ_RREV_MODULE_PE_IMAGE 4 2467 #define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5 2468 #define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6 2469 #define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7 2470 #define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8 2471 u8 reserved1[2]; 2472 u32 min_rrev; 2473 u8 reserved2[8]; 2474 }; 2475 2476 I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update); 2477 2478 /* OEM Post Update (indirect 0x0720) 2479 * no command data struct used 2480 */ 2481 struct i40e_aqc_nvm_oem_post_update { 2482 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2483 u8 sel_data; 2484 u8 reserved[7]; 2485 }; 2486 2487 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2488 2489 struct i40e_aqc_nvm_oem_post_update_buffer { 2490 u8 str_len; 2491 u8 dev_addr; 2492 __le16 eeprom_addr; 2493 u8 data[36]; 2494 }; 2495 2496 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2497 2498 /* Thermal Sensor (indirect 0x0721) 2499 * read or set thermal sensor configs and values 2500 * takes a sensor and command specific data buffer, not detailed here 2501 */ 2502 struct i40e_aqc_thermal_sensor { 2503 u8 sensor_action; 2504 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2505 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2506 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2507 u8 reserved[7]; 2508 __le32 addr_high; 2509 __le32 addr_low; 2510 }; 2511 2512 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2513 2514 /* Send to PF command (indirect 0x0801) id is only used by PF 2515 * Send to VF command (indirect 0x0802) id is only used by PF 2516 * Send to Peer PF command (indirect 0x0803) 2517 */ 2518 struct i40e_aqc_pf_vf_message { 2519 __le32 id; 2520 u8 reserved[4]; 2521 __le32 addr_high; 2522 __le32 addr_low; 2523 }; 2524 2525 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2526 2527 /* Alternate structure */ 2528 2529 /* Direct write (direct 0x0900) 2530 * Direct read (direct 0x0902) 2531 */ 2532 struct i40e_aqc_alternate_write { 2533 __le32 address0; 2534 __le32 data0; 2535 __le32 address1; 2536 __le32 data1; 2537 }; 2538 2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2540 2541 /* Indirect write (indirect 0x0901) 2542 * Indirect read (indirect 0x0903) 2543 */ 2544 2545 struct i40e_aqc_alternate_ind_write { 2546 __le32 address; 2547 __le32 length; 2548 __le32 addr_high; 2549 __le32 addr_low; 2550 }; 2551 2552 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2553 2554 /* Done alternate write (direct 0x0904) 2555 * uses i40e_aq_desc 2556 */ 2557 struct i40e_aqc_alternate_write_done { 2558 __le16 cmd_flags; 2559 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2560 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2561 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2562 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2563 u8 reserved[14]; 2564 }; 2565 2566 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2567 2568 /* Set OEM mode (direct 0x0905) */ 2569 struct i40e_aqc_alternate_set_mode { 2570 __le32 mode; 2571 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2572 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2573 u8 reserved[12]; 2574 }; 2575 2576 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2577 2578 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2579 2580 /* async events 0x10xx */ 2581 2582 /* Lan Queue Overflow Event (direct, 0x1001) */ 2583 struct i40e_aqc_lan_overflow { 2584 __le32 prtdcb_rupto; 2585 __le32 otx_ctl; 2586 u8 reserved[8]; 2587 }; 2588 2589 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2590 2591 /* Get LLDP MIB (indirect 0x0A00) */ 2592 struct i40e_aqc_lldp_get_mib { 2593 u8 type; 2594 u8 reserved1; 2595 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2596 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2597 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2598 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2599 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2600 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2601 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2602 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2603 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2604 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2605 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2606 __le16 local_len; 2607 __le16 remote_len; 2608 u8 reserved2[2]; 2609 __le32 addr_high; 2610 __le32 addr_low; 2611 }; 2612 2613 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2614 2615 /* Configure LLDP MIB Change Event (direct 0x0A01) 2616 * also used for the event (with type in the command field) 2617 */ 2618 struct i40e_aqc_lldp_update_mib { 2619 u8 command; 2620 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2621 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2622 u8 reserved[7]; 2623 __le32 addr_high; 2624 __le32 addr_low; 2625 }; 2626 2627 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2628 2629 /* Add LLDP TLV (indirect 0x0A02) 2630 * Delete LLDP TLV (indirect 0x0A04) 2631 */ 2632 struct i40e_aqc_lldp_add_tlv { 2633 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2634 u8 reserved1[1]; 2635 __le16 len; 2636 u8 reserved2[4]; 2637 __le32 addr_high; 2638 __le32 addr_low; 2639 }; 2640 2641 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2642 2643 /* Update LLDP TLV (indirect 0x0A03) */ 2644 struct i40e_aqc_lldp_update_tlv { 2645 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2646 u8 reserved; 2647 __le16 old_len; 2648 __le16 new_offset; 2649 __le16 new_len; 2650 __le32 addr_high; 2651 __le32 addr_low; 2652 }; 2653 2654 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2655 2656 /* Stop LLDP (direct 0x0A05) */ 2657 struct i40e_aqc_lldp_stop { 2658 u8 command; 2659 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2660 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2661 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2662 u8 reserved[15]; 2663 }; 2664 2665 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2666 2667 /* Start LLDP (direct 0x0A06) */ 2668 struct i40e_aqc_lldp_start { 2669 u8 command; 2670 #define I40E_AQ_LLDP_AGENT_START 0x1 2671 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2672 u8 reserved[15]; 2673 }; 2674 2675 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2676 2677 /* Set DCB (direct 0x0303) */ 2678 struct i40e_aqc_set_dcb_parameters { 2679 u8 command; 2680 #define I40E_AQ_DCB_SET_AGENT 0x1 2681 #define I40E_DCB_VALID 0x1 2682 u8 valid_flags; 2683 u8 reserved[14]; 2684 }; 2685 2686 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2687 2688 /* Get CEE DCBX Oper Config (0x0A07) 2689 * uses the generic descriptor struct 2690 * returns below as indirect response 2691 */ 2692 2693 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2694 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2695 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2696 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2697 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2698 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2699 2700 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2701 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2702 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2703 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2704 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2705 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2706 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2707 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2708 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2709 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2710 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2711 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2712 2713 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2714 * word boundary layout issues, which the Linux compilers silently deal 2715 * with by adding padding, making the actual struct larger than designed. 2716 * However, the FW compiler for the NIC is less lenient and complains 2717 * about the struct. Hence, the struct defined here has an extra byte in 2718 * fields reserved3 and reserved4 to directly acknowledge that padding, 2719 * and the new length is used in the length check macro. 2720 */ 2721 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2722 u8 reserved1; 2723 u8 oper_num_tc; 2724 u8 oper_prio_tc[4]; 2725 u8 reserved2; 2726 u8 oper_tc_bw[8]; 2727 u8 oper_pfc_en; 2728 u8 reserved3[2]; 2729 __le16 oper_app_prio; 2730 u8 reserved4[2]; 2731 __le16 tlv_status; 2732 }; 2733 2734 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2735 2736 struct i40e_aqc_get_cee_dcb_cfg_resp { 2737 u8 oper_num_tc; 2738 u8 oper_prio_tc[4]; 2739 u8 oper_tc_bw[8]; 2740 u8 oper_pfc_en; 2741 __le16 oper_app_prio; 2742 __le32 tlv_status; 2743 u8 reserved[12]; 2744 }; 2745 2746 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2747 2748 /* Set Local LLDP MIB (indirect 0x0A08) 2749 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2750 */ 2751 struct i40e_aqc_lldp_set_local_mib { 2752 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2753 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2754 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2755 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2756 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2757 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2758 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2759 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2760 u8 type; 2761 u8 reserved0; 2762 __le16 length; 2763 u8 reserved1[4]; 2764 __le32 address_high; 2765 __le32 address_low; 2766 }; 2767 2768 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2769 2770 struct i40e_aqc_lldp_set_local_mib_resp { 2771 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2772 u8 status; 2773 u8 reserved[15]; 2774 }; 2775 2776 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2777 2778 /* Stop/Start LLDP Agent (direct 0x0A09) 2779 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2780 */ 2781 struct i40e_aqc_lldp_stop_start_specific_agent { 2782 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2783 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2784 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2785 u8 command; 2786 u8 reserved[15]; 2787 }; 2788 2789 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2790 2791 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2792 struct i40e_aqc_lldp_restore { 2793 u8 command; 2794 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2795 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2796 u8 reserved[15]; 2797 }; 2798 2799 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2800 2801 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2802 struct i40e_aqc_add_udp_tunnel { 2803 __le16 udp_port; 2804 u8 reserved0[3]; 2805 u8 protocol_type; 2806 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2807 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2808 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2809 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2810 u8 reserved1[10]; 2811 }; 2812 2813 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2814 2815 struct i40e_aqc_add_udp_tunnel_completion { 2816 __le16 udp_port; 2817 u8 filter_entry_index; 2818 u8 multiple_pfs; 2819 #define I40E_AQC_SINGLE_PF 0x0 2820 #define I40E_AQC_MULTIPLE_PFS 0x1 2821 u8 total_filters; 2822 u8 reserved[11]; 2823 }; 2824 2825 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2826 2827 /* remove UDP Tunnel command (0x0B01) */ 2828 struct i40e_aqc_remove_udp_tunnel { 2829 u8 reserved[2]; 2830 u8 index; /* 0 to 15 */ 2831 u8 reserved2[13]; 2832 }; 2833 2834 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2835 2836 struct i40e_aqc_del_udp_tunnel_completion { 2837 __le16 udp_port; 2838 u8 index; /* 0 to 15 */ 2839 u8 multiple_pfs; 2840 u8 total_filters_used; 2841 u8 reserved1[11]; 2842 }; 2843 2844 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2845 2846 struct i40e_aqc_get_set_rss_key { 2847 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2848 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2849 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2850 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2851 __le16 vsi_id; 2852 u8 reserved[6]; 2853 __le32 addr_high; 2854 __le32 addr_low; 2855 }; 2856 2857 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2858 2859 struct i40e_aqc_get_set_rss_key_data { 2860 u8 standard_rss_key[0x28]; 2861 u8 extended_hash_key[0xc]; 2862 }; 2863 2864 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2865 2866 struct i40e_aqc_get_set_rss_lut { 2867 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2868 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2869 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2870 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2871 __le16 vsi_id; 2872 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2873 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2874 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2875 2876 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2877 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2878 __le16 flags; 2879 u8 reserved[4]; 2880 __le32 addr_high; 2881 __le32 addr_low; 2882 }; 2883 2884 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2885 2886 /* tunnel key structure 0x0B10 */ 2887 2888 struct i40e_aqc_tunnel_key_structure { 2889 u8 key1_off; 2890 u8 key2_off; 2891 u8 key1_len; /* 0 to 15 */ 2892 u8 key2_len; /* 0 to 15 */ 2893 u8 flags; 2894 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2895 /* response flags */ 2896 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2897 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2898 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2899 u8 network_key_index; 2900 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2901 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2902 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2903 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2904 u8 reserved[10]; 2905 }; 2906 2907 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2908 2909 /* OEM mode commands (direct 0xFE0x) */ 2910 struct i40e_aqc_oem_param_change { 2911 __le32 param_type; 2912 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2913 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2914 #define I40E_AQ_OEM_PARAM_MAC 2 2915 __le32 param_value1; 2916 __le16 param_value2; 2917 u8 reserved[6]; 2918 }; 2919 2920 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2921 2922 struct i40e_aqc_oem_state_change { 2923 __le32 state; 2924 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2925 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2926 u8 reserved[12]; 2927 }; 2928 2929 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2930 2931 /* Initialize OCSD (0xFE02, direct) */ 2932 struct i40e_aqc_opc_oem_ocsd_initialize { 2933 u8 type_status; 2934 u8 reserved1[3]; 2935 __le32 ocsd_memory_block_addr_high; 2936 __le32 ocsd_memory_block_addr_low; 2937 __le32 requested_update_interval; 2938 }; 2939 2940 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2941 2942 /* Initialize OCBB (0xFE03, direct) */ 2943 struct i40e_aqc_opc_oem_ocbb_initialize { 2944 u8 type_status; 2945 u8 reserved1[3]; 2946 __le32 ocbb_memory_block_addr_high; 2947 __le32 ocbb_memory_block_addr_low; 2948 u8 reserved2[4]; 2949 }; 2950 2951 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2952 2953 /* debug commands */ 2954 2955 /* get device id (0xFF00) uses the generic structure */ 2956 2957 /* set test more (0xFF01, internal) */ 2958 2959 struct i40e_acq_set_test_mode { 2960 u8 mode; 2961 #define I40E_AQ_TEST_PARTIAL 0 2962 #define I40E_AQ_TEST_FULL 1 2963 #define I40E_AQ_TEST_NVM 2 2964 u8 reserved[3]; 2965 u8 command; 2966 #define I40E_AQ_TEST_OPEN 0 2967 #define I40E_AQ_TEST_CLOSE 1 2968 #define I40E_AQ_TEST_INC 2 2969 u8 reserved2[3]; 2970 __le32 address_high; 2971 __le32 address_low; 2972 }; 2973 2974 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2975 2976 /* Debug Read Register command (0xFF03) 2977 * Debug Write Register command (0xFF04) 2978 */ 2979 struct i40e_aqc_debug_reg_read_write { 2980 __le32 reserved; 2981 __le32 address; 2982 __le32 value_high; 2983 __le32 value_low; 2984 }; 2985 2986 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2987 2988 /* Scatter/gather Reg Read (indirect 0xFF05) 2989 * Scatter/gather Reg Write (indirect 0xFF06) 2990 */ 2991 2992 /* i40e_aq_desc is used for the command */ 2993 struct i40e_aqc_debug_reg_sg_element_data { 2994 __le32 address; 2995 __le32 value; 2996 }; 2997 2998 /* Debug Modify register (direct 0xFF07) */ 2999 struct i40e_aqc_debug_modify_reg { 3000 __le32 address; 3001 __le32 value; 3002 __le32 clear_mask; 3003 __le32 set_mask; 3004 }; 3005 3006 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 3007 3008 /* dump internal data (0xFF08, indirect) */ 3009 3010 #define I40E_AQ_CLUSTER_ID_AUX 0 3011 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 3012 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 3013 #define I40E_AQ_CLUSTER_ID_HMC 3 3014 #define I40E_AQ_CLUSTER_ID_MAC0 4 3015 #define I40E_AQ_CLUSTER_ID_MAC1 5 3016 #define I40E_AQ_CLUSTER_ID_MAC2 6 3017 #define I40E_AQ_CLUSTER_ID_MAC3 7 3018 #define I40E_AQ_CLUSTER_ID_DCB 8 3019 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 3020 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 3021 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 3022 3023 struct i40e_aqc_debug_dump_internals { 3024 u8 cluster_id; 3025 u8 table_id; 3026 __le16 data_size; 3027 __le32 idx; 3028 __le32 address_high; 3029 __le32 address_low; 3030 }; 3031 3032 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 3033 3034 struct i40e_aqc_debug_modify_internals { 3035 u8 cluster_id; 3036 u8 cluster_specific_params[7]; 3037 __le32 address_high; 3038 __le32 address_low; 3039 }; 3040 3041 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 3042 3043 #endif /* _I40E_ADMINQ_CMD_H_ */
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