1 /*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: releng/8.3/sys/dev/jme/if_jmereg.h 217954 2011-01-27 19:02:28Z yongari $
28 */
29
30 #ifndef _IF_JMEREG_H
31 #define _IF_JMEREG_H
32
33 /*
34 * JMicron Inc. PCI vendor ID
35 */
36 #define VENDORID_JMICRON 0x197B
37
38 /*
39 * JMC250 PCI device ID
40 */
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
44
45 /*
46 * JMC260 PCI device ID
47 */
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
50
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
52
53 /* JMC250 PCI configuration register. */
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
55
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
57
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
59
60 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */
61
62 #define JME_PCI_EROM 0x30
63
64 #define JME_PCI_DBG 0x9C
65
66 #define JME_PCI_PAR0 0xA4 /* JMC25x/JMC26x REVFM >= 5 */
67
68 #define JME_PCI_PAR1 0xA8 /* JMC25x/JMC26x REVFM >= 5 */
69
70 #define JME_PCI_SPI 0xB0
71
72 #define SPI_ENB 0x00000010
73 #define SPI_SO_STATUS 0x00000008
74 #define SPI_SI_CTRL 0x00000004
75 #define SPI_SCK_CTRL 0x00000002
76 #define SPI_CS_N_CTRL 0x00000001
77
78 #define JME_EFUSE_CTL1 0xB8
79 #define EFUSE_CTL1_DATA_MASK 0xF0000000
80 #define EFUSE_CTL1_EXECUTE 0x08000000
81 #define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000
82 #define EFUSE_CTL1_CMD_READ 0x04000000
83 #define EFUSE_CTL1_CMD_BLOW 0x06000000
84 #define EFUSE_CTL1_CMD_MASK 0x06000000
85 #define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000
86 #define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00
87 #define EFUSE_CTL1_BIT_SEL_MASK 0x00000070
88 #define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001
89
90 #define JME_EFUSE_CTL2 0xBC
91 #define EFUSE_CTL2_RESET 0x00008000
92
93 #define JME_PCI_PHYCFG0 0xC0
94
95 #define JME_PCI_PHYCFG1 0xC4
96
97 #define JME_PCI_PHYCFG2 0xC8
98
99 #define JME_PCI_PHYCFG3 0xCC
100
101 #define JME_PCI_PIPECTL1 0xD0
102
103 #define JME_PCI_PIPECTL2 0xD4
104
105 /* PCIe link error/status. */
106 #define JME_PCI_LES 0xD8
107
108 /* Proprietary register 0. */
109 #define JME_PCI_PE0 0xE0
110 #define PE0_SPI_EXIST 0x00200000
111 #define PE0_PME_D0 0x00100000
112 #define PE0_PME_D3H 0x00080000
113 #define PE0_PME_SPI_PAD 0x00040000
114 #define PE0_MASK_ASPM 0x00020000
115 #define PE0_EEPROM_RW_DIS 0x00008000
116 #define PE0_PCI_INTA 0x00001000
117 #define PE0_PCI_INTB 0x00002000
118 #define PE0_PCI_INTC 0x00003000
119 #define PE0_PCI_INTD 0x00004000
120 #define PE0_PCI_SVSSID_WR_ENB 0x00000800
121 #define PE0_MSIX_SIZE_8 0x00000700
122 #define PE0_MSIX_SIZE_7 0x00000600
123 #define PE0_MSIX_SIZE_6 0x00000500
124 #define PE0_MSIX_SIZE_5 0x00000400
125 #define PE0_MSIX_SIZE_4 0x00000300
126 #define PE0_MSIX_SIZE_3 0x00000200
127 #define PE0_MSIX_SIZE_2 0x00000100
128 #define PE0_MSIX_SIZE_1 0x00000000
129 #define PE0_MSIX_SIZE_DEF 0x00000700
130 #define PE0_MSIX_CAP_DIS 0x00000080
131 #define PE0_MSI_PVMC_ENB 0x00000040
132 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038
133 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038
134 #define PE0_PM_AUXC_MASK 0x00000007
135 #define PE0_PM_AUXC_DEF 0x00000007
136
137 /* Proprietary register 1. */
138 #define JME_PCI_PE1 0xE4
139 #define PE1_GIGA_PDOWN_MASK 0x0000C000
140 #define PE1_GIGA_PDOWN_DIS 0x00000000
141 #define PE1_GIGA_PDOWN_D3 0x00004000
142 #define PE1_GIGA_PDOWN_PCIE_SHUTDOWN 0x00008000
143 #define PE1_GIGA_PDOWN_PCIE_IDDQ 0x0000C000
144
145 #define JME_EFUSE_EEPROM 0xE8
146 #define JME_EFUSE_EEPROM_WRITE 0x80000000
147 #define JME_EFUSE_EEPROM_FUNC_MASK 0x70000000
148 #define JME_EFUSE_EEPROM_PAGE_MASK 0x0F000000
149 #define JME_EFUSE_EEPROM_ADDR_MASK 0x00FF0000
150 #define JME_EFUSE_EEPROM_DATA_MASK 0x0000FF00
151 #define JME_EFUSE_EEPROM_SMBSTAT_MASK 0x000000FF
152 #define JME_EFUSE_EEPROM_FUNC_SHIFT 28
153 #define JME_EFUSE_EEPROM_PAGE_SHIFT 24
154 #define JME_EFUSE_EEPROM_ADDR_SHIFT 16
155 #define JME_EFUSE_EEPROM_DATA_SHIFT 8
156 #define JME_EFUSE_EEPROM_SMBSTAT_SHIFT 0
157
158 #define JME_EFUSE_EEPROM_FUNC0 0
159 #define JME_EFUSE_EEPROM_PAGE_BAR0 0
160 #define JME_EFUSE_EEPROM_PAGE_BAR1 1
161 #define JME_EFUSE_EEPROM_PAGE_BAR2 2
162
163 #define JME_PCI_PHYTEST 0xF8
164
165 #define JME_PCI_GPR 0xFC
166
167 /*
168 * JMC Register Map.
169 * -----------------------------------------------------------------------
170 * Register Size IO space Memory space
171 * -----------------------------------------------------------------------
172 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~
173 * BAR1 + 0x7F BAR0 + 0x7F
174 * -----------------------------------------------------------------------
175 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~
176 * BAR2 + 0x7F BAR0 + 0x47F
177 * -----------------------------------------------------------------------
178 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~
179 * BAR2 + 0x7F BAR0 + 0x87F
180 * -----------------------------------------------------------------------
181 * To simplify register access fuctions and to get better performance
182 * this driver doesn't support IO space access. It could be implemented
183 * as a function which selects appropriate BARs to access requested
184 * register.
185 */
186
187 /* Tx control and status. */
188 #define JME_TXCSR 0x0000
189 #define TXCSR_QWEIGHT_MASK 0x0F000000
190 #define TXCSR_QWEIGHT_SHIFT 24
191 #define TXCSR_TXQ_SEL_MASK 0x00070000
192 #define TXCSR_TXQ_SEL_SHIFT 16
193 #define TXCSR_TXQ_START 0x00000001
194 #define TXCSR_TXQ_START_SHIFT 8
195 #define TXCSR_FIFO_THRESH_4QW 0x00000000
196 #define TXCSR_FIFO_THRESH_8QW 0x00000040
197 #define TXCSR_FIFO_THRESH_12QW 0x00000080
198 #define TXCSR_FIFO_THRESH_16QW 0x000000C0
199 #define TXCSR_DMA_SIZE_64 0x00000000
200 #define TXCSR_DMA_SIZE_128 0x00000010
201 #define TXCSR_DMA_SIZE_256 0x00000020
202 #define TXCSR_DMA_SIZE_512 0x00000030
203 #define TXCSR_DMA_BURST 0x00000004
204 #define TXCSR_TX_SUSPEND 0x00000002
205 #define TXCSR_TX_ENB 0x00000001
206 #define TXCSR_TXQ0 0
207 #define TXCSR_TXQ1 1
208 #define TXCSR_TXQ2 2
209 #define TXCSR_TXQ3 3
210 #define TXCSR_TXQ4 4
211 #define TXCSR_TXQ5 5
212 #define TXCSR_TXQ6 6
213 #define TXCSR_TXQ7 7
214 #define TXCSR_TXQ_WEIGHT(x) \
215 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
216 #define TXCSR_TXQ_WEIGHT_MIN 0
217 #define TXCSR_TXQ_WEIGHT_MAX 15
218 #define TXCSR_TXQ_N_SEL(x) \
219 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
220 #define TXCSR_TXQ_N_START(x) \
221 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
222
223 /* Tx queue descriptor base address. 16bytes alignment required. */
224 #define JME_TXDBA_LO 0x0004
225 #define JME_TXDBA_HI 0x0008
226
227 /* Tx queue descriptor count. multiple of 16(max = 1024). */
228 #define JME_TXQDC 0x000C
229 #define TXQDC_MASK 0x0000007F0
230
231 /* Tx queue next descriptor address. */
232 #define JME_TXNDA 0x0010
233 #define TXNDA_ADDR_MASK 0xFFFFFFF0
234 #define TXNDA_DESC_EMPTY 0x00000008
235 #define TXNDA_DESC_VALID 0x00000004
236 #define TXNDA_DESC_WAIT 0x00000002
237 #define TXNDA_DESC_FETCH 0x00000001
238
239 /* Tx MAC control ans status. */
240 #define JME_TXMAC 0x0014
241 #define TXMAC_IFG2_MASK 0xC0000000
242 #define TXMAC_IFG2_DEFAULT 0x40000000
243 #define TXMAC_IFG1_MASK 0x30000000
244 #define TXMAC_IFG1_DEFAULT 0x20000000
245 #define TXMAC_PAUSE_CNT_MASK 0x00FF0000
246 #define TXMAC_THRESH_1_PKT 0x00000300
247 #define TXMAC_THRESH_1_2_PKT 0x00000200
248 #define TXMAC_THRESH_1_4_PKT 0x00000100
249 #define TXMAC_THRESH_1_8_PKT 0x00000000
250 #define TXMAC_FRAME_BURST 0x00000080
251 #define TXMAC_CARRIER_EXT 0x00000040
252 #define TXMAC_IFG_ENB 0x00000020
253 #define TXMAC_BACKOFF 0x00000010
254 #define TXMAC_CARRIER_SENSE 0x00000008
255 #define TXMAC_COLL_ENB 0x00000004
256 #define TXMAC_CRC_ENB 0x00000002
257 #define TXMAC_PAD_ENB 0x00000001
258
259 /* Tx pause frame control. */
260 #define JME_TXPFC 0x0018
261 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000
262 #define TXPFC_VLAN_TAG_SHIFT 16
263 #define TXPFC_VLAN_ENB 0x00008000
264 #define TXPFC_PAUSE_ENB 0x00000001
265
266 /* Tx timer/retry at half duplex. */
267 #define JME_TXTRHD 0x001C
268 #define TXTRHD_RT_PERIOD_ENB 0x80000000
269 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00
270 #define TXTRHD_RT_PERIOD_SHIFT 8
271 #define TXTRHD_RT_LIMIT_ENB 0x00000080
272 #define TXTRHD_RT_LIMIT_MASK 0x0000007F
273 #define TXTRHD_RT_LIMIT_SHIFT 0
274 #define TXTRHD_RT_PERIOD_DEFAULT 8192
275 #define TXTRHD_RT_LIMIT_DEFAULT 8
276
277 /* Rx control & status. */
278 #define JME_RXCSR 0x0020
279 #define RXCSR_FIFO_FTHRESH_16T 0x00000000
280 #define RXCSR_FIFO_FTHRESH_32T 0x10000000
281 #define RXCSR_FIFO_FTHRESH_64T 0x20000000
282 #define RXCSR_FIFO_FTHRESH_128T 0x30000000
283 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000
284 #define RXCSR_FIFO_THRESH_16QW 0x00000000
285 #define RXCSR_FIFO_THRESH_32QW 0x04000000
286 #define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */
287 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */
288 #define RXCSR_FIFO_THRESH_MASK 0x0C000000
289 #define RXCSR_DMA_SIZE_16 0x00000000
290 #define RXCSR_DMA_SIZE_32 0x01000000
291 #define RXCSR_DMA_SIZE_64 0x02000000
292 #define RXCSR_DMA_SIZE_128 0x03000000
293 #define RXCSR_RXQ_SEL_MASK 0x00030000
294 #define RXCSR_RXQ_SEL_SHIFT 16
295 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000
296 #define RXCSR_DESC_RT_GAP_SHIFT 12
297 #define RXCSR_DESC_RT_GAP_256 0x00000000
298 #define RXCSR_DESC_RT_GAP_512 0x00001000
299 #define RXCSR_DESC_RT_GAP_1024 0x00002000
300 #define RXCSR_DESC_RT_GAP_2048 0x00003000
301 #define RXCSR_DESC_RT_GAP_4096 0x00004000
302 #define RXCSR_DESC_RT_GAP_8192 0x00005000
303 #define RXCSR_DESC_RT_GAP_16384 0x00006000
304 #define RXCSR_DESC_RT_GAP_32768 0x00007000
305 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00
306 #define RXCSR_DESC_RT_CNT_SHIFT 8
307 #define RXCSR_PASS_WAKEUP_PKT 0x00000040
308 #define RXCSR_PASS_MAGIC_PKT 0x00000020
309 #define RXCSR_PASS_RUNT_PKT 0x00000010
310 #define RXCSR_PASS_BAD_PKT 0x00000008
311 #define RXCSR_RXQ_START 0x00000004
312 #define RXCSR_RX_SUSPEND 0x00000002
313 #define RXCSR_RX_ENB 0x00000001
314
315 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT)
316 #define RXCSR_RXQ0 0
317 #define RXCSR_RXQ1 1
318 #define RXCSR_RXQ2 2
319 #define RXCSR_RXQ3 3
320 #define RXCSR_DESC_RT_CNT(x) \
321 (((x) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
322 #define RXCSR_DESC_RT_CNT_DEFAULT 0
323
324 /* Rx queue descriptor base address. 16bytes alignment needed. */
325 #define JME_RXDBA_LO 0x0024
326 #define JME_RXDBA_HI 0x0028
327
328 /* Rx queue descriptor count. multiple of 16(max = 1024). */
329 #define JME_RXQDC 0x002C
330 #define RXQDC_MASK 0x0000007F0
331
332 /* Rx queue next descriptor address. */
333 #define JME_RXNDA 0x0030
334 #define RXNDA_ADDR_MASK 0xFFFFFFF0
335 #define RXNDA_DESC_EMPTY 0x00000008
336 #define RXNDA_DESC_VALID 0x00000004
337 #define RXNDA_DESC_WAIT 0x00000002
338 #define RXNDA_DESC_FETCH 0x00000001
339
340 /* Rx MAC control and status. */
341 #define JME_RXMAC 0x0034
342 #define RXMAC_RSS_UNICAST 0x00000000
343 #define RXMAC_RSS_UNI_MULTICAST 0x00010000
344 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000
345 #define RXMAC_RSS_ALLFRAME 0x00030000
346 #define RXMAC_PROMISC 0x00000800
347 #define RXMAC_BROADCAST 0x00000400
348 #define RXMAC_MULTICAST 0x00000200
349 #define RXMAC_UNICAST 0x00000100
350 #define RXMAC_ALLMULTI 0x00000080
351 #define RXMAC_MULTICAST_FILTER 0x00000040
352 #define RXMAC_COLL_DET_ENB 0x00000020
353 #define RXMAC_FC_ENB 0x00000008
354 #define RXMAC_VLAN_ENB 0x00000004
355 #define RXMAC_PAD_10BYTES 0x00000002
356 #define RXMAC_CSUM_ENB 0x00000001
357
358 /* Rx unicast MAC address. Read-only on JMC25x/JMC26x REVFM >= 5 */
359 #define JME_PAR0 0x0038
360 #define JME_PAR1 0x003C
361
362 /* Rx multicast address hash table. */
363 #define JME_MAR0 0x0040
364 #define JME_MAR1 0x0044
365
366 /* Wakeup frame output data port. */
367 #define JME_WFODP 0x0048
368
369 /* Wakeup frame output interface. */
370 #define JME_WFOI 0x004C
371 #define WFOI_MASK_0_31 0x00000000
372 #define WFOI_MASK_31_63 0x00000010
373 #define WFOI_MASK_64_95 0x00000020
374 #define WFOI_MASK_96_127 0x00000030
375 #define WFOI_MASK_SEL 0x00000008
376 #define WFOI_CRC_SEL 0x00000000
377 #define WFOI_WAKEUP_FRAME_MASK 0x00000007
378 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK)
379
380 /* Station management interface. */
381 #define JME_SMI 0x0050
382 #define SMI_DATA_MASK 0xFFFF0000
383 #define SMI_DATA_SHIFT 16
384 #define SMI_REG_ADDR_MASK 0x0000F800
385 #define SMI_REG_ADDR_SHIFT 11
386 #define SMI_PHY_ADDR_MASK 0x000007C0
387 #define SMI_PHY_ADDR_SHIFT 6
388 #define SMI_OP_WRITE 0x00000020
389 #define SMI_OP_READ 0x00000000
390 #define SMI_OP_EXECUTE 0x00000010
391 #define SMI_MDIO 0x00000008
392 #define SMI_MDOE 0x00000004
393 #define SMI_MDC 0x00000002
394 #define SMI_MDEN 0x00000001
395 #define SMI_REG_ADDR(x) \
396 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
397 #define SMI_PHY_ADDR(x) \
398 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
399
400 /* Global host control. */
401 #define JME_GHC 0x0054
402 #define GHC_LOOPBACK 0x80000000
403 #define GHC_RESET 0x40000000
404 #define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */
405 #define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */
406 #define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */
407 #define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */
408 #define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */
409 #define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */
410 #define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */
411 #define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */
412 #define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */
413 #define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */
414 #define GHC_FULL_DUPLEX 0x00000040
415 #define GHC_SPEED_UNKNOWN 0x00000000
416 #define GHC_SPEED_10 0x00000010
417 #define GHC_SPEED_100 0x00000020
418 #define GHC_SPEED_1000 0x00000030
419 #define GHC_SPEED_MASK 0x00000030
420 #define GHC_LINK_OFF 0x00000004
421 #define GHC_LINK_ON 0x00000002
422 #define GHC_LINK_STAT_POLLING 0x00000001
423
424 /* Power management control and status. */
425 #define JME_PMCS 0x0060
426 #define PMCS_WAKEUP_FRAME_7 0x80000000
427 #define PMCS_WAKEUP_FRAME_6 0x40000000
428 #define PMCS_WAKEUP_FRAME_5 0x20000000
429 #define PMCS_WAKEUP_FRAME_4 0x10000000
430 #define PMCS_WAKEUP_FRAME_3 0x08000000
431 #define PMCS_WAKEUP_FRAME_2 0x04000000
432 #define PMCS_WAKEUP_FRAME_1 0x02000000
433 #define PMCS_WAKEUP_FRAME_0 0x01000000
434 #define PMCS_LINK_FAIL 0x00040000
435 #define PMCS_LINK_RISING 0x00020000
436 #define PMCS_MAGIC_FRAME 0x00010000
437 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000
438 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000
439 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000
440 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000
441 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800
442 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400
443 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200
444 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100
445 #define PMCS_LINK_FAIL_ENB 0x00000004
446 #define PMCS_LINK_RISING_ENB 0x00000002
447 #define PMCS_MAGIC_FRAME_ENB 0x00000001
448 #define PMCS_WOL_ENB_MASK 0x0000FFFF
449
450 /*
451 * Statistic registers control and status.
452 * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2.
453 */
454 #define JME_STATCSR 0x0064
455 #define STATCSR_RXMPT_DIS 0x00000080
456 #define STATCSR_OFLOW_DIS 0x00000040
457 #define STATCSR_MIIRXER_DIS 0x00000020
458 #define STATCSR_CRCERR_DIS 0x00000010
459 #define STATCSR_RXBAD_DIS 0x00000008
460 #define STATCSR_RXGOOD_DIS 0x00000004
461 #define STATCSR_TXBAD_DIS 0x00000002
462 #define STATCSR_TXGOOD_DIS 0x00000001
463
464 #define JME_STAT_TXGOOD 0x0068
465
466 #define JME_STAT_RXGOOD 0x006C
467
468 #define JME_STAT_CRCMII 0x0070
469 #define STAT_RX_CRC_ERR_MASK 0xFFFF0000
470 #define STAT_RX_MII_ERR_MASK 0x0000FFFF
471 #define STAT_RX_CRC_ERR_SHIFT 16
472 #define STAT_RX_MII_ERR_SHIFT 0
473
474 #define JME_STAT_RXERR 0x0074
475 #define STAT_RXERR_OFLOW_MASK 0xFFFF0000
476 #define STAT_RXERR_MPTY_MASK 0x0000FFFF
477 #define STAT_RXERR_OFLOW_SHIFT 16
478 #define STAT_RXERR_MPTY_SHIFT 0
479
480 #define JME_STAT_RESERVED1 0x0078
481
482 #define JME_STAT_FAIL 0x007C
483 #define STAT_FAIL_RX_MASK 0xFFFF0000
484 #define STAT_FAIL_TX_MASK 0x0000FFFF
485 #define STAT_FAIL_RX_SHIFT 16
486 #define STAT_FAIL_TX_SHIFT 0
487
488 /* Giga PHY & EEPROM registers. */
489 #define JME_PHY_EEPROM_BASE_ADDR 0x0400
490
491 #define JME_GIGAR0LO 0x0400
492 #define JME_GIGAR0HI 0x0404
493 #define JME_GIGARALO 0x0408
494 #define JME_GIGARAHI 0x040C
495 #define JME_GIGARBLO 0x0410
496 #define JME_GIGARBHI 0x0414
497 #define JME_GIGARCLO 0x0418
498 #define JME_GIGARCHI 0x041C
499 #define JME_GIGARDLO 0x0420
500 #define JME_GIGARDHI 0x0424
501 #define JME_PHYPOWDN 0x0424 /* JMC250/JMC260 REVFM >= 5 */
502
503 /* BIST status and control. */
504 #define JME_GIGACSR 0x0428
505 #define GIGACSR_STATUS 0x40000000
506 #define GIGACSR_CTRL_MASK 0x30000000
507 #define GIGACSR_CTRL_DEFAULT 0x30000000
508 #define GIGACSR_TX_CLK_MASK 0x0F000000
509 #define GIGACSR_RX_CLK_MASK 0x00F00000
510 #define GIGACSR_TX_CLK_INV 0x00080000
511 #define GIGACSR_RX_CLK_INV 0x00040000
512 #define GIGACSR_PHY_RST 0x00010000
513 #define GIGACSR_IRQ_N_O 0x00001000
514 #define GIGACSR_BIST_OK 0x00000200
515 #define GIGACSR_BIST_DONE 0x00000100
516 #define GIGACSR_BIST_LED_ENB 0x00000010
517 #define GIGACSR_BIST_MASK 0x00000003
518
519 /* PHY Link Status. */
520 #define JME_LNKSTS 0x0430
521 #define LINKSTS_SPEED_10 0x00000000
522 #define LINKSTS_SPEED_100 0x00004000
523 #define LINKSTS_SPEED_1000 0x00008000
524 #define LINKSTS_FULL_DUPLEX 0x00002000
525 #define LINKSTS_PAGE_RCVD 0x00001000
526 #define LINKSTS_SPDDPX_RESOLVED 0x00000800
527 #define LINKSTS_UP 0x00000400
528 #define LINKSTS_ANEG_COMP 0x00000200
529 #define LINKSTS_MDI_CROSSOVR 0x00000040
530 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002
531 #define LINKSTS_LPAR_PAUSE 0x00000001
532
533 /* SMB control and status. */
534 #define JME_SMBCSR 0x0440
535 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000
536 #define SMBCSR_WR_DATA_NACK 0x00040000
537 #define SMBCSR_CMD_NACK 0x00020000
538 #define SMBCSR_RELOAD 0x00010000
539 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00
540 #define SMBCSR_SCL_STAT 0x00000080
541 #define SMBCSR_SDA_STAT 0x00000040
542 #define SMBCSR_EEPROM_PRESENT 0x00000020
543 #define SMBCSR_INIT_LD_DONE 0x00000010
544 #define SMBCSR_HW_BUSY_MASK 0x0000000F
545 #define SMBCSR_HW_IDLE 0x00000000
546
547 /* SMB interface. */
548 #define JME_SMBINTF 0x0444
549 #define SMBINTF_RD_DATA_MASK 0xFF000000
550 #define SMBINTF_RD_DATA_SHIFT 24
551 #define SMBINTF_WR_DATA_MASK 0x00FF0000
552 #define SMBINTF_WR_DATA_SHIFT 16
553 #define SMBINTF_ADDR_MASK 0x0000FF00
554 #define SMBINTF_ADDR_SHIFT 8
555 #define SMBINTF_RD 0x00000020
556 #define SMBINTF_WR 0x00000000
557 #define SMBINTF_CMD_TRIGGER 0x00000010
558 #define SMBINTF_BUSY 0x00000010
559 #define SMBINTF_FAST_MODE 0x00000008
560 #define SMBINTF_GPIO_SCL 0x00000004
561 #define SMBINTF_GPIO_SDA 0x00000002
562 #define SMBINTF_GPIO_ENB 0x00000001
563
564 #define JME_EEPROM_SIG0 0x55
565 #define JME_EEPROM_SIG1 0xAA
566 #define JME_EEPROM_DESC_BYTES 3
567 #define JME_EEPROM_DESC_END 0x80
568 #define JME_EEPROM_FUNC_MASK 0x70
569 #define JME_EEPROM_FUNC_SHIFT 4
570 #define JME_EEPROM_PAGE_MASK 0x0F
571 #define JME_EEPROM_PAGE_SHIFT 0
572
573 #define JME_EEPROM_FUNC0 0
574 /* PCI configuration space. */
575 #define JME_EEPROM_PAGE_BAR0 0
576 /* 128 bytes I/O window. */
577 #define JME_EEPROM_PAGE_BAR1 1
578 /* 256 bytes I/O window. */
579 #define JME_EEPROM_PAGE_BAR2 2
580
581 #define JME_EEPROM_END 0xFF
582
583 #define JME_EEPROM_MKDESC(f, p) \
584 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \
585 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
586
587 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
588 #define JME_EEPINTF 0x0448
589 #define EEPINTF_DATA_MASK 0xFFFF0000
590 #define EEPINTF_DATA_SHIFT 16
591 #define EEPINTF_ADDR_MASK 0x0000FC00
592 #define EEPINTF_ADDR_SHIFT 10
593 #define EEPRINTF_OP_MASK 0x00000300
594 #define EEPINTF_OP_EXECUTE 0x00000080
595 #define EEPINTF_DATA_OUT 0x00000008
596 #define EEPINTF_DATA_IN 0x00000004
597 #define EEPINTF_CLK 0x00000002
598 #define EEPINTF_SEL 0x00000001
599
600 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
601 #define JME_EEPCSR 0x044C
602 #define EEPCSR_EEPROM_RELOAD 0x00000002
603 #define EEPCSR_EEPROM_PRESENT 0x00000001
604
605 /* Misc registers. */
606 #define JME_MISC_BASE_ADDR 0x800
607
608 /* Timer control and status. */
609 #define JME_TMCSR 0x0800
610 #define TMCSR_SW_INTR 0x80000000
611 #define TMCSR_TIMER_INTR 0x10000000
612 #define TMCSR_TIMER_ENB 0x01000000
613 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF
614
615 /* GPIO control and status. */
616 #define JME_GPIO 0x0804
617 #define GPIO_4_SPI_IN 0x80000000
618 #define GPIO_3_SPI_IN 0x40000000
619 #define GPIO_4_SPI_OUT 0x20000000
620 #define GPIO_4_SPI_OUT_ENB 0x10000000
621 #define GPIO_3_SPI_OUT 0x08000000
622 #define GPIO_3_SPI_OUT_ENB 0x04000000
623 #define GPIO_3_4_LED 0x00000000
624 #define GPIO_3_4_GPIO 0x02000000
625 #define GPIO_2_CLKREQN_IN 0x00100000
626 #define GPIO_2_CLKREQN_OUT 0x00040000
627 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000
628 #define GPIO_1_LED42_IN 0x00001000
629 #define GPIO_1_LED42_OUT 0x00000400
630 #define GPIO_1_LED42_OUT_ENB 0x00000200
631 #define GPIO_1_LED42_ENB 0x00000100
632 #define GPIO_0_SDA_IN 0x00000010
633 #define GPIO_0_SDA_OUT 0x00000004
634 #define GPIO_0_SDA_OUT_ENB 0x00000002
635 #define GPIO_0_SDA_ENB 0x00000001
636
637 /* General purpose register 0. */
638 #define JME_GPREG0 0x0808
639 #define GPREG0_SH_POST_DW7_DIS 0x80000000
640 #define GPREG0_SH_POST_DW6_DIS 0x40000000
641 #define GPREG0_SH_POST_DW5_DIS 0x20000000
642 #define GPREG0_SH_POST_DW4_DIS 0x10000000
643 #define GPREG0_SH_POST_DW3_DIS 0x08000000
644 #define GPREG0_SH_POST_DW2_DIS 0x04000000
645 #define GPREG0_SH_POST_DW1_DIS 0x02000000
646 #define GPREG0_SH_POST_DW0_DIS 0x01000000
647 #define GPREG0_DMA_RD_REQ_8 0x00000000
648 #define GPREG0_DMA_RD_REQ_6 0x00100000
649 #define GPREG0_DMA_RD_REQ_5 0x00200000
650 #define GPREG0_DMA_RD_REQ_4 0x00300000
651 #define GPREG0_POST_DW0_ENB 0x00040000
652 #define GPREG0_PCC_CLR_DIS 0x00020000
653 #define GPREG0_FORCE_SCL_OUT 0x00010000
654 #define GPREG0_DL_RSTB_DIS 0x00008000
655 #define GPREG0_STICKY_RESET 0x00004000
656 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000
657 #define GPREG0_LINK_CHG_POLL 0x00001000
658 #define GPREG0_LINK_CHG_DIRECT 0x00000000
659 #define GPREG0_MSI_GEN_SEL 0x00000800
660 #define GPREG0_SMB_PAD_PU_DIS 0x00000400
661 #define GPREG0_PCC_UNIT_16US 0x00000000
662 #define GPREG0_PCC_UNIT_256US 0x00000100
663 #define GPREG0_PCC_UNIT_US 0x00000200
664 #define GPREG0_PCC_UNIT_MS 0x00000300
665 #define GPREG0_PCC_UNIT_MASK 0x00000300
666 #define GPREG0_INTR_EVENT_ENB 0x00000080
667 #define GPREG0_PME_ENB 0x00000020
668 #define GPREG0_PHY_ADDR_MASK 0x0000001F
669 #define GPREG0_PHY_ADDR_SHIFT 0
670 #define GPREG0_PHY_ADDR 1
671
672 /* General purpose register 1. */
673 #define JME_GPREG1 0x080C
674 #define GPREG1_RX_MAC_CLK_DIS 0x04000000 /* JMC250/JMC260 REVFM >= 2 */
675 #define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */
676 #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */
677 #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */
678 #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */
679 #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */
680 #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */
681 #define GPREG1_INTDLY_MASK 0x00000007
682
683 /* MSIX entry number of interrupt source. */
684 #define JME_MSINUM_BASE 0x0810
685 #define JME_MSINUM_END 0x081F
686 #define MSINUM_MASK 0x7FFFFFFF
687 #define MSINUM_ENTRY_MASK 7
688 #define MSINUM_REG_INDEX(x) ((x) / 8)
689 #define MSINUM_INTR_SOURCE(x, y) \
690 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4))
691 #define MSINUM_NUM_INTR_SOURCE 32
692
693 /* Interrupt event status. */
694 #define JME_INTR_STATUS 0x0820
695 #define INTR_SW 0x80000000
696 #define INTR_TIMER 0x40000000
697 #define INTR_LINKCHG 0x20000000
698 #define INTR_PAUSE 0x10000000
699 #define INTR_MAGIC_PKT 0x08000000
700 #define INTR_WAKEUP_PKT 0x04000000
701 #define INTR_RXQ0_COAL_TO 0x02000000
702 #define INTR_RXQ1_COAL_TO 0x01000000
703 #define INTR_RXQ2_COAL_TO 0x00800000
704 #define INTR_RXQ3_COAL_TO 0x00400000
705 #define INTR_TXQ_COAL_TO 0x00200000
706 #define INTR_RXQ0_COAL 0x00100000
707 #define INTR_RXQ1_COAL 0x00080000
708 #define INTR_RXQ2_COAL 0x00040000
709 #define INTR_RXQ3_COAL 0x00020000
710 #define INTR_TXQ_COAL 0x00010000
711 #define INTR_RXQ3_DESC_EMPTY 0x00008000
712 #define INTR_RXQ2_DESC_EMPTY 0x00004000
713 #define INTR_RXQ1_DESC_EMPTY 0x00002000
714 #define INTR_RXQ0_DESC_EMPTY 0x00001000
715 #define INTR_RXQ3_COMP 0x00000800
716 #define INTR_RXQ2_COMP 0x00000400
717 #define INTR_RXQ1_COMP 0x00000200
718 #define INTR_RXQ0_COMP 0x00000100
719 #define INTR_TXQ7_COMP 0x00000080
720 #define INTR_TXQ6_COMP 0x00000040
721 #define INTR_TXQ5_COMP 0x00000020
722 #define INTR_TXQ4_COMP 0x00000010
723 #define INTR_TXQ3_COMP 0x00000008
724 #define INTR_TXQ2_COMP 0x00000004
725 #define INTR_TXQ1_COMP 0x00000002
726 #define INTR_TXQ0_COMP 0x00000001
727
728 #define INTR_RXQ_COAL_TO \
729 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \
730 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
731
732 #define INTR_RXQ_COAL \
733 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \
734 INTR_RXQ3_COAL)
735
736 #define INTR_RXQ_COMP \
737 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
738 INTR_RXQ3_COMP)
739
740 #define INTR_RXQ_DESC_EMPTY \
741 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \
742 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
743
744 #define INTR_RXQ_COMP \
745 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
746 INTR_RXQ3_COMP)
747
748 #define INTR_TXQ_COMP \
749 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \
750 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \
751 INTR_TXQ6_COMP | INTR_TXQ7_COMP)
752
753 #define JME_INTRS \
754 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \
755 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
756
757 #define N_INTR_SW 31
758 #define N_INTR_TIMER 30
759 #define N_INTR_LINKCHG 29
760 #define N_INTR_PAUSE 28
761 #define N_INTR_MAGIC_PKT 27
762 #define N_INTR_WAKEUP_PKT 26
763 #define N_INTR_RXQ0_COAL_TO 25
764 #define N_INTR_RXQ1_COAL_TO 24
765 #define N_INTR_RXQ2_COAL_TO 23
766 #define N_INTR_RXQ3_COAL_TO 22
767 #define N_INTR_TXQ_COAL_TO 21
768 #define N_INTR_RXQ0_COAL 20
769 #define N_INTR_RXQ1_COAL 19
770 #define N_INTR_RXQ2_COAL 18
771 #define N_INTR_RXQ3_COAL 17
772 #define N_INTR_TXQ_COAL 16
773 #define N_INTR_RXQ3_DESC_EMPTY 15
774 #define N_INTR_RXQ2_DESC_EMPTY 14
775 #define N_INTR_RXQ1_DESC_EMPTY 13
776 #define N_INTR_RXQ0_DESC_EMPTY 12
777 #define N_INTR_RXQ3_COMP 11
778 #define N_INTR_RXQ2_COMP 10
779 #define N_INTR_RXQ1_COMP 9
780 #define N_INTR_RXQ0_COMP 8
781 #define N_INTR_TXQ7_COMP 7
782 #define N_INTR_TXQ6_COMP 6
783 #define N_INTR_TXQ5_COMP 5
784 #define N_INTR_TXQ4_COMP 4
785 #define N_INTR_TXQ3_COMP 3
786 #define N_INTR_TXQ2_COMP 2
787 #define N_INTR_TXQ1_COMP 1
788 #define N_INTR_TXQ0_COMP 0
789
790 /* Interrupt request status. */
791 #define JME_INTR_REQ_STATUS 0x0824
792
793 /* Interrupt enable - setting port. */
794 #define JME_INTR_MASK_SET 0x0828
795
796 /* Interrupt enable - clearing port. */
797 #define JME_INTR_MASK_CLR 0x082C
798
799 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
800 #define JME_PCCRX0 0x0830
801 #define JME_PCCRX1 0x0834
802 #define JME_PCCRX2 0x0838
803 #define JME_PCCRX3 0x083C
804 #define PCCRX_COAL_TO_MASK 0xFFFF0000
805 #define PCCRX_COAL_TO_SHIFT 16
806 #define PCCRX_COAL_PKT_MASK 0x0000FF00
807 #define PCCRX_COAL_PKT_SHIFT 8
808
809 #define PCCRX_COAL_TO_MIN 1
810 #define PCCRX_COAL_TO_DEFAULT 100
811 #define PCCRX_COAL_TO_MAX 65535
812
813 #define PCCRX_COAL_PKT_MIN 1
814 #define PCCRX_COAL_PKT_DEFAULT 2
815 #define PCCRX_COAL_PKT_MAX 255
816
817 /* Packet completion coalescing control of Tx queue. */
818 #define JME_PCCTX 0x0840
819 #define PCCTX_COAL_TO_MASK 0xFFFF0000
820 #define PCCTX_COAL_TO_SHIFT 16
821 #define PCCTX_COAL_PKT_MASK 0x0000FF00
822 #define PCCTX_COAL_PKT_SHIFT 8
823 #define PCCTX_COAL_TXQ7 0x00000080
824 #define PCCTX_COAL_TXQ6 0x00000040
825 #define PCCTX_COAL_TXQ5 0x00000020
826 #define PCCTX_COAL_TXQ4 0x00000010
827 #define PCCTX_COAL_TXQ3 0x00000008
828 #define PCCTX_COAL_TXQ2 0x00000004
829 #define PCCTX_COAL_TXQ1 0x00000002
830 #define PCCTX_COAL_TXQ0 0x00000001
831
832 #define PCCTX_COAL_TO_MIN 1
833 #define PCCTX_COAL_TO_DEFAULT 100
834 #define PCCTX_COAL_TO_MAX 65535
835
836 #define PCCTX_COAL_PKT_MIN 1
837 #define PCCTX_COAL_PKT_DEFAULT 8
838 #define PCCTX_COAL_PKT_MAX 255
839
840 /* Chip mode and FPGA version. */
841 #define JME_CHIPMODE 0x0844
842 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000
843 #define CHIPMODE_FPGA_REV_SHIFT 16
844 #define CHIPMODE_NOT_FPGA 0
845 #define CHIPMODE_REV_MASK 0x0000FF00
846 #define CHIPMODE_REV_SHIFT 8
847 #define CHIPMODE_MODE_48P 0x0000000C
848 #define CHIPMODE_MODE_64P 0x00000004
849 #define CHIPMODE_MODE_128P_MAC 0x00000003
850 #define CHIPMODE_MODE_128P_DBG 0x00000002
851 #define CHIPMODE_MODE_128P_PHY 0x00000000
852 /* Chip full mask revision. */
853 #define CHIPMODE_REVFM(x) ((x) & 0x0F)
854 /* Chip ECO revision. */
855 #define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F)
856
857 /* Shadow status base address high/low. */
858 #define JME_SHBASE_ADDR_HI 0x0848
859 #define JME_SHBASE_ADDR_LO 0x084C
860 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0
861 #define SHBASE_POST_FORCE 0x00000002
862 #define SHBASE_POST_ENB 0x00000001
863
864 #define JME_PCDRX_BASE 0x0850
865 #define JME_PCDRX_END 0x0857
866 #define PCDRX_REG(x) (JME_PCDRX_BASE + (((x) / 2) * 4))
867 #define PCDRX1_TO_THROTTLE_MASK 0xFF000000
868 #define PCDRX1_TO_MASK 0x00FF0000
869 #define PCDRX0_TO_THROTTLE_MASK 0x0000FF00
870 #define PCDRX0_TO_MASK 0x000000FF
871 #define PCDRX1_TO_THROTTLE_SHIFT 24
872 #define PCDRX1_TO_SHIFT 16
873 #define PCDRX0_TO_THROTTLE_SHIFT 8
874 #define PCDRX0_TO_SHIFT 0
875 #define PCDRX_TO_MIN 1
876 #define PCDRX_TO_MAX 255
877
878 #define JME_PCDTX 0x0858
879 #define PCDTX_TO_THROTTLE_MASK 0x0000FF00
880 #define PCDTX_TO_MASK 0x000000FF
881 #define PCDTX_TO_THROTTLE_SHIFT 8
882 #define PCDTX_TO_SHIFT 0
883 #define PCDTX_TO_MIN 1
884 #define PCDTX_TO_MAX 255
885
886 #define JME_PCCPCD_STAT 0x085C
887 #define PCCPCD_STAT_RX3_MASK 0xFF000000
888 #define PCCPCD_STAT_RX2_MASK 0x00FF0000
889 #define PCCPCD_STAT_RX1_MASK 0x0000FF00
890 #define PCCPCD_STAT_RX0_MASK 0x000000FF
891 #define PCCPCD_STAT_RX3_SHIFT 24
892 #define PCCPCD_STAT_RX2_SHIFT 16
893 #define PCCPCD_STAT_RX1_SHIFT 8
894 #define PCCPCD_STAT_RX0_SHIFT 0
895
896 /* TX data throughput in KB. */
897 #define JME_TX_THROUGHPUT 0x0860
898 #define TX_THROUGHPUT_MASK 0x000FFFFF
899
900 /* RX data throughput in KB. */
901 #define JME_RX_THROUGHPUT 0x0864
902 #define RX_THROUGHPUT_MASK 0x000FFFFF
903
904 #define JME_LPI_CTL 0x086C
905 #define LPI_STAT_ANC_ANF 0x00000010
906 #define LPI_STAT_AN_TIMEOUT 0x00000008
907 #define LPI_STAT_RX_LPI 0x00000004
908 #define LPI_INT_ENB 0x00000002
909 #define LPI_REQ 0x00000001
910
911 /* Timer 1 and 2. */
912 #define JME_TIMER1 0x0870
913 #define JME_TIMER2 0x0874
914 #define TIMER_ENB 0x01000000
915 #define TIMER_CNT_MASK 0x00FFFFFF
916 #define TIMER_CNT_SHIFT 0
917 #define TIMER_UNIT 1024 /* 1024us */
918
919 /* Timer 3. */
920 #define JME_TIMER3 0x0878
921 #define TIMER3_TIMEOUT 0x00010000
922 #define TIMER3_TIMEOUT_COUNT_MASK 0x0000FF00 /* 130ms unit */
923 #define TIMER3_TIMEOUT_VAL_MASK 0x000000E0
924 #define TIMER3_ENB 0x00000001
925 #define TIMER3_TIMEOUT_COUNT_SHIFT 8
926 #define TIMER3_TIMEOUT_VALUE_SHIFT 1
927
928 /* Aggresive power mode control. */
929 #define JME_APMC 0x087C
930 #define APMC_PCIE_SDOWN_STAT 0x80000000
931 #define APMC_PCIE_SDOWN_ENB 0x40000000
932 #define APMC_PSEUDO_HOT_PLUG 0x20000000
933 #define APMC_EXT_PLUGIN_ENB 0x04000000
934 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000
935 #define APMC_DIS_SRAM 0x00000004
936 #define APMC_DIS_CLKPM 0x00000002
937 #define APMC_DIS_CLKTX 0x00000001
938
939 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
940 #define JME_PCCSRX_BASE 0x0880
941 #define JME_PCCSRX_END 0x088F
942 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4))
943 #define PCCSRX_TO_MASK 0xFFFF0000
944 #define PCCSRX_TO_SHIFT 16
945 #define PCCSRX_PKT_CNT_MASK 0x0000FF00
946 #define PCCSRX_PKT_CNT_SHIFT 8
947
948 /* Packet completion coalesing status of Tx queue. */
949 #define JME_PCCSTX 0x0890
950 #define PCCSTX_TO_MASK 0xFFFF0000
951 #define PCCSTX_TO_SHIFT 16
952 #define PCCSTX_PKT_CNT_MASK 0x0000FF00
953 #define PCCSTX_PKT_CNT_SHIFT 8
954
955 /* Tx queues empty indicator. */
956 #define JME_TXQEMPTY 0x0894
957 #define TXQEMPTY_TXQ7 0x00000080
958 #define TXQEMPTY_TXQ6 0x00000040
959 #define TXQEMPTY_TXQ5 0x00000020
960 #define TXQEMPTY_TXQ4 0x00000010
961 #define TXQEMPTY_TXQ3 0x00000008
962 #define TXQEMPTY_TXQ2 0x00000004
963 #define TXQEMPTY_TXQ1 0x00000002
964 #define TXQEMPTY_TXQ0 0x00000001
965 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y)))
966
967 /* RSS control registers. */
968 #define JME_RSS_BASE 0x0C00
969
970 #define JME_RSSC 0x0C00
971 #define RSSC_HASH_LEN_MASK 0x0000E000
972 #define RSSC_HASH_64_ENTRY 0x0000A000
973 #define RSSC_HASH_128_ENTRY 0x0000E000
974 #define RSSC_HASH_NONE 0x00001000
975 #define RSSC_HASH_IPV6 0x00000800
976 #define RSSC_HASH_IPV4 0x00000400
977 #define RSSC_HASH_IPV6_TCP 0x00000200
978 #define RSSC_HASH_IPV4_TCP 0x00000100
979 #define RSSC_NCPU_MASK 0x000000F8
980 #define RSSC_NCPU_SHIFT 3
981 #define RSSC_DIS_RSS 0x00000000
982 #define RSSC_2RXQ_ENB 0x00000001
983 #define RSSS_4RXQ_ENB 0x00000002
984
985 /* CPU vector. */
986 #define JME_RSSCPU 0x0C04
987 #define RSSCPU_N_SEL(x) ((1 << (x))
988
989 /* RSS Hash value. */
990 #define JME_RSSHASH 0x0C10
991
992 #define JME_RSSHASH_STAT 0x0C14
993
994 #define JME_RSS_RDATA0 0x0C18
995
996 #define JME_RSS_RDATA1 0x0C1C
997
998 /* RSS secret key. */
999 #define JME_RSSKEY_BASE 0x0C40
1000 #define JME_RSSKEY_LAST 0x0C64
1001 #define JME_RSSKEY_END 0x0C67
1002 #define HASHKEY_NBYTES 40
1003 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4)))
1004 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4)))
1005
1006 /* RSS indirection table entries. */
1007 #define JME_RSSTBL_BASE 0x0C80
1008 #define JME_RSSTBL_END 0x0CFF
1009 #define RSSTBL_NENTRY 128
1010 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4))
1011 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4)))
1012
1013 /* MSI-X table. */
1014 #define JME_MSIX_BASE_ADDR 0x2000
1015
1016 #define JME_MSIX_BASE 0x2000
1017 #define JME_MSIX_END 0x207F
1018 #define JME_MSIX_NENTRY 8
1019 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10))
1020 #define MSIX_ADDR_HI_OFF 0x00
1021 #define MSIX_ADDR_LO_OFF 0x04
1022 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC
1023 #define MSIX_DATA_OFF 0x08
1024 #define MSIX_VECTOR_OFF 0x0C
1025 #define MSIX_VECTOR_RSVD 0x80000000
1026 #define MSIX_VECTOR_DIS 0x00000001
1027
1028 /* MSI-X PBA. */
1029 #define JME_MSIX_PBA_BASE_ADDR 0x3000
1030
1031 #define JME_MSIX_PBA 0x3000
1032 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00
1033 #define MSIX_PBA_RSVD_SHIFT 8
1034 #define MSIX_PBA_PEND_MASK 0x000000FF
1035 #define MSIX_PBA_PEND_SHIFT 0
1036 #define MSIX_PBA_PEND_ENTRY7 0x00000080
1037 #define MSIX_PBA_PEND_ENTRY6 0x00000040
1038 #define MSIX_PBA_PEND_ENTRY5 0x00000020
1039 #define MSIX_PBA_PEND_ENTRY4 0x00000010
1040 #define MSIX_PBA_PEND_ENTRY3 0x00000008
1041 #define MSIX_PBA_PEND_ENTRY2 0x00000004
1042 #define MSIX_PBA_PEND_ENTRY1 0x00000002
1043 #define MSIX_PBA_PEND_ENTRY0 0x00000001
1044
1045 #define JME_PHY_OUI 0x001B8C
1046 #define JME_PHY_MODEL 0x21
1047 #define JME_PHY_REV 0x01
1048 #define JME_PHY_ADDR 1
1049
1050 /* JMC250 shadow status block. */
1051 struct jme_ssb {
1052 uint32_t dw0;
1053 uint32_t dw1;
1054 uint32_t dw2;
1055 uint32_t dw3;
1056 uint32_t dw4;
1057 uint32_t dw5;
1058 uint32_t dw6;
1059 uint32_t dw7;
1060 };
1061
1062 /* JMC250 descriptor structures. */
1063 struct jme_desc {
1064 uint32_t flags;
1065 uint32_t buflen;
1066 uint32_t addr_hi;
1067 uint32_t addr_lo;
1068 };
1069
1070 #define JME_TD_OWN 0x80000000
1071 #define JME_TD_INTR 0x40000000
1072 #define JME_TD_64BIT 0x20000000
1073 #define JME_TD_TCPCSUM 0x10000000
1074 #define JME_TD_UDPCSUM 0x08000000
1075 #define JME_TD_IPCSUM 0x04000000
1076 #define JME_TD_TSO 0x02000000
1077 #define JME_TD_VLAN_TAG 0x01000000
1078 #define JME_TD_VLAN_MASK 0x0000FFFF
1079
1080 #define JME_TD_MSS_MASK 0xFFFC0000
1081 #define JME_TD_MSS_SHIFT 18
1082 #define JME_TD_BUF_LEN_MASK 0x0000FFFF
1083 #define JME_TD_BUF_LEN_SHIFT 0
1084
1085 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF
1086 #define JME_TD_FRAME_LEN_SHIFT 0
1087
1088 /*
1089 * Only the first Tx descriptor of a packet is updated
1090 * after packet transmission.
1091 */
1092 #define JME_TD_TMOUT 0x20000000
1093 #define JME_TD_RETRY_EXP 0x10000000
1094 #define JME_TD_COLLISION 0x08000000
1095 #define JME_TD_UNDERRUN 0x04000000
1096 #define JME_TD_EHDR_SIZE_MASK 0x000000FF
1097 #define JME_TD_EHDR_SIZE_SHIFT 0
1098
1099 #define JME_TD_SEG_CNT_MASK 0xFFFF0000
1100 #define JME_TD_SEG_CNT_SHIFT 16
1101 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF
1102 #define JME_TD_RETRY_CNT_SHIFT 0
1103
1104 #define JME_RD_OWN 0x80000000
1105 #define JME_RD_INTR 0x40000000
1106 #define JME_RD_64BIT 0x20000000
1107
1108 #define JME_RD_BUF_LEN_MASK 0x0000FFFF
1109 #define JME_RD_BUF_LEN_SHIFT 0
1110
1111 /*
1112 * Only the first Rx descriptor of a packet is updated
1113 * after packet reception.
1114 */
1115 #define JME_RD_MORE_FRAG 0x20000000
1116 #define JME_RD_TCP 0x10000000
1117 #define JME_RD_UDP 0x08000000
1118 #define JME_RD_IPCSUM 0x04000000
1119 #define JME_RD_TCPCSUM 0x02000000
1120 #define JME_RD_UDPCSUM 0x01000000
1121 #define JME_RD_VLAN_TAG 0x00800000
1122 #define JME_RD_IPV4 0x00400000
1123 #define JME_RD_IPV6 0x00200000
1124 #define JME_RD_PAUSE 0x00100000
1125 #define JME_RD_MAGIC 0x00080000
1126 #define JME_RD_WAKEUP 0x00040000
1127 #define JME_RD_BCAST 0x00030000
1128 #define JME_RD_MCAST 0x00020000
1129 #define JME_RD_UCAST 0x00010000
1130 #define JME_RD_VLAN_MASK 0x0000FFFF
1131 #define JME_RD_VLAN_SHIFT 0
1132
1133 #define JME_RD_VALID 0x80000000
1134 #define JME_RD_CNT_MASK 0x7F000000
1135 #define JME_RD_CNT_SHIFT 24
1136 #define JME_RD_GIANT 0x00800000
1137 #define JME_RD_GMII_ERR 0x00400000
1138 #define JME_RD_NBL_RCVD 0x00200000
1139 #define JME_RD_COLL 0x00100000
1140 #define JME_RD_ABORT 0x00080000
1141 #define JME_RD_RUNT 0x00040000
1142 #define JME_RD_FIFO_OVRN 0x00020000
1143 #define JME_RD_CRC_ERR 0x00010000
1144 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF
1145
1146 #define JME_RX_ERR_STAT \
1147 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \
1148 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \
1149 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
1150
1151 #define JME_RD_ERR_MASK 0x00FF0000
1152 #define JME_RD_ERR_SHIFT 16
1153 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
1154 #define JME_RX_ERR_BITS "\2" \
1155 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \
1156 "\5COLL\6NBLRCVD\7GMIIERR\1"
1157
1158 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
1159 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK)
1160 #define JME_RX_PAD_BYTES 10
1161
1162 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF
1163
1164 #define JME_RD_RSS_HASH_MASK 0x00003F00
1165 #define JME_RD_RSS_HASH_SHIFT 8
1166 #define JME_RD_RSS_HASH_NONE 0x00000000
1167 #define JME_RD_RSS_HASH_IPV4 0x00000100
1168 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200
1169 #define JME_RD_RSS_HASH_IPV6 0x00000400
1170 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000
1171 #define JME_RD_HASH_FN_NONE 0x00000000
1172 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001
1173
1174 #endif
Cache object: caa7b178db90143497af9554e30537c2
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