FreeBSD/Linux Kernel Cross Reference
sys/dev/lge/if_lge.c
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/5.3/sys/dev/lge/if_lge.c 133691 2004-08-13 23:18:01Z rwatson $");
36
37 /*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
55 *
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
60 * hardware support.
61 *
62 * Special thanks to:
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
70 */
71
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
75 #include <sys/mbuf.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
80
81 #include <net/if.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86
87 #include <net/bpf.h>
88
89 #include <vm/vm.h> /* for vtophys */
90 #include <vm/pmap.h> /* for vtophys */
91 #include <machine/clock.h> /* for DELAY */
92 #include <machine/bus_pio.h>
93 #include <machine/bus_memio.h>
94 #include <machine/bus.h>
95 #include <machine/resource.h>
96 #include <sys/bus.h>
97 #include <sys/rman.h>
98
99 #include <dev/mii/mii.h>
100 #include <dev/mii/miivar.h>
101
102 #include <dev/pci/pcireg.h>
103 #include <dev/pci/pcivar.h>
104
105 #define LGE_USEIOSPACE
106
107 #include <dev/lge/if_lgereg.h>
108
109 /* "controller miibus0" required. See GENERIC if you get errors here. */
110 #include "miibus_if.h"
111
112 /*
113 * Various supported device vendors/types and their names.
114 */
115 static struct lge_type lge_devs[] = {
116 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
117 { 0, 0, NULL }
118 };
119
120 static int lge_probe(device_t);
121 static int lge_attach(device_t);
122 static int lge_detach(device_t);
123
124 static int lge_alloc_jumbo_mem(struct lge_softc *);
125 static void lge_free_jumbo_mem(struct lge_softc *);
126 static void *lge_jalloc(struct lge_softc *);
127 static void lge_jfree(void *, void *);
128
129 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
130 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
131 static void lge_rxeof(struct lge_softc *, int);
132 static void lge_rxeoc(struct lge_softc *);
133 static void lge_txeof(struct lge_softc *);
134 static void lge_intr(void *);
135 static void lge_tick(void *);
136 static void lge_start(struct ifnet *);
137 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
138 static void lge_init(void *);
139 static void lge_stop(struct lge_softc *);
140 static void lge_watchdog(struct ifnet *);
141 static void lge_shutdown(device_t);
142 static int lge_ifmedia_upd(struct ifnet *);
143 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
144
145 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
146 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
147
148 static int lge_miibus_readreg(device_t, int, int);
149 static int lge_miibus_writereg(device_t, int, int, int);
150 static void lge_miibus_statchg(device_t);
151
152 static void lge_setmulti(struct lge_softc *);
153 static void lge_reset(struct lge_softc *);
154 static int lge_list_rx_init(struct lge_softc *);
155 static int lge_list_tx_init(struct lge_softc *);
156
157 #ifdef LGE_USEIOSPACE
158 #define LGE_RES SYS_RES_IOPORT
159 #define LGE_RID LGE_PCI_LOIO
160 #else
161 #define LGE_RES SYS_RES_MEMORY
162 #define LGE_RID LGE_PCI_LOMEM
163 #endif
164
165 static device_method_t lge_methods[] = {
166 /* Device interface */
167 DEVMETHOD(device_probe, lge_probe),
168 DEVMETHOD(device_attach, lge_attach),
169 DEVMETHOD(device_detach, lge_detach),
170 DEVMETHOD(device_shutdown, lge_shutdown),
171
172 /* bus interface */
173 DEVMETHOD(bus_print_child, bus_generic_print_child),
174 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
175
176 /* MII interface */
177 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
178 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
179 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
180
181 { 0, 0 }
182 };
183
184 static driver_t lge_driver = {
185 "lge",
186 lge_methods,
187 sizeof(struct lge_softc)
188 };
189
190 static devclass_t lge_devclass;
191
192 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
194 MODULE_DEPEND(lge, pci, 1, 1, 1);
195 MODULE_DEPEND(lge, ether, 1, 1, 1);
196 MODULE_DEPEND(lge, miibus, 1, 1, 1);
197
198 #define LGE_SETBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) | (x))
201
202 #define LGE_CLRBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, \
204 CSR_READ_4(sc, reg) & ~(x))
205
206 #define SIO_SET(x) \
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208
209 #define SIO_CLR(x) \
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
211
212 /*
213 * Read a word of data stored in the EEPROM at address 'addr.'
214 */
215 static void
216 lge_eeprom_getword(sc, addr, dest)
217 struct lge_softc *sc;
218 int addr;
219 u_int16_t *dest;
220 {
221 register int i;
222 u_int32_t val;
223
224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
226
227 for (i = 0; i < LGE_TIMEOUT; i++)
228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
229 break;
230
231 if (i == LGE_TIMEOUT) {
232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
233 return;
234 }
235
236 val = CSR_READ_4(sc, LGE_EEDATA);
237
238 if (addr & 1)
239 *dest = (val >> 16) & 0xFFFF;
240 else
241 *dest = val & 0xFFFF;
242
243 return;
244 }
245
246 /*
247 * Read a sequence of words from the EEPROM.
248 */
249 static void
250 lge_read_eeprom(sc, dest, off, cnt, swap)
251 struct lge_softc *sc;
252 caddr_t dest;
253 int off;
254 int cnt;
255 int swap;
256 {
257 int i;
258 u_int16_t word = 0, *ptr;
259
260 for (i = 0; i < cnt; i++) {
261 lge_eeprom_getword(sc, off + i, &word);
262 ptr = (u_int16_t *)(dest + (i * 2));
263 if (swap)
264 *ptr = ntohs(word);
265 else
266 *ptr = word;
267 }
268
269 return;
270 }
271
272 static int
273 lge_miibus_readreg(dev, phy, reg)
274 device_t dev;
275 int phy, reg;
276 {
277 struct lge_softc *sc;
278 int i;
279
280 sc = device_get_softc(dev);
281
282 /*
283 * If we have a non-PCS PHY, pretend that the internal
284 * autoneg stuff at PHY address 0 isn't there so that
285 * the miibus code will find only the GMII PHY.
286 */
287 if (sc->lge_pcs == 0 && phy == 0)
288 return(0);
289
290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
291
292 for (i = 0; i < LGE_TIMEOUT; i++)
293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
294 break;
295
296 if (i == LGE_TIMEOUT) {
297 printf("lge%d: PHY read timed out\n", sc->lge_unit);
298 return(0);
299 }
300
301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
302 }
303
304 static int
305 lge_miibus_writereg(dev, phy, reg, data)
306 device_t dev;
307 int phy, reg, data;
308 {
309 struct lge_softc *sc;
310 int i;
311
312 sc = device_get_softc(dev);
313
314 CSR_WRITE_4(sc, LGE_GMIICTL,
315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
316
317 for (i = 0; i < LGE_TIMEOUT; i++)
318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
319 break;
320
321 if (i == LGE_TIMEOUT) {
322 printf("lge%d: PHY write timed out\n", sc->lge_unit);
323 return(0);
324 }
325
326 return(0);
327 }
328
329 static void
330 lge_miibus_statchg(dev)
331 device_t dev;
332 {
333 struct lge_softc *sc;
334 struct mii_data *mii;
335
336 sc = device_get_softc(dev);
337 mii = device_get_softc(sc->lge_miibus);
338
339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
340 switch (IFM_SUBTYPE(mii->mii_media_active)) {
341 case IFM_1000_T:
342 case IFM_1000_SX:
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
344 break;
345 case IFM_100_TX:
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
347 break;
348 case IFM_10_T:
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
350 break;
351 default:
352 /*
353 * Choose something, even if it's wrong. Clearing
354 * all the bits will hose autoneg on the internal
355 * PHY.
356 */
357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
358 break;
359 }
360
361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
363 } else {
364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
365 }
366
367 return;
368 }
369
370 static void
371 lge_setmulti(sc)
372 struct lge_softc *sc;
373 {
374 struct ifnet *ifp;
375 struct ifmultiaddr *ifma;
376 u_int32_t h = 0, hashes[2] = { 0, 0 };
377
378 ifp = &sc->arpcom.ac_if;
379
380 /* Make sure multicast hash table is enabled. */
381 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
382
383 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
384 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
385 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
386 return;
387 }
388
389 /* first, zot all the existing hash bits */
390 CSR_WRITE_4(sc, LGE_MAR0, 0);
391 CSR_WRITE_4(sc, LGE_MAR1, 0);
392
393 /* now program new ones */
394 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
395 if (ifma->ifma_addr->sa_family != AF_LINK)
396 continue;
397 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
398 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
399 if (h < 32)
400 hashes[0] |= (1 << h);
401 else
402 hashes[1] |= (1 << (h - 32));
403 }
404
405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
407
408 return;
409 }
410
411 static void
412 lge_reset(sc)
413 struct lge_softc *sc;
414 {
415 register int i;
416
417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
418
419 for (i = 0; i < LGE_TIMEOUT; i++) {
420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
421 break;
422 }
423
424 if (i == LGE_TIMEOUT)
425 printf("lge%d: reset never completed\n", sc->lge_unit);
426
427 /* Wait a little while for the chip to get its brains in order. */
428 DELAY(1000);
429
430 return;
431 }
432
433 /*
434 * Probe for a Level 1 chip. Check the PCI vendor and device
435 * IDs against our list and return a device name if we find a match.
436 */
437 static int
438 lge_probe(dev)
439 device_t dev;
440 {
441 struct lge_type *t;
442
443 t = lge_devs;
444
445 while(t->lge_name != NULL) {
446 if ((pci_get_vendor(dev) == t->lge_vid) &&
447 (pci_get_device(dev) == t->lge_did)) {
448 device_set_desc(dev, t->lge_name);
449 return(0);
450 }
451 t++;
452 }
453
454 return(ENXIO);
455 }
456
457 /*
458 * Attach the interface. Allocate softc structures, do ifmedia
459 * setup and ethernet/BPF attach.
460 */
461 static int
462 lge_attach(dev)
463 device_t dev;
464 {
465 int s;
466 u_char eaddr[ETHER_ADDR_LEN];
467 struct lge_softc *sc;
468 struct ifnet *ifp;
469 int unit, error = 0, rid;
470
471 s = splimp();
472
473 sc = device_get_softc(dev);
474 unit = device_get_unit(dev);
475 bzero(sc, sizeof(struct lge_softc));
476 /*
477 * Map control/status registers.
478 */
479 pci_enable_busmaster(dev);
480
481 rid = LGE_RID;
482 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
483
484 if (sc->lge_res == NULL) {
485 printf("lge%d: couldn't map ports/memory\n", unit);
486 error = ENXIO;
487 goto fail;
488 }
489
490 sc->lge_btag = rman_get_bustag(sc->lge_res);
491 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
492
493 /* Allocate interrupt */
494 rid = 0;
495 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
496 RF_SHAREABLE | RF_ACTIVE);
497
498 if (sc->lge_irq == NULL) {
499 printf("lge%d: couldn't map interrupt\n", unit);
500 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
501 error = ENXIO;
502 goto fail;
503 }
504
505 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
506 lge_intr, sc, &sc->lge_intrhand);
507
508 if (error) {
509 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
510 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
511 printf("lge%d: couldn't set up irq\n", unit);
512 goto fail;
513 }
514
515 /* Reset the adapter. */
516 lge_reset(sc);
517
518 /*
519 * Get station address from the EEPROM.
520 */
521 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
522 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
523 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
524
525 sc->lge_unit = unit;
526 callout_handle_init(&sc->lge_stat_ch);
527 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
528
529 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
530 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
531
532 if (sc->lge_ldata == NULL) {
533 printf("lge%d: no memory for list buffers!\n", unit);
534 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
535 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
536 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
537 error = ENXIO;
538 goto fail;
539 }
540 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
541
542 /* Try to allocate memory for jumbo buffers. */
543 if (lge_alloc_jumbo_mem(sc)) {
544 printf("lge%d: jumbo buffer allocation failed\n",
545 sc->lge_unit);
546 contigfree(sc->lge_ldata,
547 sizeof(struct lge_list_data), M_DEVBUF);
548 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
551 error = ENXIO;
552 goto fail;
553 }
554
555 ifp = &sc->arpcom.ac_if;
556 ifp->if_softc = sc;
557 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
558 ifp->if_mtu = ETHERMTU;
559 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
560 IFF_NEEDSGIANT;
561 ifp->if_ioctl = lge_ioctl;
562 ifp->if_start = lge_start;
563 ifp->if_watchdog = lge_watchdog;
564 ifp->if_init = lge_init;
565 ifp->if_baudrate = 1000000000;
566 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
567 ifp->if_capabilities = IFCAP_RXCSUM;
568 ifp->if_capenable = ifp->if_capabilities;
569
570 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
571 sc->lge_pcs = 1;
572 else
573 sc->lge_pcs = 0;
574
575 /*
576 * Do MII setup.
577 */
578 if (mii_phy_probe(dev, &sc->lge_miibus,
579 lge_ifmedia_upd, lge_ifmedia_sts)) {
580 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
581 contigfree(sc->lge_ldata,
582 sizeof(struct lge_list_data), M_DEVBUF);
583 lge_free_jumbo_mem(sc);
584 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
585 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
586 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
587 error = ENXIO;
588 goto fail;
589 }
590
591 /*
592 * Call MI attach routine.
593 */
594 ether_ifattach(ifp, eaddr);
595 callout_handle_init(&sc->lge_stat_ch);
596
597 fail:
598 splx(s);
599 return(error);
600 }
601
602 static int
603 lge_detach(dev)
604 device_t dev;
605 {
606 struct lge_softc *sc;
607 struct ifnet *ifp;
608 int s;
609
610 s = splimp();
611
612 sc = device_get_softc(dev);
613 ifp = &sc->arpcom.ac_if;
614
615 lge_reset(sc);
616 lge_stop(sc);
617 ether_ifdetach(ifp);
618
619 bus_generic_detach(dev);
620 device_delete_child(dev, sc->lge_miibus);
621
622 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
623 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
624 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
625
626 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
627 lge_free_jumbo_mem(sc);
628
629 splx(s);
630
631 return(0);
632 }
633
634 /*
635 * Initialize the transmit descriptors.
636 */
637 static int
638 lge_list_tx_init(sc)
639 struct lge_softc *sc;
640 {
641 struct lge_list_data *ld;
642 struct lge_ring_data *cd;
643 int i;
644
645 cd = &sc->lge_cdata;
646 ld = sc->lge_ldata;
647 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
648 ld->lge_tx_list[i].lge_mbuf = NULL;
649 ld->lge_tx_list[i].lge_ctl = 0;
650 }
651
652 cd->lge_tx_prod = cd->lge_tx_cons = 0;
653
654 return(0);
655 }
656
657
658 /*
659 * Initialize the RX descriptors and allocate mbufs for them. Note that
660 * we arralge the descriptors in a closed ring, so that the last descriptor
661 * points back to the first.
662 */
663 static int
664 lge_list_rx_init(sc)
665 struct lge_softc *sc;
666 {
667 struct lge_list_data *ld;
668 struct lge_ring_data *cd;
669 int i;
670
671 ld = sc->lge_ldata;
672 cd = &sc->lge_cdata;
673
674 cd->lge_rx_prod = cd->lge_rx_cons = 0;
675
676 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
677
678 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
679 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
680 break;
681 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
682 return(ENOBUFS);
683 }
684
685 /* Clear possible 'rx command queue empty' interrupt. */
686 CSR_READ_4(sc, LGE_ISR);
687
688 return(0);
689 }
690
691 /*
692 * Initialize an RX descriptor and attach an MBUF cluster.
693 */
694 static int
695 lge_newbuf(sc, c, m)
696 struct lge_softc *sc;
697 struct lge_rx_desc *c;
698 struct mbuf *m;
699 {
700 struct mbuf *m_new = NULL;
701 caddr_t *buf = NULL;
702
703 if (m == NULL) {
704 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
705 if (m_new == NULL) {
706 printf("lge%d: no memory for rx list "
707 "-- packet dropped!\n", sc->lge_unit);
708 return(ENOBUFS);
709 }
710
711 /* Allocate the jumbo buffer */
712 buf = lge_jalloc(sc);
713 if (buf == NULL) {
714 #ifdef LGE_VERBOSE
715 printf("lge%d: jumbo allocation failed "
716 "-- packet dropped!\n", sc->lge_unit);
717 #endif
718 m_freem(m_new);
719 return(ENOBUFS);
720 }
721 /* Attach the buffer to the mbuf */
722 m_new->m_data = (void *)buf;
723 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
724 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
725 (struct lge_softc *)sc, 0, EXT_NET_DRV);
726 } else {
727 m_new = m;
728 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
729 m_new->m_data = m_new->m_ext.ext_buf;
730 }
731
732 /*
733 * Adjust alignment so packet payload begins on a
734 * longword boundary. Mandatory for Alpha, useful on
735 * x86 too.
736 */
737 m_adj(m_new, ETHER_ALIGN);
738
739 c->lge_mbuf = m_new;
740 c->lge_fragptr_hi = 0;
741 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
742 c->lge_fraglen = m_new->m_len;
743 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
744 c->lge_sts = 0;
745
746 /*
747 * Put this buffer in the RX command FIFO. To do this,
748 * we just write the physical address of the descriptor
749 * into the RX descriptor address registers. Note that
750 * there are two registers, one high DWORD and one low
751 * DWORD, which lets us specify a 64-bit address if
752 * desired. We only use a 32-bit address for now.
753 * Writing to the low DWORD register is what actually
754 * causes the command to be issued, so we do that
755 * last.
756 */
757 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
758 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
759
760 return(0);
761 }
762
763 static int
764 lge_alloc_jumbo_mem(sc)
765 struct lge_softc *sc;
766 {
767 caddr_t ptr;
768 register int i;
769 struct lge_jpool_entry *entry;
770
771 /* Grab a big chunk o' storage. */
772 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
773 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
774
775 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
776 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
777 return(ENOBUFS);
778 }
779
780 SLIST_INIT(&sc->lge_jfree_listhead);
781 SLIST_INIT(&sc->lge_jinuse_listhead);
782
783 /*
784 * Now divide it up into 9K pieces and save the addresses
785 * in an array.
786 */
787 ptr = sc->lge_cdata.lge_jumbo_buf;
788 for (i = 0; i < LGE_JSLOTS; i++) {
789 sc->lge_cdata.lge_jslots[i] = ptr;
790 ptr += LGE_JLEN;
791 entry = malloc(sizeof(struct lge_jpool_entry),
792 M_DEVBUF, M_NOWAIT);
793 if (entry == NULL) {
794 printf("lge%d: no memory for jumbo "
795 "buffer queue!\n", sc->lge_unit);
796 return(ENOBUFS);
797 }
798 entry->slot = i;
799 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
800 entry, jpool_entries);
801 }
802
803 return(0);
804 }
805
806 static void
807 lge_free_jumbo_mem(sc)
808 struct lge_softc *sc;
809 {
810 int i;
811 struct lge_jpool_entry *entry;
812
813 for (i = 0; i < LGE_JSLOTS; i++) {
814 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
815 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
816 free(entry, M_DEVBUF);
817 }
818
819 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
820
821 return;
822 }
823
824 /*
825 * Allocate a jumbo buffer.
826 */
827 static void *
828 lge_jalloc(sc)
829 struct lge_softc *sc;
830 {
831 struct lge_jpool_entry *entry;
832
833 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
834
835 if (entry == NULL) {
836 #ifdef LGE_VERBOSE
837 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
838 #endif
839 return(NULL);
840 }
841
842 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
843 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
844 return(sc->lge_cdata.lge_jslots[entry->slot]);
845 }
846
847 /*
848 * Release a jumbo buffer.
849 */
850 static void
851 lge_jfree(buf, args)
852 void *buf;
853 void *args;
854 {
855 struct lge_softc *sc;
856 int i;
857 struct lge_jpool_entry *entry;
858
859 /* Extract the softc struct pointer. */
860 sc = args;
861
862 if (sc == NULL)
863 panic("lge_jfree: can't find softc pointer!");
864
865 /* calculate the slot this buffer belongs to */
866 i = ((vm_offset_t)buf
867 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
868
869 if ((i < 0) || (i >= LGE_JSLOTS))
870 panic("lge_jfree: asked to free buffer that we don't manage!");
871
872 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
873 if (entry == NULL)
874 panic("lge_jfree: buffer not in use!");
875 entry->slot = i;
876 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
877 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
878
879 return;
880 }
881
882 /*
883 * A frame has been uploaded: pass the resulting mbuf chain up to
884 * the higher level protocols.
885 */
886 static void
887 lge_rxeof(sc, cnt)
888 struct lge_softc *sc;
889 int cnt;
890 {
891 struct mbuf *m;
892 struct ifnet *ifp;
893 struct lge_rx_desc *cur_rx;
894 int c, i, total_len = 0;
895 u_int32_t rxsts, rxctl;
896
897 ifp = &sc->arpcom.ac_if;
898
899 /* Find out how many frames were processed. */
900 c = cnt;
901 i = sc->lge_cdata.lge_rx_cons;
902
903 /* Suck them in. */
904 while(c) {
905 struct mbuf *m0 = NULL;
906
907 cur_rx = &sc->lge_ldata->lge_rx_list[i];
908 rxctl = cur_rx->lge_ctl;
909 rxsts = cur_rx->lge_sts;
910 m = cur_rx->lge_mbuf;
911 cur_rx->lge_mbuf = NULL;
912 total_len = LGE_RXBYTES(cur_rx);
913 LGE_INC(i, LGE_RX_LIST_CNT);
914 c--;
915
916 /*
917 * If an error occurs, update stats, clear the
918 * status word and leave the mbuf cluster in place:
919 * it should simply get re-used next time this descriptor
920 * comes up in the ring.
921 */
922 if (rxctl & LGE_RXCTL_ERRMASK) {
923 ifp->if_ierrors++;
924 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
925 continue;
926 }
927
928 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
930 ifp, NULL);
931 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
932 if (m0 == NULL) {
933 printf("lge%d: no receive buffers "
934 "available -- packet dropped!\n",
935 sc->lge_unit);
936 ifp->if_ierrors++;
937 continue;
938 }
939 m = m0;
940 } else {
941 m->m_pkthdr.rcvif = ifp;
942 m->m_pkthdr.len = m->m_len = total_len;
943 }
944
945 ifp->if_ipackets++;
946
947 /* Do IP checksum checking. */
948 if (rxsts & LGE_RXSTS_ISIP)
949 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
950 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
951 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
952 if ((rxsts & LGE_RXSTS_ISTCP &&
953 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
954 (rxsts & LGE_RXSTS_ISUDP &&
955 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
956 m->m_pkthdr.csum_flags |=
957 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
958 m->m_pkthdr.csum_data = 0xffff;
959 }
960
961 (*ifp->if_input)(ifp, m);
962 }
963
964 sc->lge_cdata.lge_rx_cons = i;
965
966 return;
967 }
968
969 static void
970 lge_rxeoc(sc)
971 struct lge_softc *sc;
972 {
973 struct ifnet *ifp;
974
975 ifp = &sc->arpcom.ac_if;
976 ifp->if_flags &= ~IFF_RUNNING;
977 lge_init(sc);
978 return;
979 }
980
981 /*
982 * A frame was downloaded to the chip. It's safe for us to clean up
983 * the list buffers.
984 */
985
986 static void
987 lge_txeof(sc)
988 struct lge_softc *sc;
989 {
990 struct lge_tx_desc *cur_tx = NULL;
991 struct ifnet *ifp;
992 u_int32_t idx, txdone;
993
994 ifp = &sc->arpcom.ac_if;
995
996 /* Clear the timeout timer. */
997 ifp->if_timer = 0;
998
999 /*
1000 * Go through our tx list and free mbufs for those
1001 * frames that have been transmitted.
1002 */
1003 idx = sc->lge_cdata.lge_tx_cons;
1004 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1005
1006 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1007 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1008
1009 ifp->if_opackets++;
1010 if (cur_tx->lge_mbuf != NULL) {
1011 m_freem(cur_tx->lge_mbuf);
1012 cur_tx->lge_mbuf = NULL;
1013 }
1014 cur_tx->lge_ctl = 0;
1015
1016 txdone--;
1017 LGE_INC(idx, LGE_TX_LIST_CNT);
1018 ifp->if_timer = 0;
1019 }
1020
1021 sc->lge_cdata.lge_tx_cons = idx;
1022
1023 if (cur_tx != NULL)
1024 ifp->if_flags &= ~IFF_OACTIVE;
1025
1026 return;
1027 }
1028
1029 static void
1030 lge_tick(xsc)
1031 void *xsc;
1032 {
1033 struct lge_softc *sc;
1034 struct mii_data *mii;
1035 struct ifnet *ifp;
1036 int s;
1037
1038 s = splimp();
1039
1040 sc = xsc;
1041 ifp = &sc->arpcom.ac_if;
1042
1043 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1044 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1045 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1046 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1047
1048 if (!sc->lge_link) {
1049 mii = device_get_softc(sc->lge_miibus);
1050 mii_tick(mii);
1051 if (mii->mii_media_status & IFM_ACTIVE &&
1052 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1053 sc->lge_link++;
1054 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1055 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1056 printf("lge%d: gigabit link up\n",
1057 sc->lge_unit);
1058 if (ifp->if_snd.ifq_head != NULL)
1059 lge_start(ifp);
1060 }
1061 }
1062
1063 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1064
1065 splx(s);
1066
1067 return;
1068 }
1069
1070 static void
1071 lge_intr(arg)
1072 void *arg;
1073 {
1074 struct lge_softc *sc;
1075 struct ifnet *ifp;
1076 u_int32_t status;
1077
1078 sc = arg;
1079 ifp = &sc->arpcom.ac_if;
1080
1081 /* Supress unwanted interrupts */
1082 if (!(ifp->if_flags & IFF_UP)) {
1083 lge_stop(sc);
1084 return;
1085 }
1086
1087 for (;;) {
1088 /*
1089 * Reading the ISR register clears all interrupts, and
1090 * clears the 'interrupts enabled' bit in the IMR
1091 * register.
1092 */
1093 status = CSR_READ_4(sc, LGE_ISR);
1094
1095 if ((status & LGE_INTRS) == 0)
1096 break;
1097
1098 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1099 lge_txeof(sc);
1100
1101 if (status & LGE_ISR_RXDMA_DONE)
1102 lge_rxeof(sc, LGE_RX_DMACNT(status));
1103
1104 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1105 lge_rxeoc(sc);
1106
1107 if (status & LGE_ISR_PHY_INTR) {
1108 sc->lge_link = 0;
1109 untimeout(lge_tick, sc, sc->lge_stat_ch);
1110 lge_tick(sc);
1111 }
1112 }
1113
1114 /* Re-enable interrupts. */
1115 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1116
1117 if (ifp->if_snd.ifq_head != NULL)
1118 lge_start(ifp);
1119
1120 return;
1121 }
1122
1123 /*
1124 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1125 * pointers to the fragment pointers.
1126 */
1127 static int
1128 lge_encap(sc, m_head, txidx)
1129 struct lge_softc *sc;
1130 struct mbuf *m_head;
1131 u_int32_t *txidx;
1132 {
1133 struct lge_frag *f = NULL;
1134 struct lge_tx_desc *cur_tx;
1135 struct mbuf *m;
1136 int frag = 0, tot_len = 0;
1137
1138 /*
1139 * Start packing the mbufs in this chain into
1140 * the fragment pointers. Stop when we run out
1141 * of fragments or hit the end of the mbuf chain.
1142 */
1143 m = m_head;
1144 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1145 frag = 0;
1146
1147 for (m = m_head; m != NULL; m = m->m_next) {
1148 if (m->m_len != 0) {
1149 tot_len += m->m_len;
1150 f = &cur_tx->lge_frags[frag];
1151 f->lge_fraglen = m->m_len;
1152 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1153 f->lge_fragptr_hi = 0;
1154 frag++;
1155 }
1156 }
1157
1158 if (m != NULL)
1159 return(ENOBUFS);
1160
1161 cur_tx->lge_mbuf = m_head;
1162 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1163 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1164
1165 /* Queue for transmit */
1166 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1167
1168 return(0);
1169 }
1170
1171 /*
1172 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1173 * to the mbuf data regions directly in the transmit lists. We also save a
1174 * copy of the pointers since the transmit list fragment pointers are
1175 * physical addresses.
1176 */
1177
1178 static void
1179 lge_start(ifp)
1180 struct ifnet *ifp;
1181 {
1182 struct lge_softc *sc;
1183 struct mbuf *m_head = NULL;
1184 u_int32_t idx;
1185
1186 sc = ifp->if_softc;
1187
1188 if (!sc->lge_link)
1189 return;
1190
1191 idx = sc->lge_cdata.lge_tx_prod;
1192
1193 if (ifp->if_flags & IFF_OACTIVE)
1194 return;
1195
1196 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1197 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1198 break;
1199
1200 IF_DEQUEUE(&ifp->if_snd, m_head);
1201 if (m_head == NULL)
1202 break;
1203
1204 if (lge_encap(sc, m_head, &idx)) {
1205 IF_PREPEND(&ifp->if_snd, m_head);
1206 ifp->if_flags |= IFF_OACTIVE;
1207 break;
1208 }
1209
1210 /*
1211 * If there's a BPF listener, bounce a copy of this frame
1212 * to him.
1213 */
1214 BPF_MTAP(ifp, m_head);
1215 }
1216
1217 sc->lge_cdata.lge_tx_prod = idx;
1218
1219 /*
1220 * Set a timeout in case the chip goes out to lunch.
1221 */
1222 ifp->if_timer = 5;
1223
1224 return;
1225 }
1226
1227 static void
1228 lge_init(xsc)
1229 void *xsc;
1230 {
1231 struct lge_softc *sc = xsc;
1232 struct ifnet *ifp = &sc->arpcom.ac_if;
1233 struct mii_data *mii;
1234 int s;
1235
1236 if (ifp->if_flags & IFF_RUNNING)
1237 return;
1238
1239 s = splimp();
1240
1241 /*
1242 * Cancel pending I/O and free all RX/TX buffers.
1243 */
1244 lge_stop(sc);
1245 lge_reset(sc);
1246
1247 mii = device_get_softc(sc->lge_miibus);
1248
1249 /* Set MAC address */
1250 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1251 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1252
1253 /* Init circular RX list. */
1254 if (lge_list_rx_init(sc) == ENOBUFS) {
1255 printf("lge%d: initialization failed: no "
1256 "memory for rx buffers\n", sc->lge_unit);
1257 lge_stop(sc);
1258 (void)splx(s);
1259 return;
1260 }
1261
1262 /*
1263 * Init tx descriptors.
1264 */
1265 lge_list_tx_init(sc);
1266
1267 /* Set initial value for MODE1 register. */
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1269 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1270 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1271 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1272
1273 /* If we want promiscuous mode, set the allframes bit. */
1274 if (ifp->if_flags & IFF_PROMISC) {
1275 CSR_WRITE_4(sc, LGE_MODE1,
1276 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1277 } else {
1278 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1279 }
1280
1281 /*
1282 * Set the capture broadcast bit to capture broadcast frames.
1283 */
1284 if (ifp->if_flags & IFF_BROADCAST) {
1285 CSR_WRITE_4(sc, LGE_MODE1,
1286 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1287 } else {
1288 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1289 }
1290
1291 /* Packet padding workaround? */
1292 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1293
1294 /* No error frames */
1295 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1296
1297 /* Receive large frames */
1298 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1299
1300 /* Workaround: disable RX/TX flow control */
1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1303
1304 /* Make sure to strip CRC from received frames */
1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1306
1307 /* Turn off magic packet mode */
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1309
1310 /* Turn off all VLAN stuff */
1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1312 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1313
1314 /* Workarond: FIFO overflow */
1315 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1316 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1317
1318 /*
1319 * Load the multicast filter.
1320 */
1321 lge_setmulti(sc);
1322
1323 /*
1324 * Enable hardware checksum validation for all received IPv4
1325 * packets, do not reject packets with bad checksums.
1326 */
1327 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1328 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1329 LGE_MODE2_RX_ERRCSUM);
1330
1331 /*
1332 * Enable the delivery of PHY interrupts based on
1333 * link/speed/duplex status chalges.
1334 */
1335 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1336
1337 /* Enable receiver and transmitter. */
1338 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1339 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1340
1341 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1342 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1343
1344 /*
1345 * Enable interrupts.
1346 */
1347 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1348 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1349
1350 lge_ifmedia_upd(ifp);
1351
1352 ifp->if_flags |= IFF_RUNNING;
1353 ifp->if_flags &= ~IFF_OACTIVE;
1354
1355 (void)splx(s);
1356
1357 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1358
1359 return;
1360 }
1361
1362 /*
1363 * Set media options.
1364 */
1365 static int
1366 lge_ifmedia_upd(ifp)
1367 struct ifnet *ifp;
1368 {
1369 struct lge_softc *sc;
1370 struct mii_data *mii;
1371
1372 sc = ifp->if_softc;
1373
1374 mii = device_get_softc(sc->lge_miibus);
1375 sc->lge_link = 0;
1376 if (mii->mii_instance) {
1377 struct mii_softc *miisc;
1378 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1379 miisc = LIST_NEXT(miisc, mii_list))
1380 mii_phy_reset(miisc);
1381 }
1382 mii_mediachg(mii);
1383
1384 return(0);
1385 }
1386
1387 /*
1388 * Report current media status.
1389 */
1390 static void
1391 lge_ifmedia_sts(ifp, ifmr)
1392 struct ifnet *ifp;
1393 struct ifmediareq *ifmr;
1394 {
1395 struct lge_softc *sc;
1396 struct mii_data *mii;
1397
1398 sc = ifp->if_softc;
1399
1400 mii = device_get_softc(sc->lge_miibus);
1401 mii_pollstat(mii);
1402 ifmr->ifm_active = mii->mii_media_active;
1403 ifmr->ifm_status = mii->mii_media_status;
1404
1405 return;
1406 }
1407
1408 static int
1409 lge_ioctl(ifp, command, data)
1410 struct ifnet *ifp;
1411 u_long command;
1412 caddr_t data;
1413 {
1414 struct lge_softc *sc = ifp->if_softc;
1415 struct ifreq *ifr = (struct ifreq *) data;
1416 struct mii_data *mii;
1417 int s, error = 0;
1418
1419 s = splimp();
1420
1421 switch(command) {
1422 case SIOCSIFMTU:
1423 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1424 error = EINVAL;
1425 else
1426 ifp->if_mtu = ifr->ifr_mtu;
1427 break;
1428 case SIOCSIFFLAGS:
1429 if (ifp->if_flags & IFF_UP) {
1430 if (ifp->if_flags & IFF_RUNNING &&
1431 ifp->if_flags & IFF_PROMISC &&
1432 !(sc->lge_if_flags & IFF_PROMISC)) {
1433 CSR_WRITE_4(sc, LGE_MODE1,
1434 LGE_MODE1_SETRST_CTL1|
1435 LGE_MODE1_RX_PROMISC);
1436 } else if (ifp->if_flags & IFF_RUNNING &&
1437 !(ifp->if_flags & IFF_PROMISC) &&
1438 sc->lge_if_flags & IFF_PROMISC) {
1439 CSR_WRITE_4(sc, LGE_MODE1,
1440 LGE_MODE1_RX_PROMISC);
1441 } else {
1442 ifp->if_flags &= ~IFF_RUNNING;
1443 lge_init(sc);
1444 }
1445 } else {
1446 if (ifp->if_flags & IFF_RUNNING)
1447 lge_stop(sc);
1448 }
1449 sc->lge_if_flags = ifp->if_flags;
1450 error = 0;
1451 break;
1452 case SIOCADDMULTI:
1453 case SIOCDELMULTI:
1454 lge_setmulti(sc);
1455 error = 0;
1456 break;
1457 case SIOCGIFMEDIA:
1458 case SIOCSIFMEDIA:
1459 mii = device_get_softc(sc->lge_miibus);
1460 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1461 break;
1462 default:
1463 error = ether_ioctl(ifp, command, data);
1464 break;
1465 }
1466
1467 (void)splx(s);
1468
1469 return(error);
1470 }
1471
1472 static void
1473 lge_watchdog(ifp)
1474 struct ifnet *ifp;
1475 {
1476 struct lge_softc *sc;
1477
1478 sc = ifp->if_softc;
1479
1480 ifp->if_oerrors++;
1481 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1482
1483 lge_stop(sc);
1484 lge_reset(sc);
1485 ifp->if_flags &= ~IFF_RUNNING;
1486 lge_init(sc);
1487
1488 if (ifp->if_snd.ifq_head != NULL)
1489 lge_start(ifp);
1490
1491 return;
1492 }
1493
1494 /*
1495 * Stop the adapter and free any mbufs allocated to the
1496 * RX and TX lists.
1497 */
1498 static void
1499 lge_stop(sc)
1500 struct lge_softc *sc;
1501 {
1502 register int i;
1503 struct ifnet *ifp;
1504
1505 ifp = &sc->arpcom.ac_if;
1506 ifp->if_timer = 0;
1507 untimeout(lge_tick, sc, sc->lge_stat_ch);
1508 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1509
1510 /* Disable receiver and transmitter. */
1511 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1512 sc->lge_link = 0;
1513
1514 /*
1515 * Free data in the RX lists.
1516 */
1517 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1518 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1519 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1520 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1521 }
1522 }
1523 bzero((char *)&sc->lge_ldata->lge_rx_list,
1524 sizeof(sc->lge_ldata->lge_rx_list));
1525
1526 /*
1527 * Free the TX list buffers.
1528 */
1529 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1530 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1531 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1532 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1533 }
1534 }
1535
1536 bzero((char *)&sc->lge_ldata->lge_tx_list,
1537 sizeof(sc->lge_ldata->lge_tx_list));
1538
1539 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1540
1541 return;
1542 }
1543
1544 /*
1545 * Stop all chip I/O so that the kernel's probe routines don't
1546 * get confused by errant DMAs when rebooting.
1547 */
1548 static void
1549 lge_shutdown(dev)
1550 device_t dev;
1551 {
1552 struct lge_softc *sc;
1553
1554 sc = device_get_softc(dev);
1555
1556 lge_reset(sc);
1557 lge_stop(sc);
1558
1559 return;
1560 }
Cache object: c1914c9c6a56c960372cc804b88e1492
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