Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/lge/if_lge.c
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1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 87 #include <net/bpf.h> 88 89 #include <vm/vm.h> /* for vtophys */ 90 #include <vm/pmap.h> /* for vtophys */ 91 #include <machine/clock.h> /* for DELAY */ 92 #include <machine/bus_pio.h> 93 #include <machine/bus_memio.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 #include <sys/bus.h> 97 #include <sys/rman.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/pci/pcireg.h> 103 #include <dev/pci/pcivar.h> 104 105 #define LGE_USEIOSPACE 106 107 #include <dev/lge/if_lgereg.h> 108 109 /* "controller miibus0" required. See GENERIC if you get errors here. */ 110 #include "miibus_if.h" 111 112 /* 113 * Various supported device vendors/types and their names. 114 */ 115 static struct lge_type lge_devs[] = { 116 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 117 { 0, 0, NULL } 118 }; 119 120 static int lge_probe(device_t); 121 static int lge_attach(device_t); 122 static int lge_detach(device_t); 123 124 static int lge_alloc_jumbo_mem(struct lge_softc *); 125 static void lge_free_jumbo_mem(struct lge_softc *); 126 static void *lge_jalloc(struct lge_softc *); 127 static void lge_jfree(void *, void *); 128 129 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 130 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 131 static void lge_rxeof(struct lge_softc *, int); 132 static void lge_rxeoc(struct lge_softc *); 133 static void lge_txeof(struct lge_softc *); 134 static void lge_intr(void *); 135 static void lge_tick(void *); 136 static void lge_start(struct ifnet *); 137 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 138 static void lge_init(void *); 139 static void lge_stop(struct lge_softc *); 140 static void lge_watchdog(struct ifnet *); 141 static void lge_shutdown(device_t); 142 static int lge_ifmedia_upd(struct ifnet *); 143 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 144 145 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 146 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 147 148 static int lge_miibus_readreg(device_t, int, int); 149 static int lge_miibus_writereg(device_t, int, int, int); 150 static void lge_miibus_statchg(device_t); 151 152 static void lge_setmulti(struct lge_softc *); 153 static void lge_reset(struct lge_softc *); 154 static int lge_list_rx_init(struct lge_softc *); 155 static int lge_list_tx_init(struct lge_softc *); 156 157 #ifdef LGE_USEIOSPACE 158 #define LGE_RES SYS_RES_IOPORT 159 #define LGE_RID LGE_PCI_LOIO 160 #else 161 #define LGE_RES SYS_RES_MEMORY 162 #define LGE_RID LGE_PCI_LOMEM 163 #endif 164 165 static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182 }; 183 184 static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188 }; 189 190 static devclass_t lge_devclass; 191 192 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194 MODULE_DEPEND(lge, pci, 1, 1, 1); 195 MODULE_DEPEND(lge, ether, 1, 1, 1); 196 MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198 #define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206 #define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209 #define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212 /* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215 static void 216 lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220 { 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244 } 245 246 /* 247 * Read a sequence of words from the EEPROM. 248 */ 249 static void 250 lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256 { 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270 } 271 272 static int 273 lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276 { 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302 } 303 304 static int 305 lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308 { 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327 } 328 329 static void 330 lge_miibus_statchg(dev) 331 device_t dev; 332 { 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368 } 369 370 static void 371 lge_setmulti(sc) 372 struct lge_softc *sc; 373 { 374 struct ifnet *ifp; 375 struct ifmultiaddr *ifma; 376 u_int32_t h = 0, hashes[2] = { 0, 0 }; 377 378 ifp = &sc->arpcom.ac_if; 379 380 /* Make sure multicast hash table is enabled. */ 381 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 382 383 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 384 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 385 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 386 return; 387 } 388 389 /* first, zot all the existing hash bits */ 390 CSR_WRITE_4(sc, LGE_MAR0, 0); 391 CSR_WRITE_4(sc, LGE_MAR1, 0); 392 393 /* now program new ones */ 394 IF_ADDR_LOCK(ifp); 395 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 396 if (ifma->ifma_addr->sa_family != AF_LINK) 397 continue; 398 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 399 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 400 if (h < 32) 401 hashes[0] |= (1 << h); 402 else 403 hashes[1] |= (1 << (h - 32)); 404 } 405 IF_ADDR_UNLOCK(ifp); 406 407 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 408 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 409 410 return; 411 } 412 413 static void 414 lge_reset(sc) 415 struct lge_softc *sc; 416 { 417 register int i; 418 419 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 420 421 for (i = 0; i < LGE_TIMEOUT; i++) { 422 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 423 break; 424 } 425 426 if (i == LGE_TIMEOUT) 427 printf("lge%d: reset never completed\n", sc->lge_unit); 428 429 /* Wait a little while for the chip to get its brains in order. */ 430 DELAY(1000); 431 432 return; 433 } 434 435 /* 436 * Probe for a Level 1 chip. Check the PCI vendor and device 437 * IDs against our list and return a device name if we find a match. 438 */ 439 static int 440 lge_probe(dev) 441 device_t dev; 442 { 443 struct lge_type *t; 444 445 t = lge_devs; 446 447 while(t->lge_name != NULL) { 448 if ((pci_get_vendor(dev) == t->lge_vid) && 449 (pci_get_device(dev) == t->lge_did)) { 450 device_set_desc(dev, t->lge_name); 451 return(0); 452 } 453 t++; 454 } 455 456 return(ENXIO); 457 } 458 459 /* 460 * Attach the interface. Allocate softc structures, do ifmedia 461 * setup and ethernet/BPF attach. 462 */ 463 static int 464 lge_attach(dev) 465 device_t dev; 466 { 467 int s; 468 u_char eaddr[ETHER_ADDR_LEN]; 469 struct lge_softc *sc; 470 struct ifnet *ifp; 471 int unit, error = 0, rid; 472 473 s = splimp(); 474 475 sc = device_get_softc(dev); 476 unit = device_get_unit(dev); 477 bzero(sc, sizeof(struct lge_softc)); 478 /* 479 * Map control/status registers. 480 */ 481 pci_enable_busmaster(dev); 482 483 rid = LGE_RID; 484 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 485 486 if (sc->lge_res == NULL) { 487 printf("lge%d: couldn't map ports/memory\n", unit); 488 error = ENXIO; 489 goto fail; 490 } 491 492 sc->lge_btag = rman_get_bustag(sc->lge_res); 493 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 494 495 /* Allocate interrupt */ 496 rid = 0; 497 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 498 RF_SHAREABLE | RF_ACTIVE); 499 500 if (sc->lge_irq == NULL) { 501 printf("lge%d: couldn't map interrupt\n", unit); 502 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 503 error = ENXIO; 504 goto fail; 505 } 506 507 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 508 lge_intr, sc, &sc->lge_intrhand); 509 510 if (error) { 511 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 512 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 513 printf("lge%d: couldn't set up irq\n", unit); 514 goto fail; 515 } 516 517 /* Reset the adapter. */ 518 lge_reset(sc); 519 520 /* 521 * Get station address from the EEPROM. 522 */ 523 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 524 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 525 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 526 527 sc->lge_unit = unit; 528 callout_handle_init(&sc->lge_stat_ch); 529 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 530 531 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 532 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 533 534 if (sc->lge_ldata == NULL) { 535 printf("lge%d: no memory for list buffers!\n", unit); 536 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 537 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 538 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 539 error = ENXIO; 540 goto fail; 541 } 542 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 543 544 /* Try to allocate memory for jumbo buffers. */ 545 if (lge_alloc_jumbo_mem(sc)) { 546 printf("lge%d: jumbo buffer allocation failed\n", 547 sc->lge_unit); 548 contigfree(sc->lge_ldata, 549 sizeof(struct lge_list_data), M_DEVBUF); 550 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 551 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 552 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 553 error = ENXIO; 554 goto fail; 555 } 556 557 ifp = &sc->arpcom.ac_if; 558 ifp->if_softc = sc; 559 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 560 ifp->if_mtu = ETHERMTU; 561 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 562 IFF_NEEDSGIANT; 563 ifp->if_ioctl = lge_ioctl; 564 ifp->if_start = lge_start; 565 ifp->if_watchdog = lge_watchdog; 566 ifp->if_init = lge_init; 567 ifp->if_baudrate = 1000000000; 568 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 569 ifp->if_capabilities = IFCAP_RXCSUM; 570 ifp->if_capenable = ifp->if_capabilities; 571 572 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 573 sc->lge_pcs = 1; 574 else 575 sc->lge_pcs = 0; 576 577 /* 578 * Do MII setup. 579 */ 580 if (mii_phy_probe(dev, &sc->lge_miibus, 581 lge_ifmedia_upd, lge_ifmedia_sts)) { 582 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 583 contigfree(sc->lge_ldata, 584 sizeof(struct lge_list_data), M_DEVBUF); 585 lge_free_jumbo_mem(sc); 586 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 589 error = ENXIO; 590 goto fail; 591 } 592 593 /* 594 * Call MI attach routine. 595 */ 596 ether_ifattach(ifp, eaddr); 597 callout_handle_init(&sc->lge_stat_ch); 598 599 fail: 600 splx(s); 601 return(error); 602 } 603 604 static int 605 lge_detach(dev) 606 device_t dev; 607 { 608 struct lge_softc *sc; 609 struct ifnet *ifp; 610 int s; 611 612 s = splimp(); 613 614 sc = device_get_softc(dev); 615 ifp = &sc->arpcom.ac_if; 616 617 lge_reset(sc); 618 lge_stop(sc); 619 ether_ifdetach(ifp); 620 621 bus_generic_detach(dev); 622 device_delete_child(dev, sc->lge_miibus); 623 624 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 625 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 626 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 627 628 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 629 lge_free_jumbo_mem(sc); 630 631 splx(s); 632 633 return(0); 634 } 635 636 /* 637 * Initialize the transmit descriptors. 638 */ 639 static int 640 lge_list_tx_init(sc) 641 struct lge_softc *sc; 642 { 643 struct lge_list_data *ld; 644 struct lge_ring_data *cd; 645 int i; 646 647 cd = &sc->lge_cdata; 648 ld = sc->lge_ldata; 649 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 650 ld->lge_tx_list[i].lge_mbuf = NULL; 651 ld->lge_tx_list[i].lge_ctl = 0; 652 } 653 654 cd->lge_tx_prod = cd->lge_tx_cons = 0; 655 656 return(0); 657 } 658 659 660 /* 661 * Initialize the RX descriptors and allocate mbufs for them. Note that 662 * we arralge the descriptors in a closed ring, so that the last descriptor 663 * points back to the first. 664 */ 665 static int 666 lge_list_rx_init(sc) 667 struct lge_softc *sc; 668 { 669 struct lge_list_data *ld; 670 struct lge_ring_data *cd; 671 int i; 672 673 ld = sc->lge_ldata; 674 cd = &sc->lge_cdata; 675 676 cd->lge_rx_prod = cd->lge_rx_cons = 0; 677 678 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 679 680 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 681 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 682 break; 683 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 684 return(ENOBUFS); 685 } 686 687 /* Clear possible 'rx command queue empty' interrupt. */ 688 CSR_READ_4(sc, LGE_ISR); 689 690 return(0); 691 } 692 693 /* 694 * Initialize an RX descriptor and attach an MBUF cluster. 695 */ 696 static int 697 lge_newbuf(sc, c, m) 698 struct lge_softc *sc; 699 struct lge_rx_desc *c; 700 struct mbuf *m; 701 { 702 struct mbuf *m_new = NULL; 703 caddr_t *buf = NULL; 704 705 if (m == NULL) { 706 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 707 if (m_new == NULL) { 708 printf("lge%d: no memory for rx list " 709 "-- packet dropped!\n", sc->lge_unit); 710 return(ENOBUFS); 711 } 712 713 /* Allocate the jumbo buffer */ 714 buf = lge_jalloc(sc); 715 if (buf == NULL) { 716 #ifdef LGE_VERBOSE 717 printf("lge%d: jumbo allocation failed " 718 "-- packet dropped!\n", sc->lge_unit); 719 #endif 720 m_freem(m_new); 721 return(ENOBUFS); 722 } 723 /* Attach the buffer to the mbuf */ 724 m_new->m_data = (void *)buf; 725 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 726 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 727 (struct lge_softc *)sc, 0, EXT_NET_DRV); 728 } else { 729 m_new = m; 730 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 731 m_new->m_data = m_new->m_ext.ext_buf; 732 } 733 734 /* 735 * Adjust alignment so packet payload begins on a 736 * longword boundary. Mandatory for Alpha, useful on 737 * x86 too. 738 */ 739 m_adj(m_new, ETHER_ALIGN); 740 741 c->lge_mbuf = m_new; 742 c->lge_fragptr_hi = 0; 743 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 744 c->lge_fraglen = m_new->m_len; 745 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 746 c->lge_sts = 0; 747 748 /* 749 * Put this buffer in the RX command FIFO. To do this, 750 * we just write the physical address of the descriptor 751 * into the RX descriptor address registers. Note that 752 * there are two registers, one high DWORD and one low 753 * DWORD, which lets us specify a 64-bit address if 754 * desired. We only use a 32-bit address for now. 755 * Writing to the low DWORD register is what actually 756 * causes the command to be issued, so we do that 757 * last. 758 */ 759 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 760 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 761 762 return(0); 763 } 764 765 static int 766 lge_alloc_jumbo_mem(sc) 767 struct lge_softc *sc; 768 { 769 caddr_t ptr; 770 register int i; 771 struct lge_jpool_entry *entry; 772 773 /* Grab a big chunk o' storage. */ 774 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 775 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 776 777 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 778 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 779 return(ENOBUFS); 780 } 781 782 SLIST_INIT(&sc->lge_jfree_listhead); 783 SLIST_INIT(&sc->lge_jinuse_listhead); 784 785 /* 786 * Now divide it up into 9K pieces and save the addresses 787 * in an array. 788 */ 789 ptr = sc->lge_cdata.lge_jumbo_buf; 790 for (i = 0; i < LGE_JSLOTS; i++) { 791 sc->lge_cdata.lge_jslots[i] = ptr; 792 ptr += LGE_JLEN; 793 entry = malloc(sizeof(struct lge_jpool_entry), 794 M_DEVBUF, M_NOWAIT); 795 if (entry == NULL) { 796 printf("lge%d: no memory for jumbo " 797 "buffer queue!\n", sc->lge_unit); 798 return(ENOBUFS); 799 } 800 entry->slot = i; 801 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 802 entry, jpool_entries); 803 } 804 805 return(0); 806 } 807 808 static void 809 lge_free_jumbo_mem(sc) 810 struct lge_softc *sc; 811 { 812 int i; 813 struct lge_jpool_entry *entry; 814 815 for (i = 0; i < LGE_JSLOTS; i++) { 816 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 817 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 818 free(entry, M_DEVBUF); 819 } 820 821 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 822 823 return; 824 } 825 826 /* 827 * Allocate a jumbo buffer. 828 */ 829 static void * 830 lge_jalloc(sc) 831 struct lge_softc *sc; 832 { 833 struct lge_jpool_entry *entry; 834 835 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 836 837 if (entry == NULL) { 838 #ifdef LGE_VERBOSE 839 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 840 #endif 841 return(NULL); 842 } 843 844 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 845 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 846 return(sc->lge_cdata.lge_jslots[entry->slot]); 847 } 848 849 /* 850 * Release a jumbo buffer. 851 */ 852 static void 853 lge_jfree(buf, args) 854 void *buf; 855 void *args; 856 { 857 struct lge_softc *sc; 858 int i; 859 struct lge_jpool_entry *entry; 860 861 /* Extract the softc struct pointer. */ 862 sc = args; 863 864 if (sc == NULL) 865 panic("lge_jfree: can't find softc pointer!"); 866 867 /* calculate the slot this buffer belongs to */ 868 i = ((vm_offset_t)buf 869 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 870 871 if ((i < 0) || (i >= LGE_JSLOTS)) 872 panic("lge_jfree: asked to free buffer that we don't manage!"); 873 874 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 875 if (entry == NULL) 876 panic("lge_jfree: buffer not in use!"); 877 entry->slot = i; 878 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 879 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 880 881 return; 882 } 883 884 /* 885 * A frame has been uploaded: pass the resulting mbuf chain up to 886 * the higher level protocols. 887 */ 888 static void 889 lge_rxeof(sc, cnt) 890 struct lge_softc *sc; 891 int cnt; 892 { 893 struct mbuf *m; 894 struct ifnet *ifp; 895 struct lge_rx_desc *cur_rx; 896 int c, i, total_len = 0; 897 u_int32_t rxsts, rxctl; 898 899 ifp = &sc->arpcom.ac_if; 900 901 /* Find out how many frames were processed. */ 902 c = cnt; 903 i = sc->lge_cdata.lge_rx_cons; 904 905 /* Suck them in. */ 906 while(c) { 907 struct mbuf *m0 = NULL; 908 909 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 910 rxctl = cur_rx->lge_ctl; 911 rxsts = cur_rx->lge_sts; 912 m = cur_rx->lge_mbuf; 913 cur_rx->lge_mbuf = NULL; 914 total_len = LGE_RXBYTES(cur_rx); 915 LGE_INC(i, LGE_RX_LIST_CNT); 916 c--; 917 918 /* 919 * If an error occurs, update stats, clear the 920 * status word and leave the mbuf cluster in place: 921 * it should simply get re-used next time this descriptor 922 * comes up in the ring. 923 */ 924 if (rxctl & LGE_RXCTL_ERRMASK) { 925 ifp->if_ierrors++; 926 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 927 continue; 928 } 929 930 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 931 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 932 ifp, NULL); 933 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 934 if (m0 == NULL) { 935 printf("lge%d: no receive buffers " 936 "available -- packet dropped!\n", 937 sc->lge_unit); 938 ifp->if_ierrors++; 939 continue; 940 } 941 m = m0; 942 } else { 943 m->m_pkthdr.rcvif = ifp; 944 m->m_pkthdr.len = m->m_len = total_len; 945 } 946 947 ifp->if_ipackets++; 948 949 /* Do IP checksum checking. */ 950 if (rxsts & LGE_RXSTS_ISIP) 951 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 952 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 953 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 954 if ((rxsts & LGE_RXSTS_ISTCP && 955 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 956 (rxsts & LGE_RXSTS_ISUDP && 957 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 958 m->m_pkthdr.csum_flags |= 959 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 960 m->m_pkthdr.csum_data = 0xffff; 961 } 962 963 (*ifp->if_input)(ifp, m); 964 } 965 966 sc->lge_cdata.lge_rx_cons = i; 967 968 return; 969 } 970 971 static void 972 lge_rxeoc(sc) 973 struct lge_softc *sc; 974 { 975 struct ifnet *ifp; 976 977 ifp = &sc->arpcom.ac_if; 978 ifp->if_flags &= ~IFF_RUNNING; 979 lge_init(sc); 980 return; 981 } 982 983 /* 984 * A frame was downloaded to the chip. It's safe for us to clean up 985 * the list buffers. 986 */ 987 988 static void 989 lge_txeof(sc) 990 struct lge_softc *sc; 991 { 992 struct lge_tx_desc *cur_tx = NULL; 993 struct ifnet *ifp; 994 u_int32_t idx, txdone; 995 996 ifp = &sc->arpcom.ac_if; 997 998 /* Clear the timeout timer. */ 999 ifp->if_timer = 0; 1000 1001 /* 1002 * Go through our tx list and free mbufs for those 1003 * frames that have been transmitted. 1004 */ 1005 idx = sc->lge_cdata.lge_tx_cons; 1006 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1007 1008 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1009 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1010 1011 ifp->if_opackets++; 1012 if (cur_tx->lge_mbuf != NULL) { 1013 m_freem(cur_tx->lge_mbuf); 1014 cur_tx->lge_mbuf = NULL; 1015 } 1016 cur_tx->lge_ctl = 0; 1017 1018 txdone--; 1019 LGE_INC(idx, LGE_TX_LIST_CNT); 1020 ifp->if_timer = 0; 1021 } 1022 1023 sc->lge_cdata.lge_tx_cons = idx; 1024 1025 if (cur_tx != NULL) 1026 ifp->if_flags &= ~IFF_OACTIVE; 1027 1028 return; 1029 } 1030 1031 static void 1032 lge_tick(xsc) 1033 void *xsc; 1034 { 1035 struct lge_softc *sc; 1036 struct mii_data *mii; 1037 struct ifnet *ifp; 1038 int s; 1039 1040 s = splimp(); 1041 1042 sc = xsc; 1043 ifp = &sc->arpcom.ac_if; 1044 1045 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1046 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1047 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1048 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1049 1050 if (!sc->lge_link) { 1051 mii = device_get_softc(sc->lge_miibus); 1052 mii_tick(mii); 1053 if (mii->mii_media_status & IFM_ACTIVE && 1054 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1055 sc->lge_link++; 1056 if (bootverbose && 1057 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1058 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1059 printf("lge%d: gigabit link up\n", 1060 sc->lge_unit); 1061 if (ifp->if_snd.ifq_head != NULL) 1062 lge_start(ifp); 1063 } 1064 } 1065 1066 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1067 1068 splx(s); 1069 1070 return; 1071 } 1072 1073 static void 1074 lge_intr(arg) 1075 void *arg; 1076 { 1077 struct lge_softc *sc; 1078 struct ifnet *ifp; 1079 u_int32_t status; 1080 1081 sc = arg; 1082 ifp = &sc->arpcom.ac_if; 1083 1084 /* Supress unwanted interrupts */ 1085 if (!(ifp->if_flags & IFF_UP)) { 1086 lge_stop(sc); 1087 return; 1088 } 1089 1090 for (;;) { 1091 /* 1092 * Reading the ISR register clears all interrupts, and 1093 * clears the 'interrupts enabled' bit in the IMR 1094 * register. 1095 */ 1096 status = CSR_READ_4(sc, LGE_ISR); 1097 1098 if ((status & LGE_INTRS) == 0) 1099 break; 1100 1101 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1102 lge_txeof(sc); 1103 1104 if (status & LGE_ISR_RXDMA_DONE) 1105 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1106 1107 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1108 lge_rxeoc(sc); 1109 1110 if (status & LGE_ISR_PHY_INTR) { 1111 sc->lge_link = 0; 1112 untimeout(lge_tick, sc, sc->lge_stat_ch); 1113 lge_tick(sc); 1114 } 1115 } 1116 1117 /* Re-enable interrupts. */ 1118 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1119 1120 if (ifp->if_snd.ifq_head != NULL) 1121 lge_start(ifp); 1122 1123 return; 1124 } 1125 1126 /* 1127 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1128 * pointers to the fragment pointers. 1129 */ 1130 static int 1131 lge_encap(sc, m_head, txidx) 1132 struct lge_softc *sc; 1133 struct mbuf *m_head; 1134 u_int32_t *txidx; 1135 { 1136 struct lge_frag *f = NULL; 1137 struct lge_tx_desc *cur_tx; 1138 struct mbuf *m; 1139 int frag = 0, tot_len = 0; 1140 1141 /* 1142 * Start packing the mbufs in this chain into 1143 * the fragment pointers. Stop when we run out 1144 * of fragments or hit the end of the mbuf chain. 1145 */ 1146 m = m_head; 1147 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1148 frag = 0; 1149 1150 for (m = m_head; m != NULL; m = m->m_next) { 1151 if (m->m_len != 0) { 1152 tot_len += m->m_len; 1153 f = &cur_tx->lge_frags[frag]; 1154 f->lge_fraglen = m->m_len; 1155 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1156 f->lge_fragptr_hi = 0; 1157 frag++; 1158 } 1159 } 1160 1161 if (m != NULL) 1162 return(ENOBUFS); 1163 1164 cur_tx->lge_mbuf = m_head; 1165 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1166 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1167 1168 /* Queue for transmit */ 1169 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1170 1171 return(0); 1172 } 1173 1174 /* 1175 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1176 * to the mbuf data regions directly in the transmit lists. We also save a 1177 * copy of the pointers since the transmit list fragment pointers are 1178 * physical addresses. 1179 */ 1180 1181 static void 1182 lge_start(ifp) 1183 struct ifnet *ifp; 1184 { 1185 struct lge_softc *sc; 1186 struct mbuf *m_head = NULL; 1187 u_int32_t idx; 1188 1189 sc = ifp->if_softc; 1190 1191 if (!sc->lge_link) 1192 return; 1193 1194 idx = sc->lge_cdata.lge_tx_prod; 1195 1196 if (ifp->if_flags & IFF_OACTIVE) 1197 return; 1198 1199 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1200 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1201 break; 1202 1203 IF_DEQUEUE(&ifp->if_snd, m_head); 1204 if (m_head == NULL) 1205 break; 1206 1207 if (lge_encap(sc, m_head, &idx)) { 1208 IF_PREPEND(&ifp->if_snd, m_head); 1209 ifp->if_flags |= IFF_OACTIVE; 1210 break; 1211 } 1212 1213 /* 1214 * If there's a BPF listener, bounce a copy of this frame 1215 * to him. 1216 */ 1217 BPF_MTAP(ifp, m_head); 1218 } 1219 1220 sc->lge_cdata.lge_tx_prod = idx; 1221 1222 /* 1223 * Set a timeout in case the chip goes out to lunch. 1224 */ 1225 ifp->if_timer = 5; 1226 1227 return; 1228 } 1229 1230 static void 1231 lge_init(xsc) 1232 void *xsc; 1233 { 1234 struct lge_softc *sc = xsc; 1235 struct ifnet *ifp = &sc->arpcom.ac_if; 1236 struct mii_data *mii; 1237 int s; 1238 1239 if (ifp->if_flags & IFF_RUNNING) 1240 return; 1241 1242 s = splimp(); 1243 1244 /* 1245 * Cancel pending I/O and free all RX/TX buffers. 1246 */ 1247 lge_stop(sc); 1248 lge_reset(sc); 1249 1250 mii = device_get_softc(sc->lge_miibus); 1251 1252 /* Set MAC address */ 1253 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1254 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1255 1256 /* Init circular RX list. */ 1257 if (lge_list_rx_init(sc) == ENOBUFS) { 1258 printf("lge%d: initialization failed: no " 1259 "memory for rx buffers\n", sc->lge_unit); 1260 lge_stop(sc); 1261 (void)splx(s); 1262 return; 1263 } 1264 1265 /* 1266 * Init tx descriptors. 1267 */ 1268 lge_list_tx_init(sc); 1269 1270 /* Set initial value for MODE1 register. */ 1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1272 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1273 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1274 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1275 1276 /* If we want promiscuous mode, set the allframes bit. */ 1277 if (ifp->if_flags & IFF_PROMISC) { 1278 CSR_WRITE_4(sc, LGE_MODE1, 1279 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1280 } else { 1281 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1282 } 1283 1284 /* 1285 * Set the capture broadcast bit to capture broadcast frames. 1286 */ 1287 if (ifp->if_flags & IFF_BROADCAST) { 1288 CSR_WRITE_4(sc, LGE_MODE1, 1289 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1290 } else { 1291 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1292 } 1293 1294 /* Packet padding workaround? */ 1295 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1296 1297 /* No error frames */ 1298 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1299 1300 /* Receive large frames */ 1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1302 1303 /* Workaround: disable RX/TX flow control */ 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1306 1307 /* Make sure to strip CRC from received frames */ 1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1309 1310 /* Turn off magic packet mode */ 1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1312 1313 /* Turn off all VLAN stuff */ 1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1315 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1316 1317 /* Workarond: FIFO overflow */ 1318 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1319 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1320 1321 /* 1322 * Load the multicast filter. 1323 */ 1324 lge_setmulti(sc); 1325 1326 /* 1327 * Enable hardware checksum validation for all received IPv4 1328 * packets, do not reject packets with bad checksums. 1329 */ 1330 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1331 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1332 LGE_MODE2_RX_ERRCSUM); 1333 1334 /* 1335 * Enable the delivery of PHY interrupts based on 1336 * link/speed/duplex status chalges. 1337 */ 1338 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1339 1340 /* Enable receiver and transmitter. */ 1341 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1342 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1343 1344 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1345 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1346 1347 /* 1348 * Enable interrupts. 1349 */ 1350 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1351 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1352 1353 lge_ifmedia_upd(ifp); 1354 1355 ifp->if_flags |= IFF_RUNNING; 1356 ifp->if_flags &= ~IFF_OACTIVE; 1357 1358 (void)splx(s); 1359 1360 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1361 1362 return; 1363 } 1364 1365 /* 1366 * Set media options. 1367 */ 1368 static int 1369 lge_ifmedia_upd(ifp) 1370 struct ifnet *ifp; 1371 { 1372 struct lge_softc *sc; 1373 struct mii_data *mii; 1374 1375 sc = ifp->if_softc; 1376 1377 mii = device_get_softc(sc->lge_miibus); 1378 sc->lge_link = 0; 1379 if (mii->mii_instance) { 1380 struct mii_softc *miisc; 1381 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1382 miisc = LIST_NEXT(miisc, mii_list)) 1383 mii_phy_reset(miisc); 1384 } 1385 mii_mediachg(mii); 1386 1387 return(0); 1388 } 1389 1390 /* 1391 * Report current media status. 1392 */ 1393 static void 1394 lge_ifmedia_sts(ifp, ifmr) 1395 struct ifnet *ifp; 1396 struct ifmediareq *ifmr; 1397 { 1398 struct lge_softc *sc; 1399 struct mii_data *mii; 1400 1401 sc = ifp->if_softc; 1402 1403 mii = device_get_softc(sc->lge_miibus); 1404 mii_pollstat(mii); 1405 ifmr->ifm_active = mii->mii_media_active; 1406 ifmr->ifm_status = mii->mii_media_status; 1407 1408 return; 1409 } 1410 1411 static int 1412 lge_ioctl(ifp, command, data) 1413 struct ifnet *ifp; 1414 u_long command; 1415 caddr_t data; 1416 { 1417 struct lge_softc *sc = ifp->if_softc; 1418 struct ifreq *ifr = (struct ifreq *) data; 1419 struct mii_data *mii; 1420 int s, error = 0; 1421 1422 s = splimp(); 1423 1424 switch(command) { 1425 case SIOCSIFMTU: 1426 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1427 error = EINVAL; 1428 else 1429 ifp->if_mtu = ifr->ifr_mtu; 1430 break; 1431 case SIOCSIFFLAGS: 1432 if (ifp->if_flags & IFF_UP) { 1433 if (ifp->if_flags & IFF_RUNNING && 1434 ifp->if_flags & IFF_PROMISC && 1435 !(sc->lge_if_flags & IFF_PROMISC)) { 1436 CSR_WRITE_4(sc, LGE_MODE1, 1437 LGE_MODE1_SETRST_CTL1| 1438 LGE_MODE1_RX_PROMISC); 1439 } else if (ifp->if_flags & IFF_RUNNING && 1440 !(ifp->if_flags & IFF_PROMISC) && 1441 sc->lge_if_flags & IFF_PROMISC) { 1442 CSR_WRITE_4(sc, LGE_MODE1, 1443 LGE_MODE1_RX_PROMISC); 1444 } else { 1445 ifp->if_flags &= ~IFF_RUNNING; 1446 lge_init(sc); 1447 } 1448 } else { 1449 if (ifp->if_flags & IFF_RUNNING) 1450 lge_stop(sc); 1451 } 1452 sc->lge_if_flags = ifp->if_flags; 1453 error = 0; 1454 break; 1455 case SIOCADDMULTI: 1456 case SIOCDELMULTI: 1457 lge_setmulti(sc); 1458 error = 0; 1459 break; 1460 case SIOCGIFMEDIA: 1461 case SIOCSIFMEDIA: 1462 mii = device_get_softc(sc->lge_miibus); 1463 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1464 break; 1465 default: 1466 error = ether_ioctl(ifp, command, data); 1467 break; 1468 } 1469 1470 (void)splx(s); 1471 1472 return(error); 1473 } 1474 1475 static void 1476 lge_watchdog(ifp) 1477 struct ifnet *ifp; 1478 { 1479 struct lge_softc *sc; 1480 1481 sc = ifp->if_softc; 1482 1483 ifp->if_oerrors++; 1484 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1485 1486 lge_stop(sc); 1487 lge_reset(sc); 1488 ifp->if_flags &= ~IFF_RUNNING; 1489 lge_init(sc); 1490 1491 if (ifp->if_snd.ifq_head != NULL) 1492 lge_start(ifp); 1493 1494 return; 1495 } 1496 1497 /* 1498 * Stop the adapter and free any mbufs allocated to the 1499 * RX and TX lists. 1500 */ 1501 static void 1502 lge_stop(sc) 1503 struct lge_softc *sc; 1504 { 1505 register int i; 1506 struct ifnet *ifp; 1507 1508 ifp = &sc->arpcom.ac_if; 1509 ifp->if_timer = 0; 1510 untimeout(lge_tick, sc, sc->lge_stat_ch); 1511 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1512 1513 /* Disable receiver and transmitter. */ 1514 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1515 sc->lge_link = 0; 1516 1517 /* 1518 * Free data in the RX lists. 1519 */ 1520 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1521 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1522 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1523 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1524 } 1525 } 1526 bzero((char *)&sc->lge_ldata->lge_rx_list, 1527 sizeof(sc->lge_ldata->lge_rx_list)); 1528 1529 /* 1530 * Free the TX list buffers. 1531 */ 1532 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1533 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1534 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1535 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1536 } 1537 } 1538 1539 bzero((char *)&sc->lge_ldata->lge_tx_list, 1540 sizeof(sc->lge_ldata->lge_tx_list)); 1541 1542 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1543 1544 return; 1545 } 1546 1547 /* 1548 * Stop all chip I/O so that the kernel's probe routines don't 1549 * get confused by errant DMAs when rebooting. 1550 */ 1551 static void 1552 lge_shutdown(dev) 1553 device_t dev; 1554 { 1555 struct lge_softc *sc; 1556 1557 sc = device_get_softc(dev); 1558 1559 lge_reset(sc); 1560 lge_stop(sc); 1561 1562 return; 1563 }
Cache object: ed9699312a47f7e85467e7692f8f0621
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