The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/lnc/if_lncreg.h

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    1 /*-
    2  * Copyright (c) 1994-2000
    3  *      Paul Richards.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer,
   10  *    verbatim and that no modifications are made prior to this
   11  *    point in the file.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. The name Paul Richards may not be used to endorse or promote products
   16  *    derived from this software without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY PAUL RICHARDS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL PAUL RICHARDS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD$
   31  */
   32 
   33 /*
   34  * Am7990, Local Area Network Controller for Ethernet (LANCE)
   35  *
   36  * The LANCE has four Control and Status Registers(CSRs) which are accessed
   37  * through two bus addressable ports, the address port (RAP) and the data
   38  * port (RDP).
   39  *
   40  */
   41 
   42 #define CSR0    0
   43 #define CSR1    1
   44 #define CSR2    2
   45 #define CSR3    3
   46 #define CSR88   88
   47 #define CSR89   89
   48 
   49 #define BCR49   49
   50 #define BCR32   32
   51 #define BCR33   33
   52 #define BCR34   34
   53 
   54 
   55 /* Control and Status Register Masks */
   56 
   57 /* CSR0 */
   58 
   59 #define ERR     0x8000
   60 #define BABL    0x4000
   61 #define CERR    0x2000
   62 #define MISS    0x1000
   63 #define MERR    0x0800
   64 #define RINT    0x0400
   65 #define TINT    0x0200
   66 #define IDON    0x0100
   67 #define INTR    0x0080
   68 #define INEA    0x0040
   69 #define RXON    0x0020
   70 #define TXON    0x0010
   71 #define TDMD    0x0008
   72 #define STOP    0x0004
   73 #define STRT    0x0002
   74 #define INIT    0x0001
   75 
   76 /*
   77  * CSR3
   78  *
   79  * Bits 3-15 are reserved.
   80  *
   81  */
   82 
   83 #define BSWP    0x0004
   84 #define ACON    0x0002
   85 #define BCON    0x0001
   86 
   87 /* ISA Bus Configuration Registers */
   88 #define MSRDA   0x0000  /* ISACSR0: Master Mode Read Activity */
   89 #define MSWRA   0x0001  /* ISACSR1: Master Mode Write Activity */
   90 #define MC      0x0002  /* ISACSR2: Miscellaneous Configuration */
   91 
   92 #define LED1    0x0005  /* ISACSR5: LED1 Status */
   93 #define LED2    0x0006  /* ISACSR6: LED2 Status */
   94 #define LED3    0x0007  /* ISACSR7: LED3 Status */
   95 
   96 #define LED_PSE         0x0080  /* Pulse Stretcher */
   97 #define LED_XMTE        0x0010  /* Transmit Status */
   98 #define LED_RVPOLE      0x0008  /* Receive Polarity */
   99 #define LED_RCVE        0x0004  /* Receive Status */
  100 #define LED_JABE        0x0002  /* Jabber */
  101 #define LED_COLE        0x0001  /* Collision */
  102 
  103 /* Initialisation block */
  104 
  105 struct init_block {
  106         u_short mode;           /* Mode register                        */
  107         u_char  padr[6];        /* Ethernet address                     */
  108         u_char  ladrf[8];       /* Logical address filter (multicast)   */
  109         u_short rdra;           /* Low order pointer to receive ring    */
  110         u_short rlen;           /* High order pointer and no. rings     */
  111         u_short tdra;           /* Low order pointer to transmit ring   */
  112         u_short tlen;           /* High order pointer and no rings      */
  113 };
  114 
  115 /* Initialisation Block Mode Register Masks */
  116 
  117 #define PROM      0x8000   /* Promiscuous Mode */
  118 #define DRCVBC    0x4000   /* Disable Receive Broadcast */
  119 #define DRCVPA    0x2000   /* Disable Receive Physical Address */
  120 #define DLNKTST 0x1000   /* Disable Link Status */
  121 #define DAPC      0x0800   /* Disable Automatic Polarity Correction */
  122 #define MENDECL   0x0400   /* MENDEC Loopback Mode */
  123 #define LRT       0x0200   /* Low Receive Threshold (T-MAU mode only) */
  124 #define TSEL      0x0200   /* Transmit Mode Select  (AUI mode only) */
  125 #define PORTSEL   0x0180   /* Port Select bits */
  126 #define INTL      0x0040   /* Internal Loopback */
  127 #define DRTY      0x0020   /* Disable Retry */
  128 #define FCOLL     0x0010   /* Force Collision */
  129 #define DXMTFCS   0x0008   /* Disable transmit CRC (FCS) */
  130 #define LOOP      0x0004   /* Loopback Enabl */
  131 #define DTX       0x0002   /* Disable the transmitter */
  132 #define DRX       0x0001   /* Disable the receiver */
  133 
  134 /*
  135  * Message Descriptor Structure
  136  *
  137  * Each transmit or receive descriptor ring entry (RDRE's and TDRE's)
  138  * is composed of 4, 16-bit, message descriptors. They contain the following
  139  * information.
  140  *
  141  * 1. The address of the actual message data buffer in user (host) memory.
  142  * 2. The length of that message buffer.
  143  * 3. The status information for that particular buffer. The eight most
  144  *    significant bits of md1 are collectively termed the STATUS of the
  145  *    descriptor.
  146  *
  147  * Descriptor md0 contains LADR 0-15, the low order 16 bits of the 24-bit
  148  * address of the actual data buffer.  Bits 0-7 of descriptor md1 contain
  149  * HADR, the high order 8-bits of the 24-bit data buffer address. Bits 8-15
  150  * of md1 contain the status flags of the buffer. Descriptor md2 contains the
  151  * buffer byte count in bits 0-11 as a two's complement number and must have
  152  * 1's written to bits 12-15. For the receive entry md3 has the Message Byte
  153  * Count in bits 0-11, this is the length of the received message and is valid
  154  * only when ERR is cleared and ENP is set. For the transmit entry it contains
  155  * more status information.
  156  *
  157  */
  158 
  159 struct mds {
  160         u_short md0;
  161         u_short md1;
  162         short   md2;
  163         u_short md3;
  164 };
  165 
  166 /* Receive STATUS flags for md1 */
  167 
  168 #define OWN     0x8000          /* Owner bit, 0=host, 1=Lance   */
  169 #define MDERR   0x4000          /* Error                        */
  170 #define FRAM    0x2000          /* Framing error error          */
  171 #define OFLO    0x1000          /* Silo overflow                */
  172 #define CRC     0x0800          /* CRC error                    */
  173 #define RBUFF   0x0400          /* Buffer error                 */
  174 #define STP     0x0200          /* Start of packet              */
  175 #define ENP     0x0100          /* End of packet                */
  176 #define HADR    0x00FF          /* High order address bits      */
  177 
  178 /* Receive STATUS flags for md2 */
  179 
  180 #define BCNT    0x0FFF          /* Size of data buffer as 2's comp. no. */
  181 
  182 /* Receive STATUS flags for md3 */
  183 
  184 #define MCNT    0x0FFF          /* Total size of data for received packet */
  185 
  186 /* Transmit STATUS flags for md1 */
  187 
  188 #define ADD_FCS 0x2000          /* Controls generation of FCS   */
  189 #define MORE    0x1000          /* Indicates more than one retry was needed */
  190 #define ONE     0x0800          /* Exactly one retry was needed */
  191 #define DEF     0x0400          /* Packet transmit deferred -- channel busy */
  192 
  193 /*
  194  * Transmit status flags for md2
  195  *
  196  * Same as for receive descriptor.
  197  *
  198  * BCNT   0x0FFF         Size of data buffer as 2's complement number.
  199  *
  200  */
  201 
  202 /* Transmit status flags for md3 */
  203 
  204 #define TBUFF   0x8000          /* Buffer error         */
  205 #define UFLO    0x4000          /* Silo underflow       */
  206 #define LCOL    0x1000          /* Late collision       */
  207 #define LCAR    0x0800          /* Loss of carrier      */
  208 #define RTRY    0x0400          /* Tried 16 times       */
  209 #define TDR     0x03FF          /* Time domain reflectometry */

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