The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/malo/if_malo.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2007 Marvell Semiconductor, Inc.
    5  * Copyright (c) 2007 Sam Leffler, Errno Consulting
    6  * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org>
    7  * All rights reserved.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer,
   14  *    without modification.
   15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   16  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   17  *    redistribution must be conditioned upon including a substantially
   18  *    similar Disclaimer requirement for further binary redistribution.
   19  *
   20  * NO WARRANTY
   21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   23  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   24  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   25  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   26  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   29  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGES.
   32  *
   33  * $FreeBSD: stable/12/sys/dev/malo/if_malo.h 326255 2017-11-27 14:52:40Z pfg $
   34  */
   35 
   36 /*
   37  * Definitions for the Marvell 88W8335 Wireless LAN controller.
   38  */
   39 #ifndef _DEV_MALO_H
   40 #define _DEV_MALO_H
   41 
   42 #include <net80211/ieee80211_radiotap.h>
   43 #include <dev/malo/if_malohal.h>
   44 #include <dev/malo/if_maloioctl.h>
   45 
   46 #ifndef MALO_TXBUF
   47 #define MALO_TXBUF              256     /* number of TX descriptors/buffers */
   48 #endif
   49 #ifndef MALO_RXBUF
   50 #define MALO_RXBUF              256     /* number of RX descriptors/buffers */
   51 #endif
   52 
   53 #define MALO_TXDESC             1       /* max tx descriptors/segments */
   54 
   55 #define MALO_RXSIZE             PAGE_SIZE
   56 #define MALO_RSSI_DUMMY_MARKER  127
   57 #define MALO_RSSI_EP_MULTIPLIER (1<<7)  /* pow2 to optimize out * and / */
   58 
   59 #define MALO_REG_INT_CODE                       0x00000C14
   60 /* From host to ARM */
   61 #define MALO_REG_H2A_INTERRUPT_EVENTS           0x00000C18
   62 
   63 /* bit definitions for MALO_REG_H2A_INTERRUPT_CAUSE */
   64 #define MALO_H2ARIC_BIT_PPA_READY               0x00000001
   65 #define MALO_H2ARIC_BIT_DOOR_BELL               0x00000002 /* bit 1 */
   66 #define MALO_H2ARIC_BIT_PS                      0x00000004
   67 #define MALO_H2ARIC_BIT_PSPOLL                  0x00000008 /* bit 3 */
   68 
   69 /* From ARM to host */
   70 #define MALO_REG_A2H_INTERRUPT_CAUSE            0x00000C30
   71 #define MALO_REG_A2H_INTERRUPT_MASK             0x00000C34
   72 #define MALO_REG_A2H_INTERRUPT_CLEAR_SEL        0x00000C38
   73 #define MALO_REG_A2H_INTERRUPT_STATUS_MASK      0x00000C3C
   74 
   75 /* bit definitions for MALO_REG_A2H_INTERRUPT_CAUSE */
   76 #define MALO_A2HRIC_BIT_TX_DONE                 0x00000001      /* bit 0 */
   77 #define MALO_A2HRIC_BIT_RX_RDY                  0x00000002      /* bit 1 */
   78 #define MALO_A2HRIC_BIT_OPC_DONE                0x00000004
   79 #define MALO_A2HRIC_BIT_MAC_EVENT               0x00000008
   80 #define MALO_A2HRIC_BIT_RX_PROBLEM              0x00000010
   81 #define MALO_A2HRIC_BIT_RADIO_OFF               0x00000020      /* bit 5 */
   82 #define MALO_A2HRIC_BIT_RADIO_ON                0x00000040
   83 #define MALO_A2HRIC_BIT_RADAR_DETECT            0x00000080
   84 #define MALO_A2HRIC_BIT_ICV_ERROR               0x00000100
   85 #define MALO_A2HRIC_BIT_MIC_ERROR               0x00000200      /* bit 9 */
   86 #define MALO_A2HRIC_BIT_QUEUE_EMPTY             0x00000400
   87 #define MALO_A2HRIC_BIT_QUEUE_FULL              0x00000800
   88 #define MALO_A2HRIC_BIT_CHAN_SWITCH             0x00001000
   89 #define MALO_A2HRIC_BIT_TX_WATCHDOG             0x00002000
   90 #define MALO_A2HRIC_BIT_BA_WATCHDOG             0x00004000
   91 
   92 #define MALO_ISR_SRC_BITS                       \
   93         (MALO_A2HRIC_BIT_RX_RDY |               \
   94          MALO_A2HRIC_BIT_TX_DONE |              \
   95          MALO_A2HRIC_BIT_OPC_DONE |             \
   96          MALO_A2HRIC_BIT_MAC_EVENT |            \
   97          MALO_A2HRIC_BIT_MIC_ERROR |            \
   98          MALO_A2HRIC_BIT_ICV_ERROR |            \
   99          MALO_A2HRIC_BIT_RADAR_DETECT |         \
  100          MALO_A2HRIC_BIT_CHAN_SWITCH |          \
  101          MALO_A2HRIC_BIT_TX_WATCHDOG |          \
  102          MALO_A2HRIC_BIT_QUEUE_EMPTY)
  103 #define MALO_ISR_RESET                          (1<<15)
  104 
  105 #define MALO_A2HRIC_BIT_MASK                    MALO_ISR_SRC_BITS
  106 
  107 /* map to 0x80000000 on BAR1  */
  108 #define MALO_REG_GEN_PTR                        0x00000C10
  109 #define MALO_REG_INT_CODE                       0x00000C14
  110 #define MALO_REG_SCRATCH                        0x00000C40
  111 
  112 /*
  113  * define OpMode for SoftAP/Station mode
  114  *
  115  * the following mode signature has to be written to PCI scratch register#0
  116  * right after successfully downloading the last block of firmware and
  117  * before waiting for firmware ready signature
  118  */
  119 #define MALO_HOSTCMD_STA_MODE                   0x5A
  120 #define MALO_HOSTCMD_STA_FWRDY_SIGNATURE        0xF0F1F2F4
  121 
  122 /*
  123  * 16 bit host command code
  124  */
  125 #define MALO_HOSTCMD_NONE                       0x0000
  126 #define MALO_HOSTCMD_CODE_DNLD                  0x0001
  127 #define MALO_HOSTCMD_GET_HW_SPEC                0x0003
  128 #define MALO_HOSTCMD_SET_HW_SPEC                0x0004
  129 #define MALO_HOSTCMD_MAC_MULTICAST_ADR          0x0010
  130 #define MALO_HOSTCMD_SET_WEPKEY                 0x0013
  131 #define MALO_HOSTCMD_802_11_RADIO_CONTROL       0x001c
  132 #define MALO_HOSTCMD_802_11_RF_TX_POWER         0x001e
  133 #define MALO_HOSTCMD_802_11_RF_ANTENNA          0x0020
  134 #define MALO_HOSTCMD_SET_PRE_SCAN               0x0107
  135 #define MALO_HOSTCMD_SET_POST_SCAN              0x0108
  136 #define MALO_HOSTCMD_SET_RF_CHANNEL             0x010a
  137 #define MALO_HOSTCMD_SET_AID                    0x010d
  138 #define MALO_HOSTCMD_SET_RATE                   0x0110
  139 #define MALO_HOSTCMD_SET_SLOT                   0x0114
  140 /* define DFS lab commands  */
  141 #define MALO_HOSTCMD_SET_FIXED_RATE             0x0126 
  142 #define MALO_HOSTCMD_SET_REGION_POWER           0x0128
  143 #define MALO_HOSTCMD_GET_CALTABLE               0x1134
  144 
  145 /*
  146  * definition of action or option for each command.
  147  */
  148 /* define general purpose action  */
  149 #define MALO_HOSTCMD_ACT_GEN_GET                0x0000
  150 #define MALO_HOSTCMD_ACT_GEN_SET                0x0001
  151 #define MALO_HOSTCMD_ACT_GEN_SET_LIST           0x0002
  152 
  153 /* define action or option for HostCmd_FW_USE_FIXED_RATE */
  154 #define MALO_HOSTCMD_ACT_USE_FIXED_RATE         0x0001
  155 #define MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE     0x0002
  156 
  157 /* INT code register event definition  */
  158 #define MALO_INT_CODE_CMD_FINISHED              0x00000005
  159 
  160 struct malo_cmd_header {
  161         uint16_t                cmd;
  162         uint16_t                length;
  163         uint16_t                seqnum;
  164         uint16_t                result; 
  165 } __packed;  
  166 
  167 struct malo_cmd_caltable {
  168         struct malo_cmd_header  cmdhdr;
  169         uint8_t                 annex; 
  170         uint8_t                 index;
  171         uint8_t                 len;
  172         uint8_t                 reserverd; 
  173 #define MALO_CAL_TBL_SIZE       160
  174         uint8_t                 caltbl[MALO_CAL_TBL_SIZE];
  175 } __packed;
  176 
  177 struct malo_cmd_get_hwspec {
  178         struct malo_cmd_header  cmdhdr;
  179         u_int8_t                version;        /* version of the HW  */
  180         u_int8_t                hostif;         /* host interface  */
  181         /* Max. number of WCB FW can handle  */
  182         u_int16_t               num_wcb;
  183         /* MaxNbr of MC addresses FW can handle */
  184         u_int16_t               num_mcastaddr;
  185         /* MAC address programmed in HW */
  186         u_int8_t                permaddr[6];
  187         u_int16_t               regioncode;
  188         /* Number of antenna used */
  189         u_int16_t               num_antenna;
  190         /* 4 byte of FW release number */
  191         u_int32_t               fw_releasenum;
  192         u_int32_t               wcbbase0;
  193         u_int32_t               rxpdwr_ptr;
  194         u_int32_t               rxpdrd_ptr;
  195         u_int32_t               ul_fw_awakecookie;
  196         u_int32_t               wcbbase1;
  197         u_int32_t               wcbbase2;
  198         u_int32_t               wcbbase3;
  199 } __packed;
  200 
  201 struct malo_cmd_set_hwspec {
  202         struct malo_cmd_header  cmdhdr;
  203         uint8_t                 version;        /* HW revision */
  204         uint8_t                 hostif;         /* Host interface */
  205         /* Max. number of Multicast address FW can handle */
  206         uint16_t                num_mcastaddr;
  207         uint8_t                 permaddr[6];    /* MAC address */
  208         uint16_t                regioncode;     /* Region Code */
  209         /* 4 byte of FW release number */
  210         uint32_t                fwreleasenum;
  211         /* Firmware awake cookie */
  212         uint32_t                ul_fw_awakecookie;
  213         /* Device capabilities (see above) */
  214         uint32_t                devicecaps;
  215         uint32_t                rxpdwrptr;      /* Rx shared memory queue  */
  216         /* # TX queues in WcbBase array */
  217         uint32_t                num_txqueues;
  218         /* TX WCB Rings */
  219         uint32_t                wcbbase[MALO_MAX_TXWCB_QUEUES];
  220         uint32_t                flags;
  221         uint32_t                txwcbnum_per_queue;
  222         uint32_t                total_rxwcb;
  223 } __packed;
  224 
  225 /* DS 802.11 */
  226 struct malo_cmd_rf_antenna {
  227         struct malo_cmd_header  cmdhdr;
  228         uint16_t                action;
  229         /* Number of antennas or 0xffff (diversity)  */
  230         uint16_t                mode;
  231 } __packed;
  232 
  233 struct malo_cmd_radio_control {
  234         struct malo_cmd_header  cmdhdr;
  235         uint16_t                action;                   
  236         /*
  237          * bit 0 : 1 = on, 0 = off
  238          * bit 1 : 1 = long, 0 = short
  239          * bit 2 : 1 = auto, 0 = fix
  240          */
  241         uint16_t                control;
  242         uint16_t                radio_on;
  243 } __packed;
  244 
  245 struct malo_cmd_fw_set_wmmmode {
  246         struct malo_cmd_header  cmdhdr;
  247         uint16_t                action; /* 0 -> unset, 1 -> set  */
  248 } __packed;
  249 
  250 struct malo_cmd_fw_set_rf_channel {
  251         struct malo_cmd_header  cmdhdr;
  252         uint16_t                action;
  253         uint8_t                 cur_channel;    /* channel # */
  254 } __packed;
  255 
  256 #define MALO_TX_POWER_LEVEL_TOTAL       8
  257 struct malo_cmd_rf_tx_power {
  258         struct malo_cmd_header  cmdhdr;
  259         uint16_t                action;
  260         uint16_t                support_txpower_level;
  261         uint16_t                current_txpower_level;
  262         uint16_t                reserved;
  263         uint16_t                power_levellist[MALO_TX_POWER_LEVEL_TOTAL];
  264 } __packed;
  265 
  266 struct malo_fixrate_flag {
  267         /* lower rate after the retry count.  0 = legacy, 1 = HT  */
  268         uint32_t                type;
  269         /* 0: retry count is not valid, 1: use retry count specified  */
  270         uint32_t                retrycount_valid;
  271 } __packed;
  272 
  273 struct malo_fixed_rate_entry {
  274         struct malo_fixrate_flag typeflags;
  275         /* legacy rate(not index) or an MCS code.  */
  276         uint32_t                fixedrate;
  277         uint32_t                retrycount;
  278 } __packed;
  279 
  280 struct malo_cmd_fw_use_fixed_rate {
  281         struct malo_cmd_header  cmdhdr;
  282         /*
  283          * MALO_HOSTCMD_ACT_GEN_GET     0x0000
  284          * MALO_HOSTCMD_ACT_GEN_SET     0x0001
  285          * MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE  0x0002
  286          */
  287         uint32_t                action;
  288         /* use fixed rate specified but firmware can drop to  */
  289         uint32_t                allowratedrop;
  290         uint32_t                entrycount;
  291         struct malo_fixed_rate_entry fixedrate_table[4];
  292         uint8_t                 multicast_rate;
  293         uint8_t                 multirate_txtype;
  294         uint8_t                 management_rate;
  295 } __packed;
  296 
  297 #define MALO_RATE_INDEX_MAX_ARRAY               14
  298 
  299 struct malo_cmd_fw_set_aid {
  300         struct malo_cmd_header  cmdhdr;
  301         uint16_t                associd;
  302         uint8_t                 macaddr[6];     /* AP's Mac Address(BSSID) */
  303         uint32_t                gprotection;
  304         uint8_t                 aprates[MALO_RATE_INDEX_MAX_ARRAY];
  305 } __packed;
  306 
  307 struct malo_cmd_prescan {
  308         struct malo_cmd_header  cmdhdr;
  309 } __packed;
  310 
  311 struct malo_cmd_postscan {
  312         struct malo_cmd_header  cmdhdr;
  313         uint32_t                isibss;
  314         uint8_t                 bssid[6];
  315 } __packed;
  316 
  317 struct malo_cmd_fw_setslot {
  318         struct malo_cmd_header  cmdhdr;
  319         uint16_t                action;
  320         /* slot = 0 if regular, slot = 1 if short.  */
  321         uint8_t                 slot;
  322 };
  323 
  324 struct malo_cmd_set_rate {
  325         struct malo_cmd_header  cmdhdr;
  326         uint8_t                 dataratetype;
  327         uint8_t                 rateindex;
  328         uint8_t                 aprates[14];
  329 } __packed;
  330 
  331 struct malo_cmd_wepkey {
  332         struct malo_cmd_header  cmdhdr;
  333         uint16_t                action;
  334         uint8_t                 len;
  335         uint8_t                 flags;
  336         uint16_t                index;
  337         uint8_t                 value[IEEE80211_KEYBUF_SIZE];
  338         uint8_t                 txmickey[IEEE80211_WEP_MICLEN];
  339         uint8_t                 rxmickey[IEEE80211_WEP_MICLEN];
  340         uint64_t                rxseqctr;
  341         uint64_t                txseqctr;
  342 } __packed;
  343 
  344 struct malo_cmd_mcast {
  345         struct malo_cmd_header  cmdhdr;
  346         uint16_t                action;
  347         uint16_t                numaddr;
  348 #define MALO_HAL_MCAST_MAX      32
  349         uint8_t                 maclist[6*32];
  350 } __packed;
  351 
  352 /*
  353  * DMA state for tx/rx descriptors.
  354  */
  355 
  356 /*
  357  * Common "base class" for tx/rx descriptor resources
  358  * allocated using the bus dma api.
  359  */
  360 struct malo_descdma {
  361         const char*             dd_name;
  362         void                    *dd_desc;       /* descriptors */
  363         bus_addr_t              dd_desc_paddr;  /* physical addr of dd_desc */
  364         bus_size_t              dd_desc_len;    /* size of dd_desc */
  365         bus_dma_segment_t       dd_dseg;
  366         int                     dd_dnseg;       /* number of segments */
  367         bus_dma_tag_t           dd_dmat;        /* bus DMA tag */
  368         bus_dmamap_t            dd_dmamap;      /* DMA map for descriptors */
  369         void                    *dd_bufptr;     /* associated buffers */
  370 };
  371 
  372 /*
  373  * Hardware tx/rx descriptors.
  374  *
  375  * NB: tx descriptor size must match f/w expected size
  376  * because f/w prefetch's the next descriptor linearly
  377  * and doesn't chase the next pointer.
  378  */
  379 struct malo_txdesc {
  380         uint32_t                status;
  381 #define MALO_TXD_STATUS_IDLE                    0x00000000
  382 #define MALO_TXD_STATUS_USED                    0x00000001 
  383 #define MALO_TXD_STATUS_OK                      0x00000001
  384 #define MALO_TXD_STATUS_OK_RETRY                0x00000002
  385 #define MALO_TXD_STATUS_OK_MORE_RETRY           0x00000004
  386 #define MALO_TXD_STATUS_MULTICAST_TX            0x00000008
  387 #define MALO_TXD_STATUS_BROADCAST_TX            0x00000010
  388 #define MALO_TXD_STATUS_FAILED_LINK_ERROR       0x00000020
  389 #define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT     0x00000040
  390 #define MALO_TXD_STATUS_FAILED_XRETRY   MALO_TXD_STATUS_FAILED_EXCEED_LIMIT
  391 #define MALO_TXD_STATUS_FAILED_AGING            0x00000080
  392 #define MALO_TXD_STATUS_FW_OWNED                0x80000000
  393         uint8_t                 datarate;
  394         uint8_t                 txpriority;
  395         uint16_t                qosctrl;
  396         uint32_t                pktptr;
  397         uint16_t                pktlen;
  398         uint8_t                 destaddr[6];
  399         uint32_t                physnext;
  400         uint32_t                sap_pktinfo;
  401         uint16_t                format;
  402 #define MALO_TXD_FORMAT         0x0001  /* frame format/rate */
  403 #define MALO_TXD_FORMAT_LEGACY  0x0000  /* legacy rate frame */
  404 #define MALO_TXD_RATE           0x01f8  /* tx rate (legacy)/ MCS */
  405 #define MALO_TXD_RATE_S         3
  406 /* NB: 3 is reserved */
  407 #define MALO_TXD_ANTENNA        0x1800  /* antenna select */
  408 #define MALO_TXD_ANTENNA_S      11
  409         uint16_t                pad;    /* align to 4-byte boundary */
  410 } __packed;
  411 
  412 #define MALO_TXDESC_SYNC(txq, ds, how) do {                             \
  413         bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \
  414 } while(0)
  415 
  416 struct malo_rxdesc {
  417         uint8_t         rxcontrol;      /* control element */
  418 #define MALO_RXD_CTRL_DRIVER_OWN                0x00
  419 #define MALO_RXD_CTRL_OS_OWN                    0x04
  420 #define MALO_RXD_CTRL_DMA_OWN                   0x80
  421         uint8_t         snr;            /* signal to noise ratio */
  422         uint8_t         status;         /* status field w/ USED bit */
  423 #define MALO_RXD_STATUS_IDLE                    0x00
  424 #define MALO_RXD_STATUS_OK                      0x01
  425 #define MALO_RXD_STATUS_MULTICAST_RX            0x02
  426 #define MALO_RXD_STATUS_BROADCAST_RX            0x04
  427 #define MALO_RXD_STATUS_FRAGMENT_RX             0x08
  428 #define MALO_RXD_STATUS_GENERAL_DECRYPT_ERR     0xff
  429 #define MALO_RXD_STATUS_DECRYPT_ERR_MASK        0x80
  430 #define MALO_RXD_STATUS_TKIP_MIC_DECRYPT_ERR    0x02
  431 #define MALO_RXD_STATUS_WEP_ICV_DECRYPT_ERR     0x04
  432 #define MALO_RXD_STATUS_TKIP_ICV_DECRYPT_ERR    0x08
  433         uint8_t         channel;        /* channel # pkt received on */
  434         uint16_t        pktlen;         /* total length of received data */
  435         uint8_t         nf;             /* noise floor */
  436         uint8_t         rate;           /* received data rate */
  437         uint32_t        physbuffdata;   /* physical address of payload data */
  438         uint32_t        physnext;       /* physical address of next RX desc */ 
  439         uint16_t        qosctrl;        /* received QosCtrl field variable */
  440         uint16_t        htsig2;         /* like name states */
  441 } __packed;
  442 
  443 #define MALO_RXDESC_SYNC(sc, ds, how) do {                              \
  444         bus_dmamap_sync((sc)->malo_rxdma.dd_dmat,                       \
  445             (sc)->malo_rxdma.dd_dmamap, how);                           \
  446 } while (0)
  447 
  448 struct malo_rxbuf {
  449         STAILQ_ENTRY(malo_rxbuf) bf_list;
  450         void                    *bf_desc;       /* h/w descriptor */
  451         bus_addr_t              bf_daddr;       /* physical addr of desc */
  452         bus_dmamap_t            bf_dmamap;
  453         bus_addr_t              bf_data;        /* physical addr of rx data */
  454         struct mbuf             *bf_m;          /* jumbo mbuf */
  455 };
  456 typedef STAILQ_HEAD(, malo_rxbuf) malo_rxbufhead;
  457 
  458 /*
  459  * Software backed version of tx/rx descriptors.  We keep
  460  * the software state out of the h/w descriptor structure
  461  * so that may be allocated in uncached memory w/o paying
  462  * performance hit.
  463  */
  464 struct malo_txbuf {
  465         STAILQ_ENTRY(malo_txbuf) bf_list;
  466         void                    *bf_desc;       /* h/w descriptor */
  467         bus_addr_t              bf_daddr;       /* physical addr of desc */
  468         bus_dmamap_t            bf_dmamap;      /* DMA map for descriptors */
  469         int                     bf_nseg;
  470         bus_dma_segment_t       bf_segs[MALO_TXDESC];
  471         struct mbuf             *bf_m;
  472         struct ieee80211_node   *bf_node;
  473         struct malo_txq         *bf_txq;        /* backpointer to tx q/ring */
  474 };
  475 typedef STAILQ_HEAD(, malo_txbuf) malo_txbufhead;
  476 
  477 /*
  478  * TX/RX ring definitions.  There are 4 tx rings, one
  479  * per AC, and 1 rx ring.  Note carefully that transmit
  480  * descriptors are treated as a contiguous chunk and the
  481  * firmware pre-fetches descriptors.  This means that we
  482  * must preserve order when moving descriptors between
  483  * the active+free lists; otherwise we may stall transmit.
  484  */
  485 struct malo_txq {
  486         struct malo_descdma     dma;            /* bus dma resources */
  487         struct mtx              lock;           /* tx q lock */
  488         char                    name[12];       /* e.g. "malo0_txq4" */
  489         int                     qnum;           /* f/w q number */
  490         int                     txpri;          /* f/w tx priority */
  491         int                     nfree;          /* # buffers on free list */
  492         malo_txbufhead          free;           /* queue of free buffers */
  493         malo_txbufhead          active;         /* queue of active buffers */
  494 };
  495 
  496 #define MALO_TXQ_LOCK_INIT(_sc, _tq) do { \
  497         snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \
  498                 device_get_nameunit((_sc)->malo_dev), (_tq)->qnum); \
  499         mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \
  500 } while (0)
  501 #define MALO_TXQ_LOCK_DESTROY(_tq)      mtx_destroy(&(_tq)->lock)
  502 #define MALO_TXQ_LOCK(_tq)              mtx_lock(&(_tq)->lock)
  503 #define MALO_TXQ_UNLOCK(_tq)            mtx_unlock(&(_tq)->lock)
  504 #define MALO_TXQ_LOCK_ASSERT(_tq)       mtx_assert(&(_tq)->lock, MA_OWNED)
  505 
  506 /*
  507  * Each packet has fixed front matter: a 2-byte length
  508  * of the payload, followed by a 4-address 802.11 header
  509  * (regardless of the actual header and always w/o any
  510  * QoS header).  The payload then follows.
  511  */
  512 struct malo_txrec {
  513         uint16_t fwlen;
  514         struct ieee80211_frame_addr4 wh;
  515 } __packed;
  516 
  517 struct malo_vap {
  518         struct ieee80211vap malo_vap;
  519         int                     (*malo_newstate)(struct ieee80211vap *,
  520                                     enum ieee80211_state, int);
  521 };
  522 #define MALO_VAP(vap)   ((struct malo_vap *)(vap))
  523 
  524 struct malo_softc {
  525         struct ieee80211com     malo_ic;
  526         struct mbufq            malo_snd;
  527         device_t                malo_dev;
  528         struct mtx              malo_mtx;       /* master lock (recursive) */
  529         struct taskqueue        *malo_tq;       /* private task queue */
  530 
  531         bus_dma_tag_t           malo_dmat;      /* bus DMA tag */
  532         bus_space_handle_t      malo_io0h;      /* BAR 0 */
  533         bus_space_tag_t         malo_io0t;
  534         bus_space_handle_t      malo_io1h;      /* BAR 1 */
  535         bus_space_tag_t         malo_io1t;
  536 
  537         unsigned int            malo_invalid: 1,/* disable hardware accesses */
  538                                 malo_recvsetup: 1,      /* recv setup */
  539                                 malo_fixedrate: 1,      /* use fixed tx rate */
  540                                 malo_running: 1;
  541 
  542         struct malo_hal         *malo_mh;       /* h/w access layer */
  543         struct malo_hal_hwspec  malo_hwspecs;   /* h/w capabilities */
  544         struct malo_hal_txrxdma malo_hwdma;     /* h/w dma setup */
  545         uint32_t                malo_imask;     /* interrupt mask copy */
  546         struct malo_hal_channel malo_curchan;
  547         u_int16_t               malo_rxantenna; /* rx antenna */
  548         u_int16_t               malo_txantenna; /* tx antenna */
  549 
  550         struct malo_descdma     malo_rxdma;     /* rx bus dma resources */
  551         malo_rxbufhead          malo_rxbuf;     /* rx buffers */
  552         struct malo_rxbuf       *malo_rxnext;   /* next rx buffer to process */
  553         struct task             malo_rxtask;    /* rx int processing */
  554 
  555         struct malo_txq         malo_txq[MALO_NUM_TX_QUEUES];
  556         struct task             malo_txtask;    /* tx int processing */
  557         struct callout  malo_watchdog_timer;
  558         int                     malo_timer;
  559 
  560         struct malo_tx_radiotap_header malo_tx_th;
  561         struct malo_rx_radiotap_header malo_rx_th;
  562 
  563         struct malo_stats       malo_stats;     /* interface statistics */
  564         int                     malo_debug;
  565 };
  566 
  567 #define MALO_LOCK_INIT(_sc) \
  568         mtx_init(&(_sc)->malo_mtx, device_get_nameunit((_sc)->malo_dev), \
  569                  NULL, MTX_DEF | MTX_RECURSE)
  570 #define MALO_LOCK_DESTROY(_sc)          mtx_destroy(&(_sc)->malo_mtx)
  571 #define MALO_LOCK(_sc)                  mtx_lock(&(_sc)->malo_mtx)
  572 #define MALO_UNLOCK(_sc)                mtx_unlock(&(_sc)->malo_mtx)
  573 #define MALO_LOCK_ASSERT(_sc)           mtx_assert(&(_sc)->malo_mtx, MA_OWNED)
  574 
  575 #define MALO_RXFREE_INIT(_sc)                                           \
  576         mtx_init(&(_sc)->malo_rxlock, device_get_nameunit((_sc)->malo_dev), \
  577                  NULL, MTX_DEF)
  578 #define MALO_RXFREE_DESTROY(_sc)        mtx_destroy(&(_sc)->malo_rxlock)
  579 #define MALO_RXFREE_LOCK(_sc)           mtx_lock(&(_sc)->malo_rxlock)
  580 #define MALO_RXFREE_UNLOCK(_sc)         mtx_unlock(&(_sc)->malo_rxlock)
  581 #define MALO_RXFREE_ASSERT(_sc)         mtx_assert(&(_sc)->malo_rxlock, \
  582         MA_OWNED)
  583 
  584 int     malo_attach(uint16_t, struct malo_softc *);
  585 int     malo_intr(void *);
  586 int     malo_detach(struct malo_softc *);
  587 void    malo_shutdown(struct malo_softc *);
  588 void    malo_suspend(struct malo_softc *);
  589 void    malo_resume(struct malo_softc *);
  590 
  591 #endif

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