Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/malo/if_malohal.c
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1 /*- 2 * Copyright (c) 2007 Marvell Semiconductor, Inc. 3 * Copyright (c) 2007 Sam Leffler, Errno Consulting 4 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 #ifdef __FreeBSD__ 34 __FBSDID("$FreeBSD$"); 35 #endif 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/kernel.h> 41 #include <sys/firmware.h> 42 #include <sys/socket.h> 43 44 #include <machine/bus.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net80211/ieee80211_var.h> 52 53 #include <dev/malo/if_malo.h> 54 55 #define MALO_WAITOK 1 56 #define MALO_NOWAIT 0 57 58 #define _CMD_SETUP(pCmd, _type, _cmd) do { \ 59 pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 60 memset(pCmd, 0, sizeof(_type)); \ 61 pCmd->cmdhdr.cmd = htole16(_cmd); \ 62 pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 63 } while (0) 64 65 static __inline uint32_t 66 malo_hal_read4(struct malo_hal *mh, bus_size_t off) 67 { 68 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 69 } 70 71 static __inline void 72 malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 73 { 74 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 75 } 76 77 static void 78 malo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 79 { 80 bus_addr_t *paddr = (bus_addr_t*) arg; 81 82 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 83 *paddr = segs->ds_addr; 84 } 85 86 /* 87 * Setup for communication with the device. We allocate 88 * a command buffer and map it for bus dma use. The pci 89 * device id is used to identify whether the device has 90 * SRAM on it (in which case f/w download must include a 91 * memory controller reset). All bus i/o operations happen 92 * in BAR 1; the driver passes in the tag and handle we need. 93 */ 94 struct malo_hal * 95 malo_hal_attach(device_t dev, uint16_t devid, 96 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 97 { 98 int error; 99 struct malo_hal *mh; 100 101 mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 102 if (mh == NULL) 103 return NULL; 104 105 mh->mh_dev = dev; 106 mh->mh_ioh = ioh; 107 mh->mh_iot = iot; 108 109 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 110 "%s_hal", device_get_nameunit(dev)); 111 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 112 113 /* 114 * Allocate the command buffer and map into the address 115 * space of the h/w. We request "coherent" memory which 116 * will be uncached on some architectures. 117 */ 118 error = bus_dma_tag_create(tag, /* parent */ 119 PAGE_SIZE, 0, /* alignment, bounds */ 120 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 121 BUS_SPACE_MAXADDR, /* highaddr */ 122 NULL, NULL, /* filter, filterarg */ 123 MALO_CMDBUF_SIZE, /* maxsize */ 124 1, /* nsegments */ 125 MALO_CMDBUF_SIZE, /* maxsegsize */ 126 BUS_DMA_ALLOCNOW, /* flags */ 127 NULL, /* lockfunc */ 128 NULL, /* lockarg */ 129 &mh->mh_dmat); 130 if (error != 0) { 131 device_printf(dev, "unable to allocate memory for cmd buffer, " 132 "error %u\n", error); 133 goto fail; 134 } 135 136 /* allocate descriptors */ 137 error = bus_dmamap_create(mh->mh_dmat, BUS_DMA_NOWAIT, &mh->mh_dmamap); 138 if (error != 0) { 139 device_printf(dev, "unable to create dmamap for cmd buffers, " 140 "error %u\n", error); 141 goto fail; 142 } 143 144 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 145 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 146 &mh->mh_dmamap); 147 if (error != 0) { 148 device_printf(dev, "unable to allocate memory for cmd buffer, " 149 "error %u\n", error); 150 goto fail; 151 } 152 153 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 154 mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 155 malo_hal_load_cb, &mh->mh_cmdaddr, 156 BUS_DMA_NOWAIT); 157 if (error != 0) { 158 device_printf(dev, "unable to load cmd buffer, error %u\n", 159 error); 160 goto fail; 161 } 162 163 return (mh); 164 165 fail: 166 free(mh, M_DEVBUF); 167 168 if (mh->mh_dmamap != NULL) { 169 bus_dmamap_unload(mh->mh_dmat, mh->mh_dmamap); 170 if (mh->mh_cmdbuf != NULL) 171 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 172 mh->mh_dmamap); 173 bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap); 174 } 175 if (mh->mh_dmat) 176 bus_dma_tag_destroy(mh->mh_dmat); 177 178 return (NULL); 179 } 180 181 /* 182 * Low level firmware cmd block handshake support. 183 */ 184 185 static void 186 malo_hal_send_cmd(struct malo_hal *mh) 187 { 188 uint32_t dummy; 189 190 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 191 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 192 193 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 194 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 195 196 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 197 MALO_H2ARIC_BIT_DOOR_BELL); 198 } 199 200 static int 201 malo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 202 { 203 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 204 int i; 205 206 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 207 if (mh->mh_cmdbuf[0] == le16toh(cmd)) 208 return 1; 209 210 DELAY(1 * 1000); 211 } 212 213 return 0; 214 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS 215 } 216 217 static int 218 malo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 219 { 220 MALO_HAL_LOCK_ASSERT(mh); 221 222 if ((mh->mh_flags & MHF_FWHANG) && 223 (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 224 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 225 cmd); 226 return ENXIO; 227 } 228 229 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 230 device_printf(mh->mh_dev, "%s: device not present!\n", 231 __func__); 232 return EIO; 233 } 234 235 malo_hal_send_cmd(mh); 236 if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 237 device_printf(mh->mh_dev, 238 "timeout waiting for f/w cmd 0x%x\n", cmd); 239 mh->mh_flags |= MHF_FWHANG; 240 return ETIMEDOUT; 241 } 242 243 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 244 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 245 246 return 0; 247 } 248 249 static int 250 malo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 251 { 252 struct malo_cmd_caltable *cmd; 253 int ret; 254 255 MALO_HAL_LOCK_ASSERT(mh); 256 257 _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 258 cmd->annex = annex; 259 cmd->index = index; 260 261 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 262 if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 263 ret = EIO; 264 return ret; 265 } 266 267 static int 268 malo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 269 { 270 const uint8_t *data; 271 int len; 272 273 MALO_HAL_LOCK(mh); 274 /* NB: we hold the lock so it's ok to use cmdbuf */ 275 data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 276 if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 277 len = (data[2] | (data[3] << 8)) - 12; 278 /* XXX validate len */ 279 memcpy(cal->pt_ratetable_20m, &data[12], len); 280 } 281 mh->mh_flags |= MHF_CALDATA; 282 MALO_HAL_UNLOCK(mh); 283 284 return 0; 285 } 286 287 /* 288 * Reset internal state after a firmware download. 289 */ 290 static int 291 malo_hal_resetstate(struct malo_hal *mh) 292 { 293 /* 294 * Fetch cal data for later use. 295 * XXX may want to fetch other stuff too. 296 */ 297 if ((mh->mh_flags & MHF_CALDATA) == 0) 298 malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 299 return 0; 300 } 301 302 static void 303 malo_hal_fw_reset(struct malo_hal *mh) 304 { 305 306 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 307 device_printf(mh->mh_dev, "%s: device not present!\n", 308 __func__); 309 return; 310 } 311 312 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 313 mh->mh_flags &= ~MHF_FWHANG; 314 } 315 316 static void 317 malo_hal_trigger_pcicmd(struct malo_hal *mh) 318 { 319 uint32_t dummy; 320 321 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 322 323 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 324 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 325 326 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 327 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 328 329 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 330 MALO_H2ARIC_BIT_DOOR_BELL); 331 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 332 } 333 334 static int 335 malo_hal_waitfor(struct malo_hal *mh, uint32_t val) 336 { 337 int i; 338 339 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 340 DELAY(MALO_FW_CHECK_USECS); 341 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 342 return 0; 343 } 344 345 return -1; 346 } 347 348 /* 349 * Firmware block xmit when talking to the boot-rom. 350 */ 351 static int 352 malo_hal_send_helper(struct malo_hal *mh, int bsize, 353 const void *data, size_t dsize, int waitfor) 354 { 355 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 356 mh->mh_cmdbuf[1] = htole16(bsize); 357 memcpy(&mh->mh_cmdbuf[4], data , dsize); 358 359 malo_hal_trigger_pcicmd(mh); 360 361 if (waitfor == MALO_NOWAIT) 362 goto pass; 363 364 /* XXX 2000 vs 200 */ 365 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 366 device_printf(mh->mh_dev, 367 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 368 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 369 370 return ETIMEDOUT; 371 } 372 373 pass: 374 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 375 376 return (0); 377 } 378 379 static int 380 malo_hal_fwload_helper(struct malo_hal *mh, char *helper) 381 { 382 const struct firmware *fw; 383 int error; 384 385 fw = firmware_get(helper); 386 if (fw == NULL) { 387 device_printf(mh->mh_dev, "could not read microcode %s!\n", 388 helper); 389 return (EIO); 390 } 391 392 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 393 helper, fw->datasize); 394 395 error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 396 MALO_WAITOK); 397 if (error != 0) 398 goto fail; 399 400 /* tell the card we're done and... */ 401 error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 402 403 fail: 404 firmware_put(fw, FIRMWARE_UNLOAD); 405 406 return (error); 407 } 408 409 /* 410 * Firmware block xmit when talking to the 1st-stage loader. 411 */ 412 static int 413 malo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 414 uint16_t seqnum, int waitfor) 415 { 416 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 417 mh->mh_cmdbuf[1] = htole16(dsize); 418 mh->mh_cmdbuf[2] = htole16(seqnum); 419 mh->mh_cmdbuf[3] = 0; 420 memcpy(&mh->mh_cmdbuf[4], data, dsize); 421 422 malo_hal_trigger_pcicmd(mh); 423 424 if (waitfor == MALO_NOWAIT) 425 goto pass; 426 427 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 428 device_printf(mh->mh_dev, 429 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 430 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 431 432 return ETIMEDOUT; 433 } 434 435 pass: 436 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 437 438 return 0; 439 } 440 441 static int 442 malo_hal_fwload_main(struct malo_hal *mh, char *firmware) 443 { 444 const struct firmware *fw; 445 const uint8_t *fp; 446 int error; 447 size_t count; 448 uint16_t seqnum; 449 uint32_t blocksize; 450 451 error = 0; 452 453 fw = firmware_get(firmware); 454 if (fw == NULL) { 455 device_printf(mh->mh_dev, "could not read firmware %s!\n", 456 firmware); 457 return (EIO); 458 } 459 460 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 461 firmware, fw->datasize); 462 463 seqnum = 1; 464 for (count = 0; count < fw->datasize; count += blocksize) { 465 blocksize = MIN(256, fw->datasize - count); 466 fp = (const uint8_t *)fw->data + count; 467 468 error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 469 MALO_NOWAIT); 470 if (error != 0) 471 goto fail; 472 DELAY(500); 473 } 474 475 /* 476 * send a command with size 0 to tell that the firmware has been 477 * uploaded 478 */ 479 error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 480 DELAY(100); 481 482 fail: 483 firmware_put(fw, FIRMWARE_UNLOAD); 484 485 return (error); 486 } 487 488 int 489 malo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 490 { 491 int error, i; 492 uint32_t fwreadysig, opmode; 493 494 /* 495 * NB: now malo(4) supports only STA mode. It will be better if it 496 * supports AP mode. 497 */ 498 fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 499 opmode = MALO_HOSTCMD_STA_MODE; 500 501 malo_hal_fw_reset(mh); 502 503 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 504 MALO_A2HRIC_BIT_MASK); 505 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 506 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 507 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 508 MALO_A2HRIC_BIT_MASK); 509 510 error = malo_hal_fwload_helper(mh, helper); 511 if (error != 0) { 512 device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 513 goto fail; 514 } 515 516 DELAY(200 * MALO_FW_CHECK_USECS); 517 518 error = malo_hal_fwload_main(mh, firmware); 519 if (error != 0) { 520 device_printf(mh->mh_dev, "failed to load firmware.\n"); 521 goto fail; 522 } 523 524 /* 525 * Wait for firmware to startup; we monitor the INT_CODE register 526 * waiting for a signature to written back indicating it's ready to go. 527 */ 528 mh->mh_cmdbuf[1] = 0; 529 530 if (opmode != MALO_HOSTCMD_STA_MODE) 531 malo_hal_trigger_pcicmd(mh); 532 533 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 534 malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 535 DELAY(MALO_FW_CHECK_USECS); 536 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 537 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 538 return malo_hal_resetstate(mh); 539 } 540 } 541 542 return ETIMEDOUT; 543 fail: 544 malo_hal_fw_reset(mh); 545 546 return (error); 547 } 548 549 /* 550 * Return "hw specs". Note this must be the first cmd MUST be done after 551 * a firmware download or the f/w will lockup. 552 */ 553 int 554 malo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 555 { 556 struct malo_cmd_get_hwspec *cmd; 557 int ret; 558 559 MALO_HAL_LOCK(mh); 560 561 _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 562 memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 563 cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 564 565 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 566 if (ret == 0) { 567 IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 568 hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 569 hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 570 hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 571 hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 572 hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 573 hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 574 hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 575 hw->fw_releasenum = le32toh(cmd->fw_releasenum); 576 hw->maxnum_wcb = le16toh(cmd->num_wcb); 577 hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 578 hw->num_antenna = le16toh(cmd->num_antenna); 579 hw->hwversion = cmd->version; 580 hw->hostinterface = cmd->hostif; 581 } 582 583 MALO_HAL_UNLOCK(mh); 584 585 return ret; 586 } 587 588 void 589 malo_hal_detach(struct malo_hal *mh) 590 { 591 592 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 593 bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap); 594 bus_dma_tag_destroy(mh->mh_dmat); 595 mtx_destroy(&mh->mh_mtx); 596 free(mh, M_DEVBUF); 597 } 598 599 /* 600 * Configure antenna use. Takes effect immediately. 601 * 602 * XXX tx antenna setting ignored 603 * XXX rx antenna setting should always be 3 (for now) 604 */ 605 int 606 malo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 607 { 608 struct malo_cmd_rf_antenna *cmd; 609 int ret; 610 611 if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 612 return EINVAL; 613 614 MALO_HAL_LOCK(mh); 615 616 _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 617 MALO_HOSTCMD_802_11_RF_ANTENNA); 618 cmd->action = htole16(dirset); 619 if (ant == 0) { /* default to all/both antennae */ 620 /* XXX never reach now. */ 621 ant = 3; 622 } 623 cmd->mode = htole16(ant); 624 625 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 626 627 MALO_HAL_UNLOCK(mh); 628 629 return ret; 630 } 631 632 /* 633 * Configure radio. Takes effect immediately. 634 * 635 * XXX preamble installed after set fixed rate cmd 636 */ 637 int 638 malo_hal_setradio(struct malo_hal *mh, int onoff, 639 enum malo_hal_preamble preamble) 640 { 641 struct malo_cmd_radio_control *cmd; 642 int ret; 643 644 MALO_HAL_LOCK(mh); 645 646 _CMD_SETUP(cmd, struct malo_cmd_radio_control, 647 MALO_HOSTCMD_802_11_RADIO_CONTROL); 648 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 649 if (onoff == 0) 650 cmd->control = 0; 651 else 652 cmd->control = htole16(preamble); 653 cmd->radio_on = htole16(onoff); 654 655 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 656 657 MALO_HAL_UNLOCK(mh); 658 659 return ret; 660 } 661 662 /* 663 * Set the interrupt mask. 664 */ 665 void 666 malo_hal_intrset(struct malo_hal *mh, uint32_t mask) 667 { 668 669 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 670 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 671 672 mh->mh_imask = mask; 673 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 674 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 675 } 676 677 int 678 malo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 679 { 680 struct malo_cmd_fw_set_rf_channel *cmd; 681 int ret; 682 683 MALO_HAL_LOCK(mh); 684 685 _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 686 MALO_HOSTCMD_SET_RF_CHANNEL); 687 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 688 cmd->cur_channel = chan->channel; 689 690 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 691 692 MALO_HAL_UNLOCK(mh); 693 694 return ret; 695 } 696 697 int 698 malo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 699 { 700 struct malo_cmd_rf_tx_power *cmd; 701 const struct malo_hal_caldata *cal = &mh->mh_caldata; 702 uint8_t chan = c->channel; 703 uint16_t pow; 704 int i, idx, ret; 705 706 MALO_HAL_LOCK(mh); 707 708 _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 709 MALO_HOSTCMD_802_11_RF_TX_POWER); 710 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 711 for (i = 0; i < 4; i++) { 712 idx = (chan - 1) * 4 + i; 713 pow = cal->pt_ratetable_20m[idx]; 714 cmd->power_levellist[i] = htole16(pow); 715 } 716 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 717 718 MALO_HAL_UNLOCK(mh); 719 720 return ret; 721 } 722 723 int 724 malo_hal_setpromisc(struct malo_hal *mh, int enable) 725 { 726 /* XXX need host cmd */ 727 return 0; 728 } 729 730 int 731 malo_hal_setassocid(struct malo_hal *mh, 732 const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 733 { 734 struct malo_cmd_fw_set_aid *cmd; 735 int ret; 736 737 MALO_HAL_LOCK(mh); 738 739 _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 740 MALO_HOSTCMD_SET_AID); 741 cmd->cmdhdr.seqnum = 1; 742 cmd->associd = htole16(associd); 743 IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 744 745 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 746 MALO_HAL_UNLOCK(mh); 747 return ret; 748 } 749 750 /* 751 * Kick the firmware to tell it there are new tx descriptors 752 * for processing. The driver says what h/w q has work in 753 * case the f/w ever gets smarter. 754 */ 755 void 756 malo_hal_txstart(struct malo_hal *mh, int qnum) 757 { 758 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 759 MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 760 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 761 } 762 763 /* 764 * Return the current ISR setting and clear the cause. 765 */ 766 void 767 malo_hal_getisr(struct malo_hal *mh, uint32_t *status) 768 { 769 uint32_t cause; 770 771 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 772 MALO_REG_A2H_INTERRUPT_CAUSE); 773 if (cause == 0xffffffff) { /* card removed */ 774 cause = 0; 775 } else if (cause != 0) { 776 /* clear cause bits */ 777 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 778 MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 779 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 780 MALO_REG_INT_CODE); 781 cause &= mh->mh_imask; 782 } 783 784 *status = cause; 785 } 786 787 /* 788 * Callback from the driver on a cmd done interrupt. Nothing to do right 789 * now as we spin waiting for cmd completion. 790 */ 791 void 792 malo_hal_cmddone(struct malo_hal *mh) 793 { 794 /* NB : do nothing. */ 795 } 796 797 int 798 malo_hal_prescan(struct malo_hal *mh) 799 { 800 struct malo_cmd_prescan *cmd; 801 int ret; 802 803 MALO_HAL_LOCK(mh); 804 805 _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 806 cmd->cmdhdr.seqnum = 1; 807 808 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 809 810 MALO_HAL_UNLOCK(mh); 811 812 return ret; 813 } 814 815 int 816 malo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 817 { 818 struct malo_cmd_postscan *cmd; 819 int ret; 820 821 MALO_HAL_LOCK(mh); 822 823 _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 824 cmd->cmdhdr.seqnum = 1; 825 cmd->isibss = htole32(ibsson); 826 IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 827 828 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 829 830 MALO_HAL_UNLOCK(mh); 831 832 return ret; 833 } 834 835 int 836 malo_hal_set_slot(struct malo_hal *mh, int is_short) 837 { 838 int ret; 839 struct malo_cmd_fw_setslot *cmd; 840 841 MALO_HAL_LOCK(mh); 842 843 _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 844 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 845 cmd->slot = (is_short == 1 ? 1 : 0); 846 847 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 848 849 MALO_HAL_UNLOCK(mh); 850 851 return ret; 852 } 853 854 int 855 malo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 856 { 857 int i, ret; 858 struct malo_cmd_set_rate *cmd; 859 860 MALO_HAL_LOCK(mh); 861 862 _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 863 cmd->aprates[0] = 2; 864 cmd->aprates[1] = 4; 865 cmd->aprates[2] = 11; 866 cmd->aprates[3] = 22; 867 if (curmode == IEEE80211_MODE_11G) { 868 cmd->aprates[4] = 0; /* XXX reserved? */ 869 cmd->aprates[5] = 12; 870 cmd->aprates[6] = 18; 871 cmd->aprates[7] = 24; 872 cmd->aprates[8] = 36; 873 cmd->aprates[9] = 48; 874 cmd->aprates[10] = 72; 875 cmd->aprates[11] = 96; 876 cmd->aprates[12] = 108; 877 } 878 879 if (rate != 0) { 880 /* fixed rate */ 881 for (i = 0; i < 13; i++) { 882 if (cmd->aprates[i] == rate) { 883 cmd->rateindex = i; 884 cmd->dataratetype = 1; 885 break; 886 } 887 } 888 } 889 890 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 891 892 MALO_HAL_UNLOCK(mh); 893 894 return ret; 895 } 896 897 int 898 malo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 899 { 900 struct malo_cmd_mcast *cmd; 901 int ret; 902 903 if (nmc > MALO_HAL_MCAST_MAX) 904 return EINVAL; 905 906 MALO_HAL_LOCK(mh); 907 908 _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 909 memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 910 cmd->numaddr = htole16(nmc); 911 cmd->action = htole16(0xffff); 912 913 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 914 915 MALO_HAL_UNLOCK(mh); 916 917 return ret; 918 }
Cache object: 4118e8fd62408993bf0a4de279831389
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