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sys/dev/mana/gdma_main.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/smp.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/eventhandler.h> 48 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/in_cksum.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 59 #include "gdma_util.h" 60 #include "mana.h" 61 62 63 static mana_vendor_id_t mana_id_table[] = { 64 { PCI_VENDOR_ID_MICROSOFT, PCI_DEV_ID_MANA_VF}, 65 /* Last entry */ 66 { 0, 0} 67 }; 68 69 static inline uint32_t 70 mana_gd_r32(struct gdma_context *g, uint64_t offset) 71 { 72 uint32_t v = bus_space_read_4(g->gd_bus.bar0_t, 73 g->gd_bus.bar0_h, offset); 74 rmb(); 75 return (v); 76 } 77 78 #if defined(__amd64__) 79 static inline uint64_t 80 mana_gd_r64(struct gdma_context *g, uint64_t offset) 81 { 82 uint64_t v = bus_space_read_8(g->gd_bus.bar0_t, 83 g->gd_bus.bar0_h, offset); 84 rmb(); 85 return (v); 86 } 87 #else 88 static inline uint64_t 89 mana_gd_r64(struct gdma_context *g, uint64_t offset) 90 { 91 uint64_t v; 92 uint32_t *vp = (uint32_t *)&v; 93 94 *vp = mana_gd_r32(g, offset); 95 *(vp + 1) = mana_gd_r32(g, offset + 4); 96 rmb(); 97 return (v); 98 } 99 #endif 100 101 static int 102 mana_gd_query_max_resources(device_t dev) 103 { 104 struct gdma_context *gc = device_get_softc(dev); 105 struct gdma_query_max_resources_resp resp = {}; 106 struct gdma_general_req req = {}; 107 int err; 108 109 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 110 sizeof(req), sizeof(resp)); 111 112 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 113 if (err || resp.hdr.status) { 114 device_printf(gc->dev, 115 "Failed to query resource info: %d, 0x%x\n", 116 err, resp.hdr.status); 117 return err ? err : EPROTO; 118 } 119 120 mana_dbg(NULL, "max_msix %u, max_eq %u, max_cq %u, " 121 "max_sq %u, max_rq %u\n", 122 resp.max_msix, resp.max_eq, resp.max_cq, 123 resp.max_sq, resp.max_rq); 124 125 if (gc->num_msix_usable > resp.max_msix) 126 gc->num_msix_usable = resp.max_msix; 127 128 if (gc->num_msix_usable <= 1) 129 return ENOSPC; 130 131 gc->max_num_queues = mp_ncpus; 132 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 133 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 134 135 if (gc->max_num_queues > resp.max_eq) 136 gc->max_num_queues = resp.max_eq; 137 138 if (gc->max_num_queues > resp.max_cq) 139 gc->max_num_queues = resp.max_cq; 140 141 if (gc->max_num_queues > resp.max_sq) 142 gc->max_num_queues = resp.max_sq; 143 144 if (gc->max_num_queues > resp.max_rq) 145 gc->max_num_queues = resp.max_rq; 146 147 return 0; 148 } 149 150 static int 151 mana_gd_detect_devices(device_t dev) 152 { 153 struct gdma_context *gc = device_get_softc(dev); 154 struct gdma_list_devices_resp resp = {}; 155 struct gdma_general_req req = {}; 156 struct gdma_dev_id gd_dev; 157 uint32_t i, max_num_devs; 158 uint16_t dev_type; 159 int err; 160 161 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 162 sizeof(resp)); 163 164 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 165 if (err || resp.hdr.status) { 166 device_printf(gc->dev, 167 "Failed to detect devices: %d, 0x%x\n", err, 168 resp.hdr.status); 169 return err ? err : EPROTO; 170 } 171 172 max_num_devs = min_t(uint32_t, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 173 174 for (i = 0; i < max_num_devs; i++) { 175 gd_dev = resp.devs[i]; 176 dev_type = gd_dev.type; 177 178 mana_dbg(NULL, "gdma dev %d, type %u\n", 179 i, dev_type); 180 181 /* HWC is already detected in mana_hwc_create_channel(). */ 182 if (dev_type == GDMA_DEVICE_HWC) 183 continue; 184 185 if (dev_type == GDMA_DEVICE_MANA) { 186 gc->mana.gdma_context = gc; 187 gc->mana.dev_id = gd_dev; 188 } 189 } 190 191 return gc->mana.dev_id.type == 0 ? ENODEV : 0; 192 } 193 194 int 195 mana_gd_send_request(struct gdma_context *gc, uint32_t req_len, 196 const void *req, uint32_t resp_len, void *resp) 197 { 198 struct hw_channel_context *hwc = gc->hwc.driver_data; 199 200 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 201 } 202 203 void 204 mana_gd_dma_map_paddr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 205 { 206 bus_addr_t *paddr = arg; 207 208 if (error) 209 return; 210 211 KASSERT(nseg == 1, ("too many segments %d!", nseg)); 212 *paddr = segs->ds_addr; 213 } 214 215 int 216 mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 217 struct gdma_mem_info *gmi) 218 { 219 bus_addr_t dma_handle; 220 void *buf; 221 int err; 222 223 if (!gc || !gmi) 224 return EINVAL; 225 226 if (length < PAGE_SIZE || (length != roundup_pow_of_two(length))) 227 return EINVAL; 228 229 err = bus_dma_tag_create(bus_get_dma_tag(gc->dev), /* parent */ 230 PAGE_SIZE, 0, /* alignment, boundary */ 231 BUS_SPACE_MAXADDR, /* lowaddr */ 232 BUS_SPACE_MAXADDR, /* highaddr */ 233 NULL, NULL, /* filter, filterarg */ 234 length, /* maxsize */ 235 1, /* nsegments */ 236 length, /* maxsegsize */ 237 0, /* flags */ 238 NULL, NULL, /* lockfunc, lockfuncarg*/ 239 &gmi->dma_tag); 240 if (err) { 241 device_printf(gc->dev, 242 "failed to create dma tag, err: %d\n", err); 243 return (err); 244 } 245 246 /* 247 * Must have BUS_DMA_ZERO flag to clear the dma memory. 248 * Otherwise the queue overflow detection mechanism does 249 * not work. 250 */ 251 err = bus_dmamem_alloc(gmi->dma_tag, &buf, 252 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &gmi->dma_map); 253 if (err) { 254 device_printf(gc->dev, 255 "failed to alloc dma mem, err: %d\n", err); 256 bus_dma_tag_destroy(gmi->dma_tag); 257 return (err); 258 } 259 260 err = bus_dmamap_load(gmi->dma_tag, gmi->dma_map, buf, 261 length, mana_gd_dma_map_paddr, &dma_handle, BUS_DMA_NOWAIT); 262 if (err) { 263 device_printf(gc->dev, 264 "failed to load dma mem, err: %d\n", err); 265 bus_dmamem_free(gmi->dma_tag, buf, gmi->dma_map); 266 bus_dma_tag_destroy(gmi->dma_tag); 267 return (err); 268 } 269 270 gmi->dev = gc->dev; 271 gmi->dma_handle = dma_handle; 272 gmi->virt_addr = buf; 273 gmi->length = length; 274 275 return 0; 276 } 277 278 void 279 mana_gd_free_memory(struct gdma_mem_info *gmi) 280 { 281 bus_dmamap_unload(gmi->dma_tag, gmi->dma_map); 282 bus_dmamem_free(gmi->dma_tag, gmi->virt_addr, gmi->dma_map); 283 bus_dma_tag_destroy(gmi->dma_tag); 284 } 285 286 int 287 mana_gd_destroy_doorbell_page(struct gdma_context *gc, int doorbell_page) 288 { 289 struct gdma_destroy_resource_range_req req = {}; 290 struct gdma_resp_hdr resp = {}; 291 int err; 292 293 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_RESOURCE_RANGE, 294 sizeof(req), sizeof(resp)); 295 296 req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 297 req.num_resources = 1; 298 req.allocated_resources = doorbell_page; 299 300 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 301 if (err || resp.status) { 302 device_printf(gc->dev, 303 "Failed to destroy doorbell page: ret %d, 0x%x\n", 304 err, resp.status); 305 return err ? err : EPROTO; 306 } 307 308 return 0; 309 } 310 311 int 312 mana_gd_allocate_doorbell_page(struct gdma_context *gc, int *doorbell_page) 313 { 314 struct gdma_allocate_resource_range_req req = {}; 315 struct gdma_allocate_resource_range_resp resp = {}; 316 int err; 317 318 mana_gd_init_req_hdr(&req.hdr, GDMA_ALLOCATE_RESOURCE_RANGE, 319 sizeof(req), sizeof(resp)); 320 321 req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 322 req.num_resources = 1; 323 req.alignment = 1; 324 325 /* Have GDMA start searching from 0 */ 326 req.allocated_resources = 0; 327 328 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 329 if (err || resp.hdr.status) { 330 device_printf(gc->dev, 331 "Failed to allocate doorbell page: ret %d, 0x%x\n", 332 err, resp.hdr.status); 333 return err ? err : EPROTO; 334 } 335 336 *doorbell_page = resp.allocated_resources; 337 338 return 0; 339 } 340 341 static int 342 mana_gd_create_hw_eq(struct gdma_context *gc, 343 struct gdma_queue *queue) 344 { 345 struct gdma_create_queue_resp resp = {}; 346 struct gdma_create_queue_req req = {}; 347 int err; 348 349 if (queue->type != GDMA_EQ) 350 return EINVAL; 351 352 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 353 sizeof(req), sizeof(resp)); 354 355 req.hdr.dev_id = queue->gdma_dev->dev_id; 356 req.type = queue->type; 357 req.pdid = queue->gdma_dev->pdid; 358 req.doolbell_id = queue->gdma_dev->doorbell; 359 req.gdma_region = queue->mem_info.dma_region_handle; 360 req.queue_size = queue->queue_size; 361 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 362 req.eq_pci_msix_index = queue->eq.msix_index; 363 364 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 365 if (err || resp.hdr.status) { 366 device_printf(gc->dev, 367 "Failed to create queue: %d, 0x%x\n", 368 err, resp.hdr.status); 369 return err ? err : EPROTO; 370 } 371 372 queue->id = resp.queue_index; 373 queue->eq.disable_needed = true; 374 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 375 return 0; 376 } 377 378 static 379 int mana_gd_disable_queue(struct gdma_queue *queue) 380 { 381 struct gdma_context *gc = queue->gdma_dev->gdma_context; 382 struct gdma_disable_queue_req req = {}; 383 struct gdma_general_resp resp = {}; 384 int err; 385 386 if (queue->type != GDMA_EQ) 387 mana_warn(NULL, "Not event queue type 0x%x\n", 388 queue->type); 389 390 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 391 sizeof(req), sizeof(resp)); 392 393 req.hdr.dev_id = queue->gdma_dev->dev_id; 394 req.type = queue->type; 395 req.queue_index = queue->id; 396 req.alloc_res_id_on_creation = 1; 397 398 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 399 if (err || resp.hdr.status) { 400 device_printf(gc->dev, 401 "Failed to disable queue: %d, 0x%x\n", err, 402 resp.hdr.status); 403 return err ? err : EPROTO; 404 } 405 406 return 0; 407 } 408 409 #define DOORBELL_OFFSET_SQ 0x0 410 #define DOORBELL_OFFSET_RQ 0x400 411 #define DOORBELL_OFFSET_CQ 0x800 412 #define DOORBELL_OFFSET_EQ 0xFF8 413 414 static void 415 mana_gd_ring_doorbell(struct gdma_context *gc, uint32_t db_index, 416 enum gdma_queue_type q_type, uint32_t qid, 417 uint32_t tail_ptr, uint8_t num_req) 418 { 419 union gdma_doorbell_entry e = {}; 420 void __iomem *addr; 421 422 addr = (char *)gc->db_page_base + gc->db_page_size * db_index; 423 switch (q_type) { 424 case GDMA_EQ: 425 e.eq.id = qid; 426 e.eq.tail_ptr = tail_ptr; 427 e.eq.arm = num_req; 428 429 addr = (char *)addr + DOORBELL_OFFSET_EQ; 430 break; 431 432 case GDMA_CQ: 433 e.cq.id = qid; 434 e.cq.tail_ptr = tail_ptr; 435 e.cq.arm = num_req; 436 437 addr = (char *)addr + DOORBELL_OFFSET_CQ; 438 break; 439 440 case GDMA_RQ: 441 e.rq.id = qid; 442 e.rq.tail_ptr = tail_ptr; 443 e.rq.wqe_cnt = num_req; 444 445 addr = (char *)addr + DOORBELL_OFFSET_RQ; 446 break; 447 448 case GDMA_SQ: 449 e.sq.id = qid; 450 e.sq.tail_ptr = tail_ptr; 451 452 addr = (char *)addr + DOORBELL_OFFSET_SQ; 453 break; 454 455 default: 456 mana_warn(NULL, "Invalid queue type 0x%x\n", q_type); 457 return; 458 } 459 460 /* Ensure all writes are done before ring doorbell */ 461 wmb(); 462 463 #if defined(__amd64__) 464 writeq(addr, e.as_uint64); 465 #else 466 uint32_t *p = (uint32_t *)&e.as_uint64; 467 writel(addr, *p); 468 writel((char *)addr + 4, *(p + 1)); 469 #endif 470 } 471 472 void 473 mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 474 { 475 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 476 queue->id, queue->head * GDMA_WQE_BU_SIZE, 1); 477 } 478 479 void 480 mana_gd_ring_cq(struct gdma_queue *cq, uint8_t arm_bit) 481 { 482 struct gdma_context *gc = cq->gdma_dev->gdma_context; 483 484 uint32_t num_cqe = cq->queue_size / GDMA_CQE_SIZE; 485 486 uint32_t head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 487 488 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 489 head, arm_bit); 490 } 491 492 static void 493 mana_gd_process_eqe(struct gdma_queue *eq) 494 { 495 uint32_t head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 496 struct gdma_context *gc = eq->gdma_dev->gdma_context; 497 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 498 union gdma_eqe_info eqe_info; 499 enum gdma_eqe_type type; 500 struct gdma_event event; 501 struct gdma_queue *cq; 502 struct gdma_eqe *eqe; 503 uint32_t cq_id; 504 505 eqe = &eq_eqe_ptr[head]; 506 eqe_info.as_uint32 = eqe->eqe_info; 507 type = eqe_info.type; 508 509 switch (type) { 510 case GDMA_EQE_COMPLETION: 511 cq_id = eqe->details[0] & 0xFFFFFF; 512 if (cq_id >= gc->max_num_cqs) { 513 mana_warn(NULL, 514 "failed: cq_id %u > max_num_cqs %u\n", 515 cq_id, gc->max_num_cqs); 516 break; 517 } 518 519 cq = gc->cq_table[cq_id]; 520 if (!cq || cq->type != GDMA_CQ || cq->id != cq_id) { 521 mana_warn(NULL, 522 "failed: invalid cq_id %u\n", cq_id); 523 break; 524 } 525 526 if (cq->cq.callback) 527 cq->cq.callback(cq->cq.context, cq); 528 529 break; 530 531 case GDMA_EQE_TEST_EVENT: 532 gc->test_event_eq_id = eq->id; 533 534 mana_dbg(NULL, 535 "EQE TEST EVENT received for EQ %u\n", eq->id); 536 537 complete(&gc->eq_test_event); 538 break; 539 540 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 541 case GDMA_EQE_HWC_INIT_DATA: 542 case GDMA_EQE_HWC_INIT_DONE: 543 if (!eq->eq.callback) 544 break; 545 546 event.type = type; 547 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 548 eq->eq.callback(eq->eq.context, eq, &event); 549 break; 550 551 default: 552 break; 553 } 554 } 555 556 static void 557 mana_gd_process_eq_events(void *arg) 558 { 559 uint32_t owner_bits, new_bits, old_bits; 560 union gdma_eqe_info eqe_info; 561 struct gdma_eqe *eq_eqe_ptr; 562 struct gdma_queue *eq = arg; 563 struct gdma_context *gc; 564 uint32_t head, num_eqe; 565 struct gdma_eqe *eqe; 566 int i, j; 567 568 gc = eq->gdma_dev->gdma_context; 569 570 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 571 eq_eqe_ptr = eq->queue_mem_ptr; 572 573 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 574 BUS_DMASYNC_POSTREAD); 575 576 /* Process up to 5 EQEs at a time, and update the HW head. */ 577 for (i = 0; i < 5; i++) { 578 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 579 eqe_info.as_uint32 = eqe->eqe_info; 580 owner_bits = eqe_info.owner_bits; 581 582 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 583 584 /* No more entries */ 585 if (owner_bits == old_bits) 586 break; 587 588 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 589 if (owner_bits != new_bits) { 590 /* Something wrong. Log for debugging purpose */ 591 device_printf(gc->dev, 592 "EQ %d: overflow detected, " 593 "i = %d, eq->head = %u " 594 "got owner_bits = %u, new_bits = %u " 595 "eqe addr %p, eqe->eqe_info 0x%x, " 596 "eqe type = %x, reserved1 = %x, client_id = %x, " 597 "reserved2 = %x, owner_bits = %x\n", 598 eq->id, i, eq->head, 599 owner_bits, new_bits, 600 eqe, eqe->eqe_info, 601 eqe_info.type, eqe_info.reserved1, 602 eqe_info.client_id, eqe_info.reserved2, 603 eqe_info.owner_bits); 604 605 uint32_t *eqe_dump = (uint32_t *) eq_eqe_ptr; 606 for (j = 0; j < 20; j++) { 607 device_printf(gc->dev, "%p: %x\t%x\t%x\t%x\n", 608 &eqe_dump[j * 4], eqe_dump[j * 4], eqe_dump[j * 4 + 1], 609 eqe_dump[j * 4 + 2], eqe_dump[j * 4 + 3]); 610 } 611 break; 612 } 613 614 rmb(); 615 616 mana_gd_process_eqe(eq); 617 618 eq->head++; 619 } 620 621 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 622 BUS_DMASYNC_PREREAD); 623 624 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 625 626 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 627 head, SET_ARM_BIT); 628 } 629 630 static int 631 mana_gd_register_irq(struct gdma_queue *queue, 632 const struct gdma_queue_spec *spec) 633 { 634 struct gdma_dev *gd = queue->gdma_dev; 635 struct gdma_irq_context *gic; 636 struct gdma_context *gc; 637 struct gdma_resource *r; 638 unsigned int msi_index; 639 int err; 640 641 gc = gd->gdma_context; 642 r = &gc->msix_resource; 643 644 mtx_lock_spin(&r->lock_spin); 645 646 msi_index = find_first_zero_bit(r->map, r->size); 647 if (msi_index >= r->size) { 648 err = ENOSPC; 649 } else { 650 bitmap_set(r->map, msi_index, 1); 651 queue->eq.msix_index = msi_index; 652 err = 0; 653 } 654 655 mtx_unlock_spin(&r->lock_spin); 656 657 if (err) 658 return err; 659 660 if (unlikely(msi_index >= gc->num_msix_usable)) { 661 device_printf(gc->dev, 662 "chose an invalid msix index %d, usable %d\n", 663 msi_index, gc->num_msix_usable); 664 return ENOSPC; 665 } 666 667 gic = &gc->irq_contexts[msi_index]; 668 669 if (unlikely(gic->handler || gic->arg)) { 670 device_printf(gc->dev, 671 "interrupt handler or arg already assigned, " 672 "msix index: %d\n", msi_index); 673 } 674 675 gic->arg = queue; 676 677 gic->handler = mana_gd_process_eq_events; 678 679 mana_dbg(NULL, "registered msix index %d vector %d irq %ju\n", 680 msi_index, gic->msix_e.vector, rman_get_start(gic->res)); 681 682 return 0; 683 } 684 685 static void 686 mana_gd_deregiser_irq(struct gdma_queue *queue) 687 { 688 struct gdma_dev *gd = queue->gdma_dev; 689 struct gdma_irq_context *gic; 690 struct gdma_context *gc; 691 struct gdma_resource *r; 692 unsigned int msix_index; 693 694 gc = gd->gdma_context; 695 r = &gc->msix_resource; 696 697 /* At most num_online_cpus() + 1 interrupts are used. */ 698 msix_index = queue->eq.msix_index; 699 if (unlikely(msix_index >= gc->num_msix_usable)) 700 return; 701 702 gic = &gc->irq_contexts[msix_index]; 703 gic->handler = NULL; 704 gic->arg = NULL; 705 706 mtx_lock_spin(&r->lock_spin); 707 bitmap_clear(r->map, msix_index, 1); 708 mtx_unlock_spin(&r->lock_spin); 709 710 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 711 712 mana_dbg(NULL, "deregistered msix index %d vector %d irq %ju\n", 713 msix_index, gic->msix_e.vector, rman_get_start(gic->res)); 714 } 715 716 int 717 mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 718 { 719 struct gdma_generate_test_event_req req = {}; 720 struct gdma_general_resp resp = {}; 721 device_t dev = gc->dev; 722 int err; 723 724 sx_xlock(&gc->eq_test_event_sx); 725 726 init_completion(&gc->eq_test_event); 727 gc->test_event_eq_id = INVALID_QUEUE_ID; 728 729 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 730 sizeof(req), sizeof(resp)); 731 732 req.hdr.dev_id = eq->gdma_dev->dev_id; 733 req.queue_index = eq->id; 734 735 err = mana_gd_send_request(gc, sizeof(req), &req, 736 sizeof(resp), &resp); 737 if (err) { 738 device_printf(dev, "test_eq failed: %d\n", err); 739 goto out; 740 } 741 742 err = EPROTO; 743 744 if (resp.hdr.status) { 745 device_printf(dev, "test_eq failed: 0x%x\n", 746 resp.hdr.status); 747 goto out; 748 } 749 750 if (wait_for_completion_timeout(&gc->eq_test_event, 30 * hz)) { 751 device_printf(dev, "test_eq timed out on queue %d\n", 752 eq->id); 753 goto out; 754 } 755 756 if (eq->id != gc->test_event_eq_id) { 757 device_printf(dev, 758 "test_eq got an event on wrong queue %d (%d)\n", 759 gc->test_event_eq_id, eq->id); 760 goto out; 761 } 762 763 err = 0; 764 out: 765 sx_xunlock(&gc->eq_test_event_sx); 766 return err; 767 } 768 769 static void 770 mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 771 struct gdma_queue *queue) 772 { 773 int err; 774 775 if (flush_evenets) { 776 err = mana_gd_test_eq(gc, queue); 777 if (err) 778 device_printf(gc->dev, 779 "Failed to flush EQ: %d\n", err); 780 } 781 782 mana_gd_deregiser_irq(queue); 783 784 if (queue->eq.disable_needed) 785 mana_gd_disable_queue(queue); 786 } 787 788 static int mana_gd_create_eq(struct gdma_dev *gd, 789 const struct gdma_queue_spec *spec, 790 bool create_hwq, struct gdma_queue *queue) 791 { 792 struct gdma_context *gc = gd->gdma_context; 793 device_t dev = gc->dev; 794 uint32_t log2_num_entries; 795 int err; 796 797 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 798 799 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 800 801 if (spec->eq.log2_throttle_limit > log2_num_entries) { 802 device_printf(dev, 803 "EQ throttling limit (%lu) > maximum EQE (%u)\n", 804 spec->eq.log2_throttle_limit, log2_num_entries); 805 return EINVAL; 806 } 807 808 err = mana_gd_register_irq(queue, spec); 809 if (err) { 810 device_printf(dev, "Failed to register irq: %d\n", err); 811 return err; 812 } 813 814 queue->eq.callback = spec->eq.callback; 815 queue->eq.context = spec->eq.context; 816 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 817 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 818 819 if (create_hwq) { 820 err = mana_gd_create_hw_eq(gc, queue); 821 if (err) 822 goto out; 823 824 err = mana_gd_test_eq(gc, queue); 825 if (err) 826 goto out; 827 } 828 829 return 0; 830 out: 831 device_printf(dev, "Failed to create EQ: %d\n", err); 832 mana_gd_destroy_eq(gc, false, queue); 833 return err; 834 } 835 836 static void 837 mana_gd_create_cq(const struct gdma_queue_spec *spec, 838 struct gdma_queue *queue) 839 { 840 uint32_t log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 841 842 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 843 queue->cq.parent = spec->cq.parent_eq; 844 queue->cq.context = spec->cq.context; 845 queue->cq.callback = spec->cq.callback; 846 } 847 848 static void 849 mana_gd_destroy_cq(struct gdma_context *gc, 850 struct gdma_queue *queue) 851 { 852 uint32_t id = queue->id; 853 854 if (id >= gc->max_num_cqs) 855 return; 856 857 if (!gc->cq_table[id]) 858 return; 859 860 gc->cq_table[id] = NULL; 861 } 862 863 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 864 const struct gdma_queue_spec *spec, 865 struct gdma_queue **queue_ptr) 866 { 867 struct gdma_context *gc = gd->gdma_context; 868 struct gdma_mem_info *gmi; 869 struct gdma_queue *queue; 870 int err; 871 872 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 873 if (!queue) 874 return ENOMEM; 875 876 gmi = &queue->mem_info; 877 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 878 if (err) 879 goto free_q; 880 881 queue->head = 0; 882 queue->tail = 0; 883 queue->queue_mem_ptr = gmi->virt_addr; 884 queue->queue_size = spec->queue_size; 885 queue->monitor_avl_buf = spec->monitor_avl_buf; 886 queue->type = spec->type; 887 queue->gdma_dev = gd; 888 889 if (spec->type == GDMA_EQ) 890 err = mana_gd_create_eq(gd, spec, false, queue); 891 else if (spec->type == GDMA_CQ) 892 mana_gd_create_cq(spec, queue); 893 894 if (err) 895 goto out; 896 897 *queue_ptr = queue; 898 return 0; 899 out: 900 mana_gd_free_memory(gmi); 901 free_q: 902 free(queue, M_DEVBUF); 903 return err; 904 } 905 906 int 907 mana_gd_destroy_dma_region(struct gdma_context *gc, 908 gdma_obj_handle_t dma_region_handle) 909 { 910 struct gdma_destroy_dma_region_req req = {}; 911 struct gdma_general_resp resp = {}; 912 int err; 913 914 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 915 return 0; 916 917 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 918 sizeof(resp)); 919 req.dma_region_handle = dma_region_handle; 920 921 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), 922 &resp); 923 if (err || resp.hdr.status) { 924 device_printf(gc->dev, 925 "Failed to destroy DMA region: %d, 0x%x\n", 926 err, resp.hdr.status); 927 return EPROTO; 928 } 929 930 return 0; 931 } 932 933 static int 934 mana_gd_create_dma_region(struct gdma_dev *gd, 935 struct gdma_mem_info *gmi) 936 { 937 unsigned int num_page = gmi->length / PAGE_SIZE; 938 struct gdma_create_dma_region_req *req = NULL; 939 struct gdma_create_dma_region_resp resp = {}; 940 struct gdma_context *gc = gd->gdma_context; 941 struct hw_channel_context *hwc; 942 uint32_t length = gmi->length; 943 uint32_t req_msg_size; 944 int err; 945 int i; 946 947 if (length < PAGE_SIZE || !is_power_of_2(length)) { 948 mana_err(NULL, "gmi size incorrect: %u\n", length); 949 return EINVAL; 950 } 951 952 if (offset_in_page((uintptr_t)gmi->virt_addr) != 0) { 953 mana_err(NULL, "gmi not page aligned: %p\n", 954 gmi->virt_addr); 955 return EINVAL; 956 } 957 958 hwc = gc->hwc.driver_data; 959 req_msg_size = sizeof(*req) + num_page * sizeof(uint64_t); 960 if (req_msg_size > hwc->max_req_msg_size) { 961 mana_err(NULL, "req msg size too large: %u, %u\n", 962 req_msg_size, hwc->max_req_msg_size); 963 return EINVAL; 964 } 965 966 req = malloc(req_msg_size, M_DEVBUF, M_WAITOK | M_ZERO); 967 if (!req) 968 return ENOMEM; 969 970 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 971 req_msg_size, sizeof(resp)); 972 req->length = length; 973 req->offset_in_page = 0; 974 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 975 req->page_count = num_page; 976 req->page_addr_list_len = num_page; 977 978 for (i = 0; i < num_page; i++) 979 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 980 981 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 982 if (err) 983 goto out; 984 985 if (resp.hdr.status || 986 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 987 device_printf(gc->dev, "Failed to create DMA region: 0x%x\n", 988 resp.hdr.status); 989 err = EPROTO; 990 goto out; 991 } 992 993 gmi->dma_region_handle = resp.dma_region_handle; 994 out: 995 free(req, M_DEVBUF); 996 return err; 997 } 998 999 int 1000 mana_gd_create_mana_eq(struct gdma_dev *gd, 1001 const struct gdma_queue_spec *spec, 1002 struct gdma_queue **queue_ptr) 1003 { 1004 struct gdma_context *gc = gd->gdma_context; 1005 struct gdma_mem_info *gmi; 1006 struct gdma_queue *queue; 1007 int err; 1008 1009 if (spec->type != GDMA_EQ) 1010 return EINVAL; 1011 1012 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1013 if (!queue) 1014 return ENOMEM; 1015 1016 gmi = &queue->mem_info; 1017 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1018 if (err) 1019 goto free_q; 1020 1021 err = mana_gd_create_dma_region(gd, gmi); 1022 if (err) 1023 goto out; 1024 1025 queue->head = 0; 1026 queue->tail = 0; 1027 queue->queue_mem_ptr = gmi->virt_addr; 1028 queue->queue_size = spec->queue_size; 1029 queue->monitor_avl_buf = spec->monitor_avl_buf; 1030 queue->type = spec->type; 1031 queue->gdma_dev = gd; 1032 1033 err = mana_gd_create_eq(gd, spec, true, queue); 1034 if (err) 1035 goto out; 1036 1037 *queue_ptr = queue; 1038 return 0; 1039 1040 out: 1041 mana_gd_free_memory(gmi); 1042 free_q: 1043 free(queue, M_DEVBUF); 1044 return err; 1045 } 1046 1047 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 1048 const struct gdma_queue_spec *spec, 1049 struct gdma_queue **queue_ptr) 1050 { 1051 struct gdma_context *gc = gd->gdma_context; 1052 struct gdma_mem_info *gmi; 1053 struct gdma_queue *queue; 1054 int err; 1055 1056 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 1057 spec->type != GDMA_RQ) 1058 return EINVAL; 1059 1060 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1061 if (!queue) 1062 return ENOMEM; 1063 1064 gmi = &queue->mem_info; 1065 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1066 if (err) 1067 goto free_q; 1068 1069 err = mana_gd_create_dma_region(gd, gmi); 1070 if (err) 1071 goto out; 1072 1073 queue->head = 0; 1074 queue->tail = 0; 1075 queue->queue_mem_ptr = gmi->virt_addr; 1076 queue->queue_size = spec->queue_size; 1077 queue->monitor_avl_buf = spec->monitor_avl_buf; 1078 queue->type = spec->type; 1079 queue->gdma_dev = gd; 1080 1081 if (spec->type == GDMA_CQ) 1082 mana_gd_create_cq(spec, queue); 1083 1084 *queue_ptr = queue; 1085 return 0; 1086 1087 out: 1088 mana_gd_free_memory(gmi); 1089 free_q: 1090 free(queue, M_DEVBUF); 1091 return err; 1092 } 1093 1094 void 1095 mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 1096 { 1097 struct gdma_mem_info *gmi = &queue->mem_info; 1098 1099 switch (queue->type) { 1100 case GDMA_EQ: 1101 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 1102 break; 1103 1104 case GDMA_CQ: 1105 mana_gd_destroy_cq(gc, queue); 1106 break; 1107 1108 case GDMA_RQ: 1109 break; 1110 1111 case GDMA_SQ: 1112 break; 1113 1114 default: 1115 device_printf(gc->dev, 1116 "Can't destroy unknown queue: type = %d\n", 1117 queue->type); 1118 return; 1119 } 1120 1121 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 1122 mana_gd_free_memory(gmi); 1123 free(queue, M_DEVBUF); 1124 } 1125 1126 #define OS_MAJOR_DIV 100000 1127 #define OS_BUILD_MOD 1000 1128 1129 int 1130 mana_gd_verify_vf_version(device_t dev) 1131 { 1132 struct gdma_context *gc = device_get_softc(dev); 1133 struct gdma_verify_ver_resp resp = {}; 1134 struct gdma_verify_ver_req req = {}; 1135 int err; 1136 1137 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 1138 sizeof(req), sizeof(resp)); 1139 1140 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 1141 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 1142 1143 req.drv_ver = 0; /* Unused */ 1144 req.os_type = 0x30; /* Other */ 1145 req.os_ver_major = osreldate / OS_MAJOR_DIV; 1146 req.os_ver_minor = (osreldate % OS_MAJOR_DIV) / OS_BUILD_MOD; 1147 req.os_ver_build = osreldate % OS_BUILD_MOD; 1148 strncpy(req.os_ver_str1, ostype, sizeof(req.os_ver_str1) - 1); 1149 strncpy(req.os_ver_str2, osrelease, sizeof(req.os_ver_str2) - 1); 1150 1151 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1152 if (err || resp.hdr.status) { 1153 device_printf(gc->dev, 1154 "VfVerifyVersionOutput: %d, status=0x%x\n", 1155 err, resp.hdr.status); 1156 return err ? err : EPROTO; 1157 } 1158 1159 return 0; 1160 } 1161 1162 int 1163 mana_gd_register_device(struct gdma_dev *gd) 1164 { 1165 struct gdma_context *gc = gd->gdma_context; 1166 struct gdma_register_device_resp resp = {}; 1167 struct gdma_general_req req = {}; 1168 int err; 1169 1170 gd->pdid = INVALID_PDID; 1171 gd->doorbell = INVALID_DOORBELL; 1172 gd->gpa_mkey = INVALID_MEM_KEY; 1173 1174 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 1175 sizeof(resp)); 1176 1177 req.hdr.dev_id = gd->dev_id; 1178 1179 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1180 if (err || resp.hdr.status) { 1181 device_printf(gc->dev, 1182 "gdma_register_device_resp failed: %d, 0x%x\n", 1183 err, resp.hdr.status); 1184 return err ? err : -EPROTO; 1185 } 1186 1187 gd->pdid = resp.pdid; 1188 gd->gpa_mkey = resp.gpa_mkey; 1189 gd->doorbell = resp.db_id; 1190 1191 mana_dbg(NULL, "mana device pdid %u, gpa_mkey %u, doorbell %u \n", 1192 gd->pdid, gd->gpa_mkey, gd->doorbell); 1193 1194 return 0; 1195 } 1196 1197 int 1198 mana_gd_deregister_device(struct gdma_dev *gd) 1199 { 1200 struct gdma_context *gc = gd->gdma_context; 1201 struct gdma_general_resp resp = {}; 1202 struct gdma_general_req req = {}; 1203 int err; 1204 1205 if (gd->pdid == INVALID_PDID) 1206 return EINVAL; 1207 1208 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1209 sizeof(resp)); 1210 1211 req.hdr.dev_id = gd->dev_id; 1212 1213 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1214 if (err || resp.hdr.status) { 1215 device_printf(gc->dev, 1216 "Failed to deregister device: %d, 0x%x\n", 1217 err, resp.hdr.status); 1218 if (!err) 1219 err = EPROTO; 1220 } 1221 1222 gd->pdid = INVALID_PDID; 1223 gd->doorbell = INVALID_DOORBELL; 1224 gd->gpa_mkey = INVALID_MEM_KEY; 1225 1226 return err; 1227 } 1228 1229 uint32_t 1230 mana_gd_wq_avail_space(struct gdma_queue *wq) 1231 { 1232 uint32_t used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1233 uint32_t wq_size = wq->queue_size; 1234 1235 if (used_space > wq_size) { 1236 mana_warn(NULL, "failed: used space %u > queue size %u\n", 1237 used_space, wq_size); 1238 } 1239 1240 return wq_size - used_space; 1241 } 1242 1243 uint8_t * 1244 mana_gd_get_wqe_ptr(const struct gdma_queue *wq, uint32_t wqe_offset) 1245 { 1246 uint32_t offset = 1247 (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1248 1249 if ((offset + GDMA_WQE_BU_SIZE) > wq->queue_size) { 1250 mana_warn(NULL, "failed: write end out of queue bound %u, " 1251 "queue size %u\n", 1252 offset + GDMA_WQE_BU_SIZE, wq->queue_size); 1253 } 1254 1255 return (uint8_t *)wq->queue_mem_ptr + offset; 1256 } 1257 1258 static uint32_t 1259 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1260 enum gdma_queue_type q_type, 1261 uint32_t client_oob_size, uint32_t sgl_data_size, 1262 uint8_t *wqe_ptr) 1263 { 1264 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1265 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1266 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1267 uint8_t *ptr; 1268 1269 memset(header, 0, sizeof(struct gdma_wqe)); 1270 header->num_sge = wqe_req->num_sge; 1271 header->inline_oob_size_div4 = client_oob_size / sizeof(uint32_t); 1272 1273 if (oob_in_sgl) { 1274 if (!pad_data || wqe_req->num_sge < 2) { 1275 mana_warn(NULL, "no pad_data or num_sge < 2\n"); 1276 } 1277 1278 header->client_oob_in_sgl = 1; 1279 1280 if (pad_data) 1281 header->last_vbytes = wqe_req->sgl[0].size; 1282 } 1283 1284 if (q_type == GDMA_SQ) 1285 header->client_data_unit = wqe_req->client_data_unit; 1286 1287 /* 1288 * The size of gdma_wqe + client_oob_size must be less than or equal 1289 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1290 * the queue memory buffer boundary. 1291 */ 1292 ptr = wqe_ptr + sizeof(header); 1293 1294 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1295 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1296 1297 if (client_oob_size > wqe_req->inline_oob_size) 1298 memset(ptr + wqe_req->inline_oob_size, 0, 1299 client_oob_size - wqe_req->inline_oob_size); 1300 } 1301 1302 return sizeof(header) + client_oob_size; 1303 } 1304 1305 static void 1306 mana_gd_write_sgl(struct gdma_queue *wq, uint8_t *wqe_ptr, 1307 const struct gdma_wqe_request *wqe_req) 1308 { 1309 uint32_t sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1310 const uint8_t *address = (uint8_t *)wqe_req->sgl; 1311 uint8_t *base_ptr, *end_ptr; 1312 uint32_t size_to_end; 1313 1314 base_ptr = wq->queue_mem_ptr; 1315 end_ptr = base_ptr + wq->queue_size; 1316 size_to_end = (uint32_t)(end_ptr - wqe_ptr); 1317 1318 if (size_to_end < sgl_size) { 1319 memcpy(wqe_ptr, address, size_to_end); 1320 1321 wqe_ptr = base_ptr; 1322 address += size_to_end; 1323 sgl_size -= size_to_end; 1324 } 1325 1326 memcpy(wqe_ptr, address, sgl_size); 1327 } 1328 1329 int 1330 mana_gd_post_work_request(struct gdma_queue *wq, 1331 const struct gdma_wqe_request *wqe_req, 1332 struct gdma_posted_wqe_info *wqe_info) 1333 { 1334 uint32_t client_oob_size = wqe_req->inline_oob_size; 1335 struct gdma_context *gc; 1336 uint32_t sgl_data_size; 1337 uint32_t max_wqe_size; 1338 uint32_t wqe_size; 1339 uint8_t *wqe_ptr; 1340 1341 if (wqe_req->num_sge == 0) 1342 return EINVAL; 1343 1344 if (wq->type == GDMA_RQ) { 1345 if (client_oob_size != 0) 1346 return EINVAL; 1347 1348 client_oob_size = INLINE_OOB_SMALL_SIZE; 1349 1350 max_wqe_size = GDMA_MAX_RQE_SIZE; 1351 } else { 1352 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1353 client_oob_size != INLINE_OOB_LARGE_SIZE) 1354 return EINVAL; 1355 1356 max_wqe_size = GDMA_MAX_SQE_SIZE; 1357 } 1358 1359 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1360 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1361 sgl_data_size, GDMA_WQE_BU_SIZE); 1362 if (wqe_size > max_wqe_size) 1363 return EINVAL; 1364 1365 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1366 gc = wq->gdma_dev->gdma_context; 1367 device_printf(gc->dev, "unsuccessful flow control!\n"); 1368 return ENOSPC; 1369 } 1370 1371 if (wqe_info) 1372 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1373 1374 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1375 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1376 sgl_data_size, wqe_ptr); 1377 if (wqe_ptr >= (uint8_t *)wq->queue_mem_ptr + wq->queue_size) 1378 wqe_ptr -= wq->queue_size; 1379 1380 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1381 1382 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1383 1384 bus_dmamap_sync(wq->mem_info.dma_tag, wq->mem_info.dma_map, 1385 BUS_DMASYNC_PREWRITE); 1386 1387 return 0; 1388 } 1389 1390 int 1391 mana_gd_post_and_ring(struct gdma_queue *queue, 1392 const struct gdma_wqe_request *wqe_req, 1393 struct gdma_posted_wqe_info *wqe_info) 1394 { 1395 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1396 int err; 1397 1398 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1399 if (err) 1400 return err; 1401 1402 mana_gd_wq_ring_doorbell(gc, queue); 1403 1404 return 0; 1405 } 1406 1407 static int 1408 mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1409 { 1410 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1411 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1412 uint32_t owner_bits, new_bits, old_bits; 1413 struct gdma_cqe *cqe; 1414 1415 cqe = &cq_cqe[cq->head % num_cqe]; 1416 owner_bits = cqe->cqe_info.owner_bits; 1417 1418 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1419 /* Return 0 if no more entries. */ 1420 if (owner_bits == old_bits) 1421 return 0; 1422 1423 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1424 /* Return -1 if overflow detected. */ 1425 if (owner_bits != new_bits) { 1426 mana_warn(NULL, 1427 "overflow detected! owner_bits %u != new_bits %u\n", 1428 owner_bits, new_bits); 1429 return -1; 1430 } 1431 1432 rmb(); 1433 1434 comp->wq_num = cqe->cqe_info.wq_num; 1435 comp->is_sq = cqe->cqe_info.is_sq; 1436 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1437 1438 return 1; 1439 } 1440 1441 int 1442 mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1443 { 1444 int cqe_idx; 1445 int ret; 1446 1447 bus_dmamap_sync(cq->mem_info.dma_tag, cq->mem_info.dma_map, 1448 BUS_DMASYNC_POSTREAD); 1449 1450 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1451 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1452 1453 if (ret < 0) { 1454 cq->head -= cqe_idx; 1455 return ret; 1456 } 1457 1458 if (ret == 0) 1459 break; 1460 1461 cq->head++; 1462 } 1463 1464 return cqe_idx; 1465 } 1466 1467 static void 1468 mana_gd_intr(void *arg) 1469 { 1470 struct gdma_irq_context *gic = arg; 1471 1472 if (gic->handler) { 1473 gic->handler(gic->arg); 1474 } 1475 } 1476 1477 int 1478 mana_gd_alloc_res_map(uint32_t res_avail, 1479 struct gdma_resource *r, const char *lock_name) 1480 { 1481 int n = howmany(res_avail, BITS_PER_LONG); 1482 1483 r->map = 1484 malloc(n * sizeof(unsigned long), M_DEVBUF, M_WAITOK | M_ZERO); 1485 if (!r->map) 1486 return ENOMEM; 1487 1488 r->size = res_avail; 1489 mtx_init(&r->lock_spin, lock_name, NULL, MTX_SPIN); 1490 1491 mana_dbg(NULL, 1492 "total res %u, total number of unsigned longs %u\n", 1493 r->size, n); 1494 return (0); 1495 } 1496 1497 void 1498 mana_gd_free_res_map(struct gdma_resource *r) 1499 { 1500 if (!r || !r->map) 1501 return; 1502 1503 free(r->map, M_DEVBUF); 1504 r->map = NULL; 1505 r->size = 0; 1506 } 1507 1508 static void 1509 mana_gd_init_registers(struct gdma_context *gc) 1510 { 1511 uintptr_t bar0_va = rman_get_bushandle(gc->bar0); 1512 vm_paddr_t bar0_pa = rman_get_start(gc->bar0); 1513 1514 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 1515 1516 gc->db_page_base = 1517 (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET)); 1518 1519 gc->phys_db_page_base = 1520 bar0_pa + mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 1521 1522 gc->shm_base = 1523 (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_SHM_OFFSET)); 1524 1525 mana_dbg(NULL, "db_page_size 0x%xx, db_page_base %p," 1526 " shm_base %p\n", 1527 gc->db_page_size, gc->db_page_base, gc->shm_base); 1528 } 1529 1530 static struct resource * 1531 mana_gd_alloc_bar(device_t dev, int bar) 1532 { 1533 struct resource *res = NULL; 1534 struct pci_map *pm; 1535 int rid, type; 1536 1537 if (bar < 0 || bar > PCIR_MAX_BAR_0) 1538 goto alloc_bar_out; 1539 1540 pm = pci_find_bar(dev, PCIR_BAR(bar)); 1541 if (!pm) 1542 goto alloc_bar_out; 1543 1544 if (PCI_BAR_IO(pm->pm_value)) 1545 type = SYS_RES_IOPORT; 1546 else 1547 type = SYS_RES_MEMORY; 1548 if (type < 0) 1549 goto alloc_bar_out; 1550 1551 rid = PCIR_BAR(bar); 1552 res = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE); 1553 #if defined(__amd64__) 1554 if (res) 1555 mana_dbg(NULL, "bar %d: rid 0x%x, type 0x%jx," 1556 " handle 0x%jx\n", 1557 bar, rid, res->r_bustag, res->r_bushandle); 1558 #endif 1559 1560 alloc_bar_out: 1561 return (res); 1562 } 1563 1564 static void 1565 mana_gd_free_pci_res(struct gdma_context *gc) 1566 { 1567 if (!gc || gc->dev) 1568 return; 1569 1570 if (gc->bar0 != NULL) { 1571 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1572 PCIR_BAR(GDMA_BAR0), gc->bar0); 1573 } 1574 1575 if (gc->msix != NULL) { 1576 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1577 gc->msix_rid, gc->msix); 1578 } 1579 } 1580 1581 static int 1582 mana_gd_setup_irqs(device_t dev) 1583 { 1584 unsigned int max_queues_per_port = mp_ncpus; 1585 struct gdma_context *gc = device_get_softc(dev); 1586 struct gdma_irq_context *gic; 1587 unsigned int max_irqs; 1588 int nvec; 1589 int rc, rcc, i; 1590 1591 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1592 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1593 1594 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1595 max_irqs = max_queues_per_port + 1; 1596 1597 nvec = max_irqs; 1598 rc = pci_alloc_msix(dev, &nvec); 1599 if (unlikely(rc != 0)) { 1600 device_printf(dev, 1601 "Failed to allocate MSIX, vectors %d, error: %d\n", 1602 nvec, rc); 1603 rc = ENOSPC; 1604 goto err_setup_irq_alloc; 1605 } 1606 1607 if (nvec != max_irqs) { 1608 if (nvec == 1) { 1609 device_printf(dev, 1610 "Not enough number of MSI-x allocated: %d\n", 1611 nvec); 1612 rc = ENOSPC; 1613 goto err_setup_irq_release; 1614 } 1615 device_printf(dev, "Allocated only %d MSI-x (%d requested)\n", 1616 nvec, max_irqs); 1617 } 1618 1619 gc->irq_contexts = malloc(nvec * sizeof(struct gdma_irq_context), 1620 M_DEVBUF, M_WAITOK | M_ZERO); 1621 if (!gc->irq_contexts) { 1622 rc = ENOMEM; 1623 goto err_setup_irq_release; 1624 } 1625 1626 for (i = 0; i < nvec; i++) { 1627 gic = &gc->irq_contexts[i]; 1628 gic->msix_e.entry = i; 1629 /* Vector starts from 1. */ 1630 gic->msix_e.vector = i + 1; 1631 gic->handler = NULL; 1632 gic->arg = NULL; 1633 1634 gic->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1635 &gic->msix_e.vector, RF_ACTIVE | RF_SHAREABLE); 1636 if (unlikely(gic->res == NULL)) { 1637 rc = ENOMEM; 1638 device_printf(dev, "could not allocate resource " 1639 "for irq vector %d\n", gic->msix_e.vector); 1640 goto err_setup_irq; 1641 } 1642 1643 rc = bus_setup_intr(dev, gic->res, 1644 INTR_TYPE_NET | INTR_MPSAFE, NULL, mana_gd_intr, 1645 gic, &gic->cookie); 1646 if (unlikely(rc != 0)) { 1647 device_printf(dev, "failed to register interrupt " 1648 "handler for irq %ju vector %d: error %d\n", 1649 rman_get_start(gic->res), gic->msix_e.vector, rc); 1650 goto err_setup_irq; 1651 } 1652 gic->requested = true; 1653 1654 mana_dbg(NULL, "added msix vector %d irq %ju\n", 1655 gic->msix_e.vector, rman_get_start(gic->res)); 1656 } 1657 1658 rc = mana_gd_alloc_res_map(nvec, &gc->msix_resource, 1659 "gdma msix res lock"); 1660 if (rc != 0) { 1661 device_printf(dev, "failed to allocate memory " 1662 "for msix bitmap\n"); 1663 goto err_setup_irq; 1664 } 1665 1666 gc->max_num_msix = nvec; 1667 gc->num_msix_usable = nvec; 1668 1669 mana_dbg(NULL, "setup %d msix interrupts\n", nvec); 1670 1671 return (0); 1672 1673 err_setup_irq: 1674 for (; i >= 0; i--) { 1675 gic = &gc->irq_contexts[i]; 1676 rcc = 0; 1677 1678 /* 1679 * If gic->requested is true, we need to free both intr and 1680 * resources. 1681 */ 1682 if (gic->requested) 1683 rcc = bus_teardown_intr(dev, gic->res, gic->cookie); 1684 if (unlikely(rcc != 0)) 1685 device_printf(dev, "could not release " 1686 "irq vector %d, error: %d\n", 1687 gic->msix_e.vector, rcc); 1688 1689 rcc = 0; 1690 if (gic->res != NULL) { 1691 rcc = bus_release_resource(dev, SYS_RES_IRQ, 1692 gic->msix_e.vector, gic->res); 1693 } 1694 if (unlikely(rcc != 0)) 1695 device_printf(dev, "dev has no parent while " 1696 "releasing resource for irq vector %d\n", 1697 gic->msix_e.vector); 1698 gic->requested = false; 1699 gic->res = NULL; 1700 } 1701 1702 free(gc->irq_contexts, M_DEVBUF); 1703 gc->irq_contexts = NULL; 1704 err_setup_irq_release: 1705 pci_release_msi(dev); 1706 err_setup_irq_alloc: 1707 return (rc); 1708 } 1709 1710 static void 1711 mana_gd_remove_irqs(device_t dev) 1712 { 1713 struct gdma_context *gc = device_get_softc(dev); 1714 struct gdma_irq_context *gic; 1715 int rc, i; 1716 1717 mana_gd_free_res_map(&gc->msix_resource); 1718 1719 for (i = 0; i < gc->max_num_msix; i++) { 1720 gic = &gc->irq_contexts[i]; 1721 if (gic->requested) { 1722 rc = bus_teardown_intr(dev, gic->res, gic->cookie); 1723 if (unlikely(rc != 0)) { 1724 device_printf(dev, "failed to tear down " 1725 "irq vector %d, error: %d\n", 1726 gic->msix_e.vector, rc); 1727 } 1728 gic->requested = false; 1729 } 1730 1731 if (gic->res != NULL) { 1732 rc = bus_release_resource(dev, SYS_RES_IRQ, 1733 gic->msix_e.vector, gic->res); 1734 if (unlikely(rc != 0)) { 1735 device_printf(dev, "dev has no parent while " 1736 "releasing resource for irq vector %d\n", 1737 gic->msix_e.vector); 1738 } 1739 gic->res = NULL; 1740 } 1741 } 1742 1743 gc->max_num_msix = 0; 1744 gc->num_msix_usable = 0; 1745 free(gc->irq_contexts, M_DEVBUF); 1746 gc->irq_contexts = NULL; 1747 1748 pci_release_msi(dev); 1749 } 1750 1751 static int 1752 mana_gd_probe(device_t dev) 1753 { 1754 mana_vendor_id_t *ent; 1755 char adapter_name[60]; 1756 uint16_t pci_vendor_id = 0; 1757 uint16_t pci_device_id = 0; 1758 1759 pci_vendor_id = pci_get_vendor(dev); 1760 pci_device_id = pci_get_device(dev); 1761 1762 ent = mana_id_table; 1763 while (ent->vendor_id != 0) { 1764 if ((pci_vendor_id == ent->vendor_id) && 1765 (pci_device_id == ent->device_id)) { 1766 mana_dbg(NULL, "vendor=%x device=%x\n", 1767 pci_vendor_id, pci_device_id); 1768 1769 sprintf(adapter_name, DEVICE_DESC); 1770 device_set_desc_copy(dev, adapter_name); 1771 return (BUS_PROBE_DEFAULT); 1772 } 1773 1774 ent++; 1775 } 1776 1777 return (ENXIO); 1778 } 1779 1780 /** 1781 * mana_attach - Device Initialization Routine 1782 * @dev: device information struct 1783 * 1784 * Returns 0 on success, otherwise on failure. 1785 * 1786 * mana_attach initializes a GDMA adapter identified by a device structure. 1787 **/ 1788 static int 1789 mana_gd_attach(device_t dev) 1790 { 1791 struct gdma_context *gc; 1792 int msix_rid; 1793 int rc; 1794 1795 gc = device_get_softc(dev); 1796 gc->dev = dev; 1797 1798 pci_enable_io(dev, SYS_RES_IOPORT); 1799 pci_enable_io(dev, SYS_RES_MEMORY); 1800 1801 pci_enable_busmaster(dev); 1802 1803 gc->bar0 = mana_gd_alloc_bar(dev, GDMA_BAR0); 1804 if (unlikely(gc->bar0 == NULL)) { 1805 device_printf(dev, 1806 "unable to allocate bus resource for bar0!\n"); 1807 rc = ENOMEM; 1808 goto err_disable_dev; 1809 } 1810 1811 /* Store bar0 tage and handle for quick access */ 1812 gc->gd_bus.bar0_t = rman_get_bustag(gc->bar0); 1813 gc->gd_bus.bar0_h = rman_get_bushandle(gc->bar0); 1814 1815 /* Map MSI-x vector table */ 1816 msix_rid = pci_msix_table_bar(dev); 1817 1818 mana_dbg(NULL, "msix_rid 0x%x\n", msix_rid); 1819 1820 gc->msix = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1821 &msix_rid, RF_ACTIVE); 1822 if (unlikely(gc->msix == NULL)) { 1823 device_printf(dev, 1824 "unable to allocate bus resource for msix!\n"); 1825 rc = ENOMEM; 1826 goto err_free_pci_res; 1827 } 1828 gc->msix_rid = msix_rid; 1829 1830 if (unlikely(gc->gd_bus.bar0_h == 0)) { 1831 device_printf(dev, "failed to map bar0!\n"); 1832 rc = ENXIO; 1833 goto err_free_pci_res; 1834 } 1835 1836 mana_gd_init_registers(gc); 1837 1838 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1839 1840 rc = mana_gd_setup_irqs(dev); 1841 if (rc) { 1842 goto err_free_pci_res; 1843 } 1844 1845 sx_init(&gc->eq_test_event_sx, "gdma test event sx"); 1846 1847 rc = mana_hwc_create_channel(gc); 1848 if (rc) { 1849 mana_dbg(NULL, "Failed to create hwc channel\n"); 1850 if (rc == EIO) 1851 goto err_clean_up_gdma; 1852 else 1853 goto err_remove_irq; 1854 } 1855 1856 rc = mana_gd_verify_vf_version(dev); 1857 if (rc) { 1858 mana_dbg(NULL, "Failed to verify vf\n"); 1859 goto err_clean_up_gdma; 1860 } 1861 1862 rc = mana_gd_query_max_resources(dev); 1863 if (rc) { 1864 mana_dbg(NULL, "Failed to query max resources\n"); 1865 goto err_clean_up_gdma; 1866 } 1867 1868 rc = mana_gd_detect_devices(dev); 1869 if (rc) { 1870 mana_dbg(NULL, "Failed to detect mana device\n"); 1871 goto err_clean_up_gdma; 1872 } 1873 1874 rc = mana_probe(&gc->mana); 1875 if (rc) { 1876 mana_dbg(NULL, "Failed to probe mana device\n"); 1877 goto err_clean_up_gdma; 1878 } 1879 1880 return (0); 1881 1882 err_clean_up_gdma: 1883 mana_hwc_destroy_channel(gc); 1884 err_remove_irq: 1885 mana_gd_remove_irqs(dev); 1886 err_free_pci_res: 1887 mana_gd_free_pci_res(gc); 1888 err_disable_dev: 1889 pci_disable_busmaster(dev); 1890 1891 return(rc); 1892 } 1893 1894 /** 1895 * mana_detach - Device Removal Routine 1896 * @pdev: device information struct 1897 * 1898 * mana_detach is called by the device subsystem to alert the driver 1899 * that it should release a PCI device. 1900 **/ 1901 static int 1902 mana_gd_detach(device_t dev) 1903 { 1904 struct gdma_context *gc = device_get_softc(dev); 1905 1906 mana_remove(&gc->mana); 1907 1908 mana_hwc_destroy_channel(gc); 1909 1910 mana_gd_remove_irqs(dev); 1911 1912 mana_gd_free_pci_res(gc); 1913 1914 pci_disable_busmaster(dev); 1915 1916 return (bus_generic_detach(dev)); 1917 } 1918 1919 1920 /********************************************************************* 1921 * FreeBSD Device Interface Entry Points 1922 *********************************************************************/ 1923 1924 static device_method_t mana_methods[] = { 1925 /* Device interface */ 1926 DEVMETHOD(device_probe, mana_gd_probe), 1927 DEVMETHOD(device_attach, mana_gd_attach), 1928 DEVMETHOD(device_detach, mana_gd_detach), 1929 DEVMETHOD_END 1930 }; 1931 1932 static driver_t mana_driver = { 1933 "mana", mana_methods, sizeof(struct gdma_context), 1934 }; 1935 1936 DRIVER_MODULE(mana, pci, mana_driver, 0, 0); 1937 MODULE_PNP_INFO("U16:vendor;U16:device", pci, mana, mana_id_table, 1938 nitems(mana_id_table) - 1); 1939 MODULE_DEPEND(mana, pci, 1, 1, 1); 1940 MODULE_DEPEND(mana, ether, 1, 1, 1); 1941 1942 /*********************************************************************/
Cache object: 67954b9b769f33b56042b6ad17ea5f2d
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