1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Microsoft Corp.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 *
32 */
33
34 #ifndef _HW_CHANNEL_H
35 #define _HW_CHANNEL_H
36
37 #include <sys/sema.h>
38
39 #define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ 4
40
41 #define HW_CHANNEL_MAX_REQUEST_SIZE 0x1000
42 #define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000
43
44 #define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1
45
46 #define HWC_INIT_DATA_CQID 1
47 #define HWC_INIT_DATA_RQID 2
48 #define HWC_INIT_DATA_SQID 3
49 #define HWC_INIT_DATA_QUEUE_DEPTH 4
50 #define HWC_INIT_DATA_MAX_REQUEST 5
51 #define HWC_INIT_DATA_MAX_RESPONSE 6
52 #define HWC_INIT_DATA_MAX_NUM_CQS 7
53 #define HWC_INIT_DATA_PDID 8
54 #define HWC_INIT_DATA_GPA_MKEY 9
55
56 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of
57 * them are naturally aligned and hence don't need __packed.
58 */
59
60 union hwc_init_eq_id_db {
61 uint32_t as_uint32;
62
63 struct {
64 uint32_t eq_id : 16;
65 uint32_t doorbell: 16;
66 };
67 }; /* HW DATA */
68
69 union hwc_init_type_data {
70 uint32_t as_uint32;
71
72 struct {
73 uint32_t value : 24;
74 uint32_t type : 8;
75 };
76 }; /* HW DATA */
77
78 struct hwc_rx_oob {
79 uint32_t type : 6;
80 uint32_t eom : 1;
81 uint32_t som : 1;
82 uint32_t vendor_err : 8;
83 uint32_t reserved1 : 16;
84
85 uint32_t src_virt_wq : 24;
86 uint32_t src_vfid : 8;
87
88 uint32_t reserved2;
89
90 union {
91 uint32_t wqe_addr_low;
92 uint32_t wqe_offset;
93 };
94
95 uint32_t wqe_addr_high;
96
97 uint32_t client_data_unit : 14;
98 uint32_t reserved3 : 18;
99
100 uint32_t tx_oob_data_size;
101
102 uint32_t chunk_offset : 21;
103 uint32_t reserved4 : 11;
104 }; /* HW DATA */
105
106 struct hwc_tx_oob {
107 uint32_t reserved1;
108
109 uint32_t reserved2;
110
111 uint32_t vrq_id : 24;
112 uint32_t dest_vfid : 8;
113
114 uint32_t vrcq_id : 24;
115 uint32_t reserved3 : 8;
116
117 uint32_t vscq_id : 24;
118 uint32_t loopback : 1;
119 uint32_t lso_override: 1;
120 uint32_t dest_pf : 1;
121 uint32_t reserved4 : 5;
122
123 uint32_t vsq_id : 24;
124 uint32_t reserved5 : 8;
125 }; /* HW DATA */
126
127 struct hwc_work_request {
128 void *buf_va;
129 void *buf_sge_addr;
130 uint32_t buf_len;
131 uint32_t msg_size;
132
133 struct gdma_wqe_request wqe_req;
134 struct hwc_tx_oob tx_oob;
135
136 struct gdma_sge sge;
137 };
138
139 /* hwc_dma_buf represents the array of in-flight WQEs.
140 * mem_info as know as the GDMA mapped memory is partitioned and used by
141 * in-flight WQEs.
142 * The number of WQEs is determined by the number of in-flight messages.
143 */
144 struct hwc_dma_buf {
145 struct gdma_mem_info mem_info;
146
147 uint32_t gpa_mkey;
148
149 uint32_t num_reqs;
150 struct hwc_work_request reqs[];
151 };
152
153 typedef void hwc_rx_event_handler_t(void *ctx, uint32_t gdma_rxq_id,
154 const struct hwc_rx_oob *rx_oob);
155
156 typedef void hwc_tx_event_handler_t(void *ctx, uint32_t gdma_txq_id,
157 const struct hwc_rx_oob *rx_oob);
158
159 struct hwc_cq {
160 struct hw_channel_context *hwc;
161
162 struct gdma_queue *gdma_cq;
163 struct gdma_queue *gdma_eq;
164 struct gdma_comp *comp_buf;
165 uint16_t queue_depth;
166
167 hwc_rx_event_handler_t *rx_event_handler;
168 void *rx_event_ctx;
169
170 hwc_tx_event_handler_t *tx_event_handler;
171 void *tx_event_ctx;
172 };
173
174 struct hwc_wq {
175 struct hw_channel_context *hwc;
176
177 struct gdma_queue *gdma_wq;
178 struct hwc_dma_buf *msg_buf;
179 uint16_t queue_depth;
180
181 struct hwc_cq *hwc_cq;
182 };
183
184 struct hwc_caller_ctx {
185 struct completion comp_event;
186 void *output_buf;
187 uint32_t output_buflen;
188
189 uint32_t error; /* Error code */
190 uint32_t status_code;
191 };
192
193 struct hw_channel_context {
194 struct gdma_dev *gdma_dev;
195 device_t dev;
196
197 uint16_t num_inflight_msg;
198 uint32_t max_req_msg_size;
199
200 uint16_t hwc_init_q_depth_max;
201 uint32_t hwc_init_max_req_msg_size;
202 uint32_t hwc_init_max_resp_msg_size;
203
204 struct completion hwc_init_eqe_comp;
205
206 struct hwc_wq *rxq;
207 struct hwc_wq *txq;
208 struct hwc_cq *cq;
209
210 struct sema sema;
211 struct gdma_resource inflight_msg_res;
212
213 struct hwc_caller_ctx *caller_ctx;
214 };
215
216 int mana_hwc_create_channel(struct gdma_context *gc);
217 void mana_hwc_destroy_channel(struct gdma_context *gc);
218
219 int mana_hwc_send_request(struct hw_channel_context *hwc, uint32_t req_len,
220 const void *req, uint32_t resp_len, void *resp);
221
222 #endif /* _HW_CHANNEL_H */
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