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sys/dev/marvell/gtpci.c
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1 /* $NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $"); 42 43 #include "opt_marvell.h" 44 #include <sys/param.h> 45 #include <sys/device.h> 46 #include <sys/extent.h> 47 #include <sys/malloc.h> 48 #include <lib/libkern/libkern.h> 49 50 #define _BUS_SPACE_PRIVATE 51 #define _BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pciconf.h> 58 #include <dev/marvell/gtreg.h> 59 #include <dev/marvell/gtvar.h> 60 #include <dev/marvell/gtintrreg.h> 61 #include <dev/marvell/gtpcireg.h> 62 #include <dev/marvell/gtpcivar.h> 63 #include <dev/marvell/gtvar.h> 64 65 static int gtpci_error_intr(void *); 66 67 static void gtpci_bus_init(struct gtpci_chipset *); 68 69 static void gtpci_bus_attach_hook(struct device *, struct device *, 70 struct pcibus_attach_args *); 71 static int gtpci_bus_maxdevs(pci_chipset_tag_t, int); 72 73 static const char * 74 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 75 static const struct evcnt * 76 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 77 static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 78 int, int (*)(void *), void *); 79 static void gtpci_intr_disestablish(pci_chipset_tag_t, void *); 80 81 #ifdef DEBUG 82 int gtpci_debug = 0; 83 #endif 84 85 struct gtpci_softc { 86 struct device gtpci_dev; 87 struct gtpci_chipset gtpci_gtpc; 88 }; 89 90 static int gtpci_cfprint(void *, const char *); 91 static int gtpci_match(struct device *, struct cfdata *, void *); 92 static void gtpci_attach(struct device *, struct device *, void *); 93 94 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc), 95 gtpci_match, gtpci_attach, NULL, NULL); 96 97 extern struct cfdriver gtpci_cd; 98 99 const struct pci_chipset_functions gtpci_functions = { 100 gtpci_bus_attach_hook, 101 gtpci_bus_maxdevs, 102 gtpci_md_bus_devorder, 103 104 gtpci_make_tag, 105 gtpci_decompose_tag, 106 107 gtpci_conf_read, 108 gtpci_conf_write, 109 gtpci_md_conf_hook, 110 gtpci_md_conf_interrupt, 111 112 gtpci_md_intr_map, 113 gtpci_intr_string, 114 gtpci_intr_evcnt, 115 gtpci_intr_establish, 116 gtpci_intr_disestablish 117 }; 118 119 static const int pci_irqs[2][3] = { 120 { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 }, 121 { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 }, 122 }; 123 124 static const struct pci_init { 125 int bar_regno; 126 u_int32_t bar_enable; 127 bus_addr_t low_decode; 128 bus_addr_t high_decode; 129 bus_addr_t barsize; 130 bus_addr_t accctl_high; 131 bus_addr_t accctl_low; 132 bus_addr_t accctl_top; 133 } pci_initinfo[2][4] = { 134 { 135 { 136 0x10, PCI_BARE_SCS0En, 137 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 138 PCI_SCS0_BAR_SIZE(0), 139 PCI_ACCESS_CONTROL_BASE_HIGH(0, 0), 140 PCI_ACCESS_CONTROL_BASE_LOW(0, 0), 141 PCI_ACCESS_CONTROL_TOP(0, 0), 142 }, { 143 0x14, PCI_BARE_SCS1En, 144 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 145 PCI_SCS1_BAR_SIZE(0), 146 PCI_ACCESS_CONTROL_BASE_HIGH(0, 1), 147 PCI_ACCESS_CONTROL_BASE_LOW(0, 1), 148 PCI_ACCESS_CONTROL_TOP(0, 1), 149 }, { 150 0x18, PCI_BARE_SCS2En, 151 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 152 PCI_SCS2_BAR_SIZE(0), 153 PCI_ACCESS_CONTROL_BASE_HIGH(0, 2), 154 PCI_ACCESS_CONTROL_BASE_LOW(0, 2), 155 PCI_ACCESS_CONTROL_TOP(0, 2), 156 }, { 157 0x1c, PCI_BARE_SCS3En, 158 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 159 PCI_SCS3_BAR_SIZE(0), 160 PCI_ACCESS_CONTROL_BASE_HIGH(0, 3), 161 PCI_ACCESS_CONTROL_BASE_LOW(0, 3), 162 PCI_ACCESS_CONTROL_TOP(0, 3), 163 }, 164 }, { 165 { 166 0x10, PCI_BARE_SCS0En, 167 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 168 PCI_SCS0_BAR_SIZE(1), 169 PCI_ACCESS_CONTROL_BASE_HIGH(1, 0), 170 PCI_ACCESS_CONTROL_BASE_LOW(1, 0), 171 PCI_ACCESS_CONTROL_TOP(1, 0), 172 }, { 173 0x14, PCI_BARE_SCS1En, 174 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 175 PCI_SCS1_BAR_SIZE(1), 176 PCI_ACCESS_CONTROL_BASE_HIGH(1, 1), 177 PCI_ACCESS_CONTROL_BASE_LOW(1, 1), 178 PCI_ACCESS_CONTROL_TOP(1, 1), 179 }, { 180 0x18, PCI_BARE_SCS2En, 181 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 182 PCI_SCS2_BAR_SIZE(1), 183 PCI_ACCESS_CONTROL_BASE_HIGH(1, 2), 184 PCI_ACCESS_CONTROL_BASE_LOW(1, 2), 185 PCI_ACCESS_CONTROL_TOP(1, 2), 186 }, { 187 0x1c, PCI_BARE_SCS3En, 188 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 189 PCI_SCS3_BAR_SIZE(1), 190 PCI_ACCESS_CONTROL_BASE_HIGH(1, 3), 191 PCI_ACCESS_CONTROL_BASE_LOW(1, 3), 192 PCI_ACCESS_CONTROL_TOP(1, 3), 193 }, 194 } 195 }; 196 197 int 198 gtpci_match(struct device *parent, struct cfdata *self, void *aux) 199 { 200 struct gt_softc * const gt = (struct gt_softc *) parent; 201 struct gt_attach_args * const ga = aux; 202 203 return GT_PCIOK(gt, ga, >pci_cd); 204 } 205 206 int 207 gtpci_cfprint(void *aux, const char *pnp) 208 { 209 struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux; 210 211 if (pnp) 212 aprint_normal("pci at %s", pnp); 213 214 aprint_normal(" bus %d", pba->pba_bus); 215 216 return (UNCONF); 217 } 218 219 void 220 gtpci_attach(struct device *parent, struct device *self, void *aux) 221 { 222 struct pcibus_attach_args pba; 223 struct gt_attach_args * const ga = aux; 224 struct gt_softc * const gt = (struct gt_softc *) parent; 225 struct gtpci_softc * const gtp = (struct gtpci_softc *) self; 226 struct gtpci_chipset * const gtpc = >p->gtpci_gtpc; 227 struct pci_chipset * const pc = >pc->gtpc_pc; 228 const int busno = ga->ga_unit; 229 uint32_t data; 230 231 GT_PCIFOUND(gt, ga); 232 233 pc->pc_funcs = >pci_functions; 234 pc->pc_parent = self; 235 236 gtpc->gtpc_busno = busno; 237 gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno); 238 gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno); 239 gtpc->gtpc_syncreg = PCI_SYNC_REG(busno); 240 gtpc->gtpc_gt_memt = ga->ga_memt; 241 gtpc->gtpc_gt_memh = ga->ga_memh; 242 243 /* 244 * Let's find out where we are located. 245 */ 246 data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno)); 247 gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc, 248 PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0); 249 250 251 switch (busno) { 252 case 0: 253 gtpc->gtpc_io_bs = gt->gt_pci0_iot; 254 gtpc->gtpc_mem_bs = gt->gt_pci0_memt; 255 gtpc->gtpc_host = gt->gt_pci0_host; 256 break; 257 case 1: 258 gtpc->gtpc_io_bs = gt->gt_pci1_iot; 259 gtpc->gtpc_mem_bs = gt->gt_pci1_memt; 260 gtpc->gtpc_host = gt->gt_pci1_host; 261 break; 262 default: 263 break; 264 } 265 266 /* 267 * If no bus_spaces exist, then it's been disabled. 268 */ 269 if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) { 270 aprint_normal(": disabled\n"); 271 return; 272 } 273 274 aprint_normal("\n"); 275 276 /* 277 * clear any pre-existing error interrupt(s) 278 * clear latched pci error registers 279 * establish ISRs for PCI errors 280 * enable PCI error interrupts 281 */ 282 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0); 283 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0); 284 (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 285 (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 286 (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 287 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 288 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 289 if (gtpc->gtpc_host) { 290 intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, 291 IPL_GTERR, gtpci_error_intr, pc); 292 intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, 293 IPL_GTERR, gtpci_error_intr, pc); 294 intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, 295 IPL_GTERR, gtpci_error_intr, pc); 296 aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n", 297 pc->pc_parent->dv_xname, "pci", busno, 298 intr_string(pci_irqs[gtpc->gtpc_busno][0]), 299 intr_string(pci_irqs[gtpc->gtpc_busno][1]), 300 intr_string(pci_irqs[gtpc->gtpc_busno][2])); 301 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 302 PCI_SERRMSK_ALL_ERRS); 303 } 304 305 /* 306 * Fill in the pci_bus_attach_args 307 */ 308 pba.pba_pc = pc; 309 pba.pba_bus = 0; 310 pba.pba_busname = "pci"; 311 pba.pba_iot = gtpc->gtpc_io_bs; 312 pba.pba_memt = gtpc->gtpc_mem_bs; 313 pba.pba_dmat = gt->gt_dmat; 314 pba.pba_flags = 0; 315 if (pba.pba_iot != NULL) 316 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 317 if (pba.pba_memt != NULL) 318 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 319 320 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 321 if (data & PCI_CMD_MRdMul) 322 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 323 if (data & PCI_CMD_MRdLine) 324 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 325 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 326 327 gt_watchdog_service(); 328 /* 329 * Configure the pci bus. 330 */ 331 config_found(self, &pba, gtpci_cfprint); 332 333 gt_watchdog_service(); 334 335 } 336 337 void 338 gtpci_bus_init(struct gtpci_chipset *gtpc) 339 { 340 const struct pci_init *pi; 341 uint32_t data, datal, datah; 342 pcireg_t pcidata; 343 int i; 344 345 /* 346 * disable all BARs to start. 347 */ 348 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 349 0xffffffff); 350 351 #ifndef GT_PCI0_EXT_ARBITER 352 #define GT_PCI0_EXT_ARBITER 0 353 #endif 354 #ifndef GT_PCI1_EXT_ARBITER 355 #define GT_PCI1_EXT_ARBITER 0 356 #endif 357 358 if (gtpc->gtpc_host && 359 ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) || 360 (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) { 361 /* 362 * Enable internal arbiter 363 */ 364 data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno)); 365 data |= PCI_ARBCTL_EN; 366 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data); 367 } else { 368 /* 369 * Make sure the internal arbiter is disabled 370 */ 371 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0); 372 } 373 374 /* 375 * Make the GT reflects reality. 376 * We always enable internal memory. 377 */ 378 if (gtpc->gtpc_host) { 379 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 380 0x20) & 0xfff; 381 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20, 382 GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | 383 pcidata); 384 } 385 data = PCI_BARE_IntMemEn; 386 387 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) 388 gtpci_write(gtpc, pi->barsize, 0); 389 390 if (gtpc->gtpc_host) { 391 /* 392 * Enable bus master access (needed for config access). 393 */ 394 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 395 PCI_COMMAND_STATUS_REG); 396 pcidata |= PCI_COMMAND_MASTER_ENABLE; 397 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 398 PCI_COMMAND_STATUS_REG, pcidata); 399 } 400 401 /* 402 * Map each SCS BAR to correspond to each SDRAM decode register. 403 */ 404 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) { 405 datal = gtpci_read(gtpc, pi->low_decode); 406 datah = gtpci_read(gtpc, pi->high_decode); 407 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 408 pi->bar_regno); 409 gtpci_write(gtpc, pi->accctl_high, 0); 410 if (datal < datah) { 411 datal &= 0xfff; 412 pcidata &= 0xfff; 413 pcidata |= datal << 20; 414 data |= pi->bar_enable; 415 datah -= datal; 416 datal |= PCI_ACCCTLBASEL_PrefetchEn| 417 PCI_ACCCTLBASEL_RdPrefetch| 418 PCI_ACCCTLBASEL_RdLinePrefetch| 419 PCI_ACCCTLBASEL_RdMulPrefetch| 420 PCI_ACCCTLBASEL_WBurst_8_QW| 421 PCI_ACCCTLBASEL_PCISwap_NoSwap; 422 gtpci_write(gtpc, pi->accctl_low, datal); 423 } else { 424 pcidata &= 0xfff; 425 datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap; 426 datah = 0; 427 } 428 gtpci_write(gtpc, pi->barsize, 429 datah ? ((datah << 20) | 0xff000) : 0); 430 if (gtpc->gtpc_host) { 431 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 432 pi->bar_regno, pcidata); 433 } 434 gtpci_write(gtpc, pi->accctl_low, datal); 435 gtpci_write(gtpc, pi->accctl_top, datah); 436 } 437 438 /* 439 * Now re-enable those BARs that are real. 440 */ 441 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 442 ~data); 443 444 if (gtpc->gtpc_host) { 445 /* 446 * Enable I/O and memory (bus master is already enabled) access. 447 */ 448 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 449 PCI_COMMAND_STATUS_REG); 450 pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 451 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 452 PCI_COMMAND_STATUS_REG, pcidata); 453 } 454 } 455 456 void 457 gtpci_bus_attach_hook(struct device *parent, struct device *self, 458 struct pcibus_attach_args *pba) 459 { 460 struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc; 461 uint32_t data; 462 #if defined(DEBUG) 463 pcitag_t tag; 464 int bus, dev; 465 int i; 466 #endif 467 468 if (gtpc->gtpc_pc.pc_parent != parent) 469 return; 470 471 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 472 aprint_normal(": id %d%s%s%s%s%s%s%s%s", 473 PCI_MODE_PciID_GET(data), 474 (data & PCI_MODE_Pci64) ? ", 64bit" : "", 475 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "", 476 (data & PCI_MODE_VPD) ? ", VPD" : "", 477 (data & PCI_MODE_MSI) ? ", MSI" : "", 478 (data & PCI_MODE_PMG) ? ", PMG" : "", 479 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "", 480 (data & PCI_MODE_BIST) ? ", BIST" : "", 481 (data & PCI_MODE_PRst) ? "" : ", PRst"); 482 483 #if 0 484 while ((data & PCI_MODE_PRst) == 0) { 485 DELAY(10); 486 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 487 aprint_normal("."); 488 } 489 #endif 490 491 gtpci_bus_init(gtpc); 492 gtpci_bus_configure(gtpc); 493 494 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 495 if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) { 496 aprint_normal("\n%s: ", self->dv_xname); 497 if (data & PCI_CMD_MSwapEn) { 498 switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) { 499 case PCI_CMD_MWordSwap: 500 aprint_normal(" mswap=w"); break; 501 case PCI_CMD_MByteSwap: 502 aprint_normal(" mswap=b"); break; 503 case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap: 504 aprint_normal(" mswap=b+w"); break; 505 case 0: 506 aprint_normal(" mswap=none"); break; 507 } 508 } 509 510 if (data & PCI_CMD_SSwapEn) { 511 switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) { 512 case PCI_CMD_SWordSwap: 513 aprint_normal(" sswap=w"); break; 514 case PCI_CMD_SByteSwap: 515 aprint_normal(" sswap=b"); break; 516 case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap: 517 aprint_normal(" sswap=b+w"); break; 518 case 0: 519 aprint_normal(" sswap=none"); break; 520 } 521 } 522 } 523 524 #if defined(DEBUG) 525 if (gtpci_debug == 0) 526 return; 527 528 data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno)); 529 aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data); 530 531 aprint_normal("\n%s: 0:0:0\n", self->dv_xname); 532 aprint_normal(" %sSCS0=%#010x", 533 (data & 1) ? "-" : "+", 534 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10)); 535 aprint_normal("/%#010x", gtpci_read(gtpc, 536 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno))); 537 aprint_normal(" remap %#010x\n", 538 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 539 540 aprint_normal(" %sSCS1=%#010x", 541 (data & 2) ? "-" : "+", 542 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14)); 543 aprint_normal("/%#010x", 544 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno))); 545 aprint_normal(" remap %#010x\n", 546 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 547 548 aprint_normal(" %sSCS2=%#010x", 549 (data & 4) ? "-" : "+", 550 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18)); 551 aprint_normal("/%#010x", 552 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno))); 553 aprint_normal(" remap %#010x\n", 554 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 555 556 aprint_normal(" %sSCS3=%#010x", 557 (data & 8) ? "-" : "+", 558 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c)); 559 aprint_normal("/%#010x", 560 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno))); 561 aprint_normal(" remap %#010x\n", 562 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 563 564 aprint_normal(" %sIMem=%#010x", 565 (data & PCI_BARE_IntMemEn) ? "-" : "+", 566 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20)); 567 aprint_normal("\n"); 568 aprint_normal(" %sIIO=%#010x", 569 (data & PCI_BARE_IntIOEn) ? "-" : "+", 570 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24)); 571 aprint_normal("\n"); 572 573 gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL); 574 tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1); 575 aprint_normal(" %sCS0=%#010x", 576 (data & PCI_BARE_CS0En) ? "-" : "+", 577 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 578 aprint_normal("/%#010x", 579 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno))); 580 aprint_normal(" remap %#010x\n", 581 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 582 583 aprint_normal(" %sCS1=%#010x", 584 (data & PCI_BARE_CS1En) ? "-" : "+", 585 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 586 aprint_normal("/%#010x", 587 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno))); 588 aprint_normal(" remap %#010x\n", 589 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 590 591 aprint_normal(" %sCS2=%#010x", 592 (data & PCI_BARE_CS2En) ? "-" : "+", 593 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 594 aprint_normal("/%#010x", 595 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno))); 596 aprint_normal(" remap %#010x\n", 597 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 598 599 aprint_normal(" %sCS3=%#010x", 600 (data & PCI_BARE_CS3En) ? "-" : "+", 601 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 602 aprint_normal("/%#010x", 603 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno))); 604 aprint_normal(" remap %#010x\n", 605 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 606 607 aprint_normal(" %sBootCS=%#010x", 608 (data & PCI_BARE_BootCSEn) ? "-" : "+", 609 gtpci_conf_read(>pc->gtpc_pc, tag, 0x20)); 610 aprint_normal("/%#010x", 611 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno))); 612 aprint_normal(" remap %#010x\n", 613 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno))); 614 615 tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2); 616 aprint_normal(" %sP2PM0=%#010x", 617 (data & PCI_BARE_P2PMem0En) ? "-" : "+", 618 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 619 aprint_normal("/%#010x", 620 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno))); 621 aprint_normal(" remap %#010x.%#010x\n", 622 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 623 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 624 625 aprint_normal(" %sP2PM1=%#010x", 626 (data & PCI_BARE_P2PMem1En) ? "-" : "+", 627 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 628 aprint_normal("/%#010x", 629 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno))); 630 aprint_normal(" remap %#010x.%#010x\n", 631 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 632 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 633 634 aprint_normal(" %sP2PIO=%#010x", 635 (data & PCI_BARE_P2PIOEn) ? "-" : "+", 636 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 637 aprint_normal("/%#010x", 638 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno))); 639 aprint_normal(" remap %#010x\n", 640 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 641 642 aprint_normal(" %sCPU=%#010x", 643 (data & PCI_BARE_CPUEn) ? "-" : "+", 644 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 645 aprint_normal("/%#010x", 646 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno))); 647 aprint_normal(" remap %#010x\n", 648 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 649 650 for (i = 0; i < 8; i++) { 651 aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i); 652 data = gtpci_read(gtpc, 653 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i)); 654 if (data) 655 aprint_normal("base=0x%08x.", data); 656 else 657 aprint_normal("base=0x"); 658 data = gtpci_read(gtpc, 659 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)); 660 printf("%08x cfg=0x%08x", data << 20, data & ~0xfff); 661 aprint_normal(" top=0x%03x00000", 662 gtpci_read(gtpc, 663 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i))); 664 } 665 #endif 666 } 667 668 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings; 669 670 int 671 gtpci_error_intr(void *arg) 672 { 673 pci_chipset_tag_t pc = arg; 674 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 675 uint32_t cause, mask, errmask; 676 u_int32_t alo, ahi, dlo, dhi, cmd; 677 int i; 678 679 cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno)); 680 errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno)); 681 cause &= errmask | 0xf8000000; 682 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause); 683 printf("%s: pci%d error: cause=%#x mask=%#x", 684 pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask); 685 if ((cause & 0xf8000000) == 0) { 686 printf(" ?\n"); 687 return 0; 688 } 689 690 for (i = 0, mask = 1; i <= 26; i++, mask += mask) 691 if (mask & cause) 692 printf(" %s", gtpci_error_strings[i]); 693 694 /* 695 * "no new data is latched until the PCI Error Low Address 696 * register is read. This means that PCI Error Low Address 697 * register must be the last register read by the interrupt 698 * handler." 699 */ 700 dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 701 dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 702 cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 703 ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 704 alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 705 printf("\n%s: pci%d error: %s cmd=%#x", 706 pc->pc_parent->dv_xname, gtpc->gtpc_busno, 707 gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd); 708 if (dhi == 0) 709 printf(" data=%08x", dlo); 710 else 711 printf(" data=%08x.%08x", dhi, dlo); 712 if (ahi == 0) 713 printf(" address=%08x\n", alo); 714 else 715 printf(" address=%08x.%08x\n", ahi, alo); 716 717 #if defined(DEBUG) && defined(DDB) 718 if (gtpci_debug > 1) 719 Debugger(); 720 #endif 721 return 1; 722 } 723 724 725 #if 0 726 void 727 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs, 728 struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi) 729 { 730 /* See how I/O space is configured. Read the base and top 731 * registers. 732 */ 733 paddr_t pbasel, pbaseh; 734 uint32_t datal, datah; 735 736 datal = gtpci_read(gtpc, lo); 737 datah = gtpci_read(gtpc, hi); 738 pbasel = GT_LowAddr_GET(datal); 739 pbaseh = GT_HighAddr_GET(datah); 740 /* 741 * If the start is greater than the end, ignore the region. 742 */ 743 if (pbaseh < pbasel) 744 return; 745 if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase 746 && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) { 747 bs->bs_regions[bs->bs_nregion].br_vbase = 748 gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask); 749 } 750 bs->bs_regions[bs->bs_nregion].br_pbase = pbasel; 751 if (bs->bs_flags & _BUS_SPACE_RELATIVE) { 752 bs->bs_regions[bs->bs_nregion].br_start = 0; 753 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel; 754 } else { 755 bs->bs_regions[bs->bs_nregion].br_start = pbasel; 756 bs->bs_regions[bs->bs_nregion].br_end = pbaseh; 757 } 758 bs->bs_nregion++; 759 } 760 #endif 761 762 /* 763 * Internal functions. 764 */ 765 int 766 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 767 { 768 return 32; 769 } 770 771 pcitag_t 772 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno) 773 { 774 return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0); 775 } 776 777 void 778 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 779 int *bp, int *dp, int *fp) 780 { 781 if (bp != NULL) 782 *bp = PCI_CFG_GET_BUSNO(tag); 783 if (dp != NULL) 784 *dp = PCI_CFG_GET_DEVNO(tag); 785 if (fp != NULL) 786 *fp = PCI_CFG_GET_FUNCNO(tag); 787 } 788 789 pcireg_t 790 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno) 791 { 792 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 793 #ifdef DIAGNOSTIC 794 if ((regno & 3) || (regno & ~0xff)) 795 panic("gtpci_conf_read: bad regno %#x\n", regno); 796 #endif 797 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 798 return gtpci_read(gtpc, gtpc->gtpc_cfgdata); 799 } 800 801 void 802 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data) 803 { 804 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 805 #ifdef DIAGNOSTIC 806 if ((regno & 3) || (regno & ~0xff)) 807 panic("gtpci_conf_write: bad regno %#x\n", regno); 808 #endif 809 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 810 gtpci_write(gtpc, gtpc->gtpc_cfgdata, data); 811 } 812 813 const char * 814 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih) 815 { 816 return intr_string(pih); 817 } 818 819 const struct evcnt * 820 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih) 821 { 822 return intr_evcnt(pih); 823 } 824 825 void * 826 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, 827 int ipl, int (*handler)(void *), void *arg) 828 { 829 return intr_establish(pih, IST_LEVEL, ipl, handler, arg); 830 } 831 832 void 833 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 834 { 835 intr_disestablish(cookie); 836 }
Cache object: 7dce50f0da866518361f0aebffc881c0
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