The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mc146818/mc146818reg.h

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    1 /*-
    2  * Copyright (c) 1995 Carnegie-Mellon University.
    3  * All rights reserved.
    4  *
    5  * Permission to use, copy, modify and distribute this software and
    6  * its documentation is hereby granted, provided that both the copyright
    7  * notice and this permission notice appear in all copies of the
    8  * software, derivative works or modified versions, and any portions
    9  * thereof, and that both notices appear in supporting documentation.
   10  *
   11  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   12  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
   13  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   14  *
   15  * Carnegie Mellon requests users of this software to return to
   16  *
   17  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   18  *  School of Computer Science
   19  *  Carnegie Mellon University
   20  *  Pittsburgh PA 15213-3890
   21  *
   22  * any improvements or extensions that they make and grant Carnegie the
   23  * rights to redistribute these changes.
   24  *
   25  *      $NetBSD: mc146818reg.h,v 1.9 2006/03/08 23:46:25 lukem Exp $
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 /*
   31  * Definitions for the Motorola MC146818A Real Time Clock.
   32  * They also apply for the (compatible) Dallas Semiconductor DS1287A RTC.
   33  *
   34  * Though there are undoubtedly other (better) sources, this material was
   35  * culled from the DEC "KN121 System Module Programmer's Reference
   36  * Information."
   37  *
   38  * The MC146818A has 16 registers.  The first 10 contain time-of-year
   39  * and alarm data.  The rest contain various control and status bits.
   40  *
   41  * To read or write the registers, one writes the register number to
   42  * the RTC's control port, then either reads from or writes the new
   43  * data to the RTC's data port.  Since the locations of these ports
   44  * and the method used to access them can be machine-dependent, the
   45  * low-level details of reading and writing the RTC's registers are
   46  * handled by machine-specific functions.
   47  *
   48  * The time-of-year and alarm data can be expressed in either binary
   49  * or BCD, and they are selected by a bit in register B.
   50  *
   51  * The "hour" time-of-year and alarm fields can either be expressed in
   52  * AM/PM format, or in 24-hour format.  If AM/PM format is chosen, the
   53  * hour fields can have the values: 1-12 and 81-92 (the latter being
   54  * PM).  If the 24-hour format is chosen, they can have the values
   55  * 0-24.  The hour format is selectable by a bit in register B.
   56  * (XXX IS AM/PM MODE DESCRIPTION CORRECT?)
   57  *
   58  * It is assumed the if systems are going to use BCD (rather than
   59  * binary) mode, or AM/PM hour format, they'll do the appropriate
   60  * conversions in machine-dependent code.  Also, if the clock is
   61  * switched between BCD and binary mode, or between AM/PM mode and
   62  * 24-hour mode, the time-of-day and alarm registers are NOT
   63  * automatically reset; they must be reprogrammed with correct values.
   64  */
   65 
   66 /*
   67  * The registers, and the bits within each register.
   68  */
   69 
   70 #define MC_SEC          0x0     /* Time of year: seconds (0-59) */
   71 #define MC_ASEC         0x1     /* Alarm: seconds */
   72 #define MC_MIN          0x2     /* Time of year: minutes (0-59) */
   73 #define MC_AMIN         0x3     /* Alarm: minutes */
   74 #define MC_HOUR         0x4     /* Time of year: hour (see above) */
   75 #define MC_AHOUR        0x5     /* Alarm: hour */
   76 #define MC_DOW          0x6     /* Time of year: day of week (1-7) */
   77 #define MC_DOM          0x7     /* Time of year: day of month (1-31) */
   78 #define MC_MONTH        0x8     /* Time of year: month (1-12) */
   79 #define MC_YEAR         0x9     /* Time of year: year in century (0-99) */
   80 
   81 #define MC_REGA         0xa     /* Control register A */
   82 
   83 #define  MC_REGA_RSMASK 0x0f    /* Interrupt rate select mask (see below) */
   84 #define  MC_REGA_DVMASK 0x70    /* Divisor select mask (see below) */
   85 #define  MC_REGA_DV0    0x10    /* Divisor 0 */
   86 #define  MC_REGA_DV1    0x20    /* Divisor 1 */
   87 #define  MC_REGA_DV2    0x40    /* Divisor 2 */
   88 #define  MC_REGA_UIP    0x80    /* Update in progress; read only. */
   89 
   90 #define MC_REGB         0xb     /* Control register B */
   91 
   92 #define  MC_REGB_DSE    0x01    /* Daylight Savings Enable */
   93 #define  MC_REGB_24HR   0x02    /* 24-hour mode (AM/PM mode when clear) */
   94 #define  MC_REGB_BINARY 0x04    /* Binary mode (BCD mode when clear) */
   95 #define  MC_REGB_SQWE   0x08    /* Square Wave Enable */
   96 #define  MC_REGB_UIE    0x10    /* Update End interrupt enable */
   97 #define  MC_REGB_AIE    0x20    /* Alarm interrupt enable */
   98 #define  MC_REGB_PIE    0x40    /* Periodic interrupt enable */
   99 #define  MC_REGB_SET    0x80    /* Allow time to be set; stops updates */
  100 
  101 #define MC_REGC         0xc     /* Control register C */
  102 
  103 /*       MC_REGC_UNUSED 0x0f    UNUSED */
  104 #define  MC_REGC_UF     0x10    /* Update End interrupt flag */
  105 #define  MC_REGC_AF     0x20    /* Alarm interrupt flag */
  106 #define  MC_REGC_PF     0x40    /* Periodic interrupt flag */
  107 #define  MC_REGC_IRQF   0x80    /* Interrupt request pending flag */
  108 
  109 #define MC_REGD         0xd     /* Control register D */
  110 
  111 /*       MC_REGD_UNUSED 0x7f    UNUSED */
  112 #define  MC_REGD_VRT    0x80    /* Valid RAM and Time bit */
  113 
  114 
  115 #define MC_NREGS        0xe     /* 14 registers; CMOS follows */
  116 #define MC_NTODREGS     0xa     /* 10 of those regs are for TOD and alarm */
  117 
  118 #define MC_NVRAM_START  0xe     /* start of NVRAM: offset 14 */
  119 #define MC_NVRAM_SIZE   50      /* 50 bytes of NVRAM */
  120 
  121 /*
  122  * Periodic Interrupt Rate Select constants (Control register A)
  123  */
  124 #define MC_RATE_NONE    0x0     /* No periodic interrupt */
  125 #define MC_RATE_1       0x1     /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */
  126 #define MC_RATE_2       0x2     /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */
  127 #define MC_RATE_8192_Hz 0x3     /* 122.070 us period */
  128 #define MC_RATE_4096_Hz 0x4     /* 244.141 us period */
  129 #define MC_RATE_2048_Hz 0x5     /* 488.281 us period */
  130 #define MC_RATE_1024_Hz 0x6     /* 976.562 us period */
  131 #define MC_RATE_512_Hz  0x7     /* 1.953125 ms period */
  132 #define MC_RATE_256_Hz  0x8     /* 3.90625 ms period */
  133 #define MC_RATE_128_Hz  0x9     /* 7.8125 ms period */
  134 #define MC_RATE_64_Hz   0xa     /* 15.625 ms period */
  135 #define MC_RATE_32_Hz   0xb     /* 31.25 ms period */
  136 #define MC_RATE_16_Hz   0xc     /* 62.5 ms period */
  137 #define MC_RATE_8_Hz    0xd     /* 125 ms period */
  138 #define MC_RATE_4_Hz    0xe     /* 250 ms period */
  139 #define MC_RATE_2_Hz    0xf     /* 500 ms period */
  140 
  141 /*
  142  * Time base (divisor select) constants (Control register A)
  143  */
  144 #define MC_BASE_4_MHz   0x00            /* 4 MHz crystal */
  145 #define MC_BASE_1_MHz   MC_REGA_DV0     /* 1 MHz crystal */
  146 #define MC_BASE_32_KHz  MC_REGA_DV1     /* 32 KHz crystal */
  147 #define MC_BASE_NONE    (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */
  148 #define MC_BASE_RESET   (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0)

Cache object: fb7a06e3518734e5bd7b211ebabd5497


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