mfireg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause
    3  *
    4  * Copyright (c) 2006 IronPort Systems
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 /*-
   29  * Copyright (c) 2007 LSI Corp.
   30  * Copyright (c) 2007 Rajesh Prabhakaran.
   31  * All rights reserved.
   32  *
   33  * Redistribution and use in source and binary forms, with or without
   34  * modification, are permitted provided that the following conditions
   35  * are met:
   36  * 1. Redistributions of source code must retain the above copyright
   37  *    notice, this list of conditions and the following disclaimer.
   38  * 2. Redistributions in binary form must reproduce the above copyright
   39  *    notice, this list of conditions and the following disclaimer in the
   40  *    documentation and/or other materials provided with the distribution.
   41  *
   42  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   43  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   44  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   45  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   46  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   47  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   48  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   49  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   50  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   51  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   52  * SUCH DAMAGE.
   53  */
   54 
   55 #ifndef _MFIREG_H
   56 #define _MFIREG_H
   57 
   58 #include <sys/cdefs.h>
   59 __FBSDID("$FreeBSD: releng/12.0/sys/dev/mfi/mfireg.h 326255 2017-11-27 14:52:40Z pfg $");
   60 
   61 /*
   62  * MegaRAID SAS MFI firmware definitions
   63  *
   64  * Calling this driver 'MegaRAID SAS' is a bit misleading.  It's a completely
   65  * new firmware interface from the old AMI MegaRAID one, and there is no
   66  * reason why this interface should be limited to just SAS.  In any case, LSI
   67  * seems to also call this interface 'MFI', so that will be used here.
   68  */
   69 #define MEGAMFI_FRAME_SIZE              64
   70 /*
   71  * Start with the register set.  All registers are 32 bits wide.
   72  * The usual Intel IOP style setup.
   73  */
   74 #define MFI_IMSG0       0x10    /* Inbound message 0 */
   75 #define MFI_IMSG1       0x14    /* Inbound message 1 */
   76 #define MFI_OMSG0       0x18    /* Outbound message 0 */
   77 #define MFI_OMSG1       0x1c    /* Outbound message 1 */
   78 #define MFI_IDB         0x20    /* Inbound doorbell */
   79 #define MFI_ISTS        0x24    /* Inbound interrupt status */
   80 #define MFI_IMSK        0x28    /* Inbound interrupt mask */
   81 #define MFI_ODB         0x2c    /* Outbound doorbell */
   82 #define MFI_OSTS        0x30    /* Outbound interrupt status */
   83 #define MFI_OMSK        0x34    /* Outbound interrupt mask */
   84 #define MFI_IQP         0x40    /* Inbound queue port */
   85 #define MFI_OQP         0x44    /* Outbound queue port */
   86 
   87 /*
   88 *  ThunderBolt specific Register
   89 */
   90 
   91 #define MFI_RFPI        0x48            /* reply_free_post_host_index */
   92 #define MFI_RPI         0x6c            /* reply_post_host_index */
   93 #define MFI_ILQP        0xc0            /* inbound_low_queue_port */
   94 #define MFI_IHQP        0xc4            /* inbound_high_queue_port */
   95 
   96 /*
   97  * 1078 specific related register
   98  */
   99 #define MFI_ODR0        0x9c            /* outbound doorbell register0 */
  100 #define MFI_ODCR0       0xa0            /* outbound doorbell clear register0  */
  101 #define MFI_OSP0        0xb0            /* outbound scratch pad0  */
  102 #define MFI_1078_EIM    0x80000004      /* 1078 enable intrrupt mask  */
  103 #define MFI_RMI         0x2             /* reply message interrupt  */
  104 #define MFI_1078_RM     0x80000000      /* reply 1078 message interrupt  */
  105 #define MFI_ODC         0x4             /* outbound doorbell change interrupt */
  106 
  107 /* OCR registers */
  108 #define MFI_WSR         0x004           /* write sequence register */
  109 #define MFI_HDR         0x008           /* host diagnostic register */
  110 #define MFI_RSR         0x3c3           /* Reset Status Register */
  111 
  112 /*
  113  * GEN2 specific changes
  114  */
  115 #define MFI_GEN2_EIM    0x00000005      /* GEN2 enable interrupt mask */
  116 #define MFI_GEN2_RM     0x00000001      /* reply GEN2 message interrupt */
  117 
  118 /*
  119  * skinny specific changes
  120  */
  121 #define MFI_SKINNY_IDB  0x00    /* Inbound doorbell is at 0x00 for skinny */
  122 #define MFI_IQPL        0x000000c0
  123 #define MFI_IQPH        0x000000c4
  124 #define MFI_SKINNY_RM   0x00000001      /* reply skinny message interrupt */
  125 
  126 /* Bits for MFI_OSTS */
  127 #define MFI_OSTS_INTR_VALID     0x00000002
  128 
  129 /* OCR specific flags */
  130 #define MFI_FIRMWARE_STATE_CHANGE       0x00000002
  131 #define MFI_STATE_CHANGE_INTERRUPT      0x00000004  /* MFI state change interrrupt */
  132 
  133 /*
  134  * Firmware state values.  Found in OMSG0 during initialization.
  135  */
  136 #define MFI_FWSTATE_MASK                0xf0000000
  137 #define MFI_FWSTATE_UNDEFINED           0x00000000
  138 #define MFI_FWSTATE_BB_INIT             0x10000000
  139 #define MFI_FWSTATE_FW_INIT             0x40000000
  140 #define MFI_FWSTATE_WAIT_HANDSHAKE      0x60000000
  141 #define MFI_FWSTATE_FW_INIT_2           0x70000000
  142 #define MFI_FWSTATE_DEVICE_SCAN         0x80000000
  143 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING        0x90000000
  144 #define MFI_FWSTATE_FLUSH_CACHE         0xa0000000
  145 #define MFI_FWSTATE_READY               0xb0000000
  146 #define MFI_FWSTATE_OPERATIONAL         0xc0000000
  147 #define MFI_FWSTATE_FAULT               0xf0000000
  148 #define MFI_FWSTATE_MAXSGL_MASK         0x00ff0000
  149 #define MFI_FWSTATE_MAXCMD_MASK         0x0000ffff
  150 #define MFI_FWSTATE_HOSTMEMREQD_MASK    0x08000000
  151 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING        0x90000000
  152 #define MFI_RESET_REQUIRED              0x00000001
  153 
  154 /* ThunderBolt Support */
  155 #define MFI_FWSTATE_TB_MASK             0xf0000000
  156 #define MFI_FWSTATE_TB_RESET            0x00000000
  157 #define MFI_FWSTATE_TB_READY            0x10000000
  158 #define MFI_FWSTATE_TB_OPERATIONAL      0x20000000
  159 #define MFI_FWSTATE_TB_FAULT            0x40000000
  160 
  161 /*
  162  * Control bits to drive the card to ready state.  These go into the IDB
  163  * register.
  164  */
  165 #define MFI_FWINIT_ABORT        0x00000000 /* Abort all pending commands */
  166 #define MFI_FWINIT_READY        0x00000002 /* Move from operational to ready */
  167 #define MFI_FWINIT_MFIMODE      0x00000004 /* unknown */
  168 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
  169 #define MFI_FWINIT_HOTPLUG      0x00000010
  170 
  171 /* ADP reset flags */
  172 #define MFI_STOP_ADP            0x00000020
  173 #define MFI_ADP_RESET           0x00000040
  174 #define DIAG_WRITE_ENABLE       0x00000080
  175 #define DIAG_RESET_ADAPTER      0x00000004
  176 
  177 /* MFI Commands */
  178 typedef enum {
  179         MFI_CMD_INIT =          0x00,
  180         MFI_CMD_LD_READ,
  181         MFI_CMD_LD_WRITE,
  182         MFI_CMD_LD_SCSI_IO,
  183         MFI_CMD_PD_SCSI_IO,
  184         MFI_CMD_DCMD,
  185         MFI_CMD_ABORT,
  186         MFI_CMD_SMP,
  187         MFI_CMD_STP
  188 } mfi_cmd_t;
  189 
  190 /* Direct commands */
  191 typedef enum {
  192         MFI_DCMD_CTRL_GETINFO =         0x01010000,
  193         MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100,
  194         MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
  195         MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
  196         MFI_DCMD_CTRL_FLUSHCACHE =      0x01101000,
  197         MFI_DCMD_CTRL_GET_PROPS =       0x01020100,
  198         MFI_DCMD_CTRL_SET_PROPS =       0x01020200,
  199         MFI_DCMD_CTRL_SHUTDOWN =        0x01050000,
  200         MFI_DCMD_CTRL_EVENT_GETINFO =   0x01040100,
  201         MFI_DCMD_CTRL_EVENT_GET =       0x01040300,
  202         MFI_DCMD_CTRL_EVENT_WAIT =      0x01040500,
  203         MFI_DCMD_PR_GET_STATUS =        0x01070100,
  204         MFI_DCMD_PR_GET_PROPERTIES =    0x01070200,
  205         MFI_DCMD_PR_SET_PROPERTIES =    0x01070300,
  206         MFI_DCMD_PR_START =             0x01070400,
  207         MFI_DCMD_PR_STOP =              0x01070500,
  208         MFI_DCMD_TIME_SECS_GET =        0x01080201,
  209         MFI_DCMD_FLASH_FW_OPEN =        0x010f0100,
  210         MFI_DCMD_FLASH_FW_DOWNLOAD =    0x010f0200,
  211         MFI_DCMD_FLASH_FW_FLASH =       0x010f0300,
  212         MFI_DCMD_FLASH_FW_CLOSE =       0x010f0400,
  213         MFI_DCMD_PD_GET_LIST =          0x02010000,
  214         MFI_DCMD_PD_LIST_QUERY =        0x02010100,
  215         MFI_DCMD_PD_GET_INFO =          0x02020000,
  216         MFI_DCMD_PD_STATE_SET =         0x02030100,
  217         MFI_DCMD_PD_REBUILD_START =     0x02040100,
  218         MFI_DCMD_PD_REBUILD_ABORT =     0x02040200,
  219         MFI_DCMD_PD_CLEAR_START =       0x02050100,
  220         MFI_DCMD_PD_CLEAR_ABORT =       0x02050200,
  221         MFI_DCMD_PD_GET_PROGRESS =      0x02060000,
  222         MFI_DCMD_PD_LOCATE_START =      0x02070100,
  223         MFI_DCMD_PD_LOCATE_STOP =       0x02070200,
  224         MFI_DCMD_LD_MAP_GET_INFO =      0x0300e101,
  225         MFI_DCMD_LD_SYNC =              0x0300e102,
  226         MFI_DCMD_LD_GET_LIST =          0x03010000,
  227         MFI_DCMD_LD_GET_INFO =          0x03020000,
  228         MFI_DCMD_LD_GET_PROP =          0x03030000,
  229         MFI_DCMD_LD_SET_PROP =          0x03040000,
  230         MFI_DCMD_LD_INIT_START =        0x03060100,
  231         MFI_DCMD_LD_DELETE =            0x03090000,
  232         MFI_DCMD_CFG_READ =             0x04010000,
  233         MFI_DCMD_CFG_ADD =              0x04020000,
  234         MFI_DCMD_CFG_CLEAR =            0x04030000,
  235         MFI_DCMD_CFG_MAKE_SPARE =       0x04040000,
  236         MFI_DCMD_CFG_REMOVE_SPARE =     0x04050000,
  237         MFI_DCMD_CFG_FOREIGN_SCAN =     0x04060100,
  238         MFI_DCMD_CFG_FOREIGN_DISPLAY =  0x04060200,
  239         MFI_DCMD_CFG_FOREIGN_PREVIEW =  0x04060300,
  240         MFI_DCMD_CFG_FOREIGN_IMPORT =   0x04060400,
  241         MFI_DCMD_CFG_FOREIGN_CLEAR =    0x04060500,
  242         MFI_DCMD_BBU_GET_STATUS =       0x05010000,
  243         MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000,
  244         MFI_DCMD_BBU_GET_DESIGN_INFO =  0x05030000,
  245         MFI_DCMD_BBU_START_LEARN =      0x05040000,
  246         MFI_DCMD_BBU_GET_PROP =         0x05050100,
  247         MFI_DCMD_BBU_SET_PROP =         0x05050200,
  248         MFI_DCMD_CLUSTER =              0x08000000,
  249         MFI_DCMD_CLUSTER_RESET_ALL =    0x08010100,
  250         MFI_DCMD_CLUSTER_RESET_LD =     0x08010200
  251 } mfi_dcmd_t;
  252 
  253 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
  254 #define MFI_FLUSHCACHE_CTRL     0x01
  255 #define MFI_FLUSHCACHE_DISK     0x02
  256 
  257 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
  258 #define MFI_SHUTDOWN_SPINDOWN   0x01
  259 
  260 /*
  261  * MFI Frame flags
  262  */
  263 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
  264 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
  265 #define MFI_FRAME_SGL32                         0x0000
  266 #define MFI_FRAME_SGL64                         0x0002
  267 #define MFI_FRAME_SENSE32                       0x0000
  268 #define MFI_FRAME_SENSE64                       0x0004
  269 #define MFI_FRAME_DIR_NONE                      0x0000
  270 #define MFI_FRAME_DIR_WRITE                     0x0008
  271 #define MFI_FRAME_DIR_READ                      0x0010
  272 #define MFI_FRAME_DIR_BOTH                      0x0018
  273 #define MFI_FRAME_IEEE_SGL                      0x0020
  274 #define MFI_FRAME_FMT "\2" \
  275     "\1NOPOST" \
  276     "\2SGL64" \
  277     "\3SENSE64" \
  278     "\4WRITE" \
  279     "\5READ" \
  280     "\6IEEESGL"
  281 
  282 /* ThunderBolt Specific */
  283 
  284 /*
  285  * Pre-TB command size and TB command size.
  286  * We will be checking it at the load time for the time being
  287  */
  288 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */
  289 
  290 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT  256
  291 /*
  292  * We are defining only 128 byte message to reduce memory move over head
  293  * and also it will reduce the SRB extension size by 128byte compared with
  294  * 256 message size
  295  */
  296 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE        256
  297 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS        1024
  298 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT     1024
  299 #define MEGASAS_THUNDERBOLT_REPLY_SIZE          8
  300 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT     1
  301 #define MEGASAS_MAX_SZ_CHAIN_FRAME              1024
  302 
  303 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST       0xF0
  304 #define MPI2_FUNCTION_LD_IO_REQUEST             0xF1
  305 
  306 #define MR_INTERNAL_MFI_FRAMES_SMID             1
  307 #define MR_CTRL_EVENT_WAIT_SMID                 2
  308 #define MR_INTERNAL_DRIVER_RESET_SMID           3
  309 
  310 
  311 /* MFI Status codes */
  312 typedef enum {
  313         MFI_STAT_OK =                   0x00,
  314         MFI_STAT_INVALID_CMD,
  315         MFI_STAT_INVALID_DCMD,
  316         MFI_STAT_INVALID_PARAMETER,
  317         MFI_STAT_INVALID_SEQUENCE_NUMBER,
  318         MFI_STAT_ABORT_NOT_POSSIBLE,
  319         MFI_STAT_APP_HOST_CODE_NOT_FOUND,
  320         MFI_STAT_APP_IN_USE,
  321         MFI_STAT_APP_NOT_INITIALIZED,
  322         MFI_STAT_ARRAY_INDEX_INVALID,
  323         MFI_STAT_ARRAY_ROW_NOT_EMPTY,
  324         MFI_STAT_CONFIG_RESOURCE_CONFLICT,
  325         MFI_STAT_DEVICE_NOT_FOUND,
  326         MFI_STAT_DRIVE_TOO_SMALL,
  327         MFI_STAT_FLASH_ALLOC_FAIL,
  328         MFI_STAT_FLASH_BUSY,
  329         MFI_STAT_FLASH_ERROR =          0x10,
  330         MFI_STAT_FLASH_IMAGE_BAD,
  331         MFI_STAT_FLASH_IMAGE_INCOMPLETE,
  332         MFI_STAT_FLASH_NOT_OPEN,
  333         MFI_STAT_FLASH_NOT_STARTED,
  334         MFI_STAT_FLUSH_FAILED,
  335         MFI_STAT_HOST_CODE_NOT_FOUNT,
  336         MFI_STAT_LD_CC_IN_PROGRESS,
  337         MFI_STAT_LD_INIT_IN_PROGRESS,
  338         MFI_STAT_LD_LBA_OUT_OF_RANGE,
  339         MFI_STAT_LD_MAX_CONFIGURED,
  340         MFI_STAT_LD_NOT_OPTIMAL,
  341         MFI_STAT_LD_RBLD_IN_PROGRESS,
  342         MFI_STAT_LD_RECON_IN_PROGRESS,
  343         MFI_STAT_LD_WRONG_RAID_LEVEL,
  344         MFI_STAT_MAX_SPARES_EXCEEDED,
  345         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
  346         MFI_STAT_MFC_HW_ERROR,
  347         MFI_STAT_NO_HW_PRESENT,
  348         MFI_STAT_NOT_FOUND,
  349         MFI_STAT_NOT_IN_ENCL,
  350         MFI_STAT_PD_CLEAR_IN_PROGRESS,
  351         MFI_STAT_PD_TYPE_WRONG,
  352         MFI_STAT_PR_DISABLED,
  353         MFI_STAT_ROW_INDEX_INVALID,
  354         MFI_STAT_SAS_CONFIG_INVALID_ACTION,
  355         MFI_STAT_SAS_CONFIG_INVALID_DATA,
  356         MFI_STAT_SAS_CONFIG_INVALID_PAGE,
  357         MFI_STAT_SAS_CONFIG_INVALID_TYPE,
  358         MFI_STAT_SCSI_DONE_WITH_ERROR,
  359         MFI_STAT_SCSI_IO_FAILED,
  360         MFI_STAT_SCSI_RESERVATION_CONFLICT,
  361         MFI_STAT_SHUTDOWN_FAILED =      0x30,
  362         MFI_STAT_TIME_NOT_SET,
  363         MFI_STAT_WRONG_STATE,
  364         MFI_STAT_LD_OFFLINE,
  365         MFI_STAT_PEER_NOTIFICATION_REJECTED,
  366         MFI_STAT_PEER_NOTIFICATION_FAILED,
  367         MFI_STAT_RESERVATION_IN_PROGRESS,
  368         MFI_STAT_I2C_ERRORS_DETECTED,
  369         MFI_STAT_PCI_ERRORS_DETECTED,
  370         MFI_STAT_DIAG_FAILED,
  371         MFI_STAT_BOOT_MSG_PENDING,
  372         MFI_STAT_FOREIGN_CONFIG_INCOMPLETE,
  373         MFI_STAT_INVALID_STATUS =       0xFF
  374 } mfi_status_t;
  375 
  376 typedef enum {
  377         MFI_EVT_CLASS_DEBUG =           -2,
  378         MFI_EVT_CLASS_PROGRESS =        -1,
  379         MFI_EVT_CLASS_INFO =            0,
  380         MFI_EVT_CLASS_WARNING =         1,
  381         MFI_EVT_CLASS_CRITICAL =        2,
  382         MFI_EVT_CLASS_FATAL =           3,
  383         MFI_EVT_CLASS_DEAD =            4
  384 } mfi_evt_class_t;
  385 
  386 typedef enum {
  387         MFI_EVT_LOCALE_LD =             0x0001,
  388         MFI_EVT_LOCALE_PD =             0x0002,
  389         MFI_EVT_LOCALE_ENCL =           0x0004,
  390         MFI_EVT_LOCALE_BBU =            0x0008,
  391         MFI_EVT_LOCALE_SAS =            0x0010,
  392         MFI_EVT_LOCALE_CTRL =           0x0020,
  393         MFI_EVT_LOCALE_CONFIG =         0x0040,
  394         MFI_EVT_LOCALE_CLUSTER =        0x0080,
  395         MFI_EVT_LOCALE_ALL =            0xffff
  396 } mfi_evt_locale_t;
  397 
  398 typedef enum {
  399         MR_EVT_ARGS_NONE =              0x00,
  400         MR_EVT_ARGS_CDB_SENSE,
  401         MR_EVT_ARGS_LD,
  402         MR_EVT_ARGS_LD_COUNT,
  403         MR_EVT_ARGS_LD_LBA,
  404         MR_EVT_ARGS_LD_OWNER,
  405         MR_EVT_ARGS_LD_LBA_PD_LBA,
  406         MR_EVT_ARGS_LD_PROG,
  407         MR_EVT_ARGS_LD_STATE,
  408         MR_EVT_ARGS_LD_STRIP,
  409         MR_EVT_ARGS_PD,
  410         MR_EVT_ARGS_PD_ERR,
  411         MR_EVT_ARGS_PD_LBA,
  412         MR_EVT_ARGS_PD_LBA_LD,
  413         MR_EVT_ARGS_PD_PROG,
  414         MR_EVT_ARGS_PD_STATE,
  415         MR_EVT_ARGS_PCI,
  416         MR_EVT_ARGS_RATE,
  417         MR_EVT_ARGS_STR,
  418         MR_EVT_ARGS_TIME,
  419         MR_EVT_ARGS_ECC
  420 } mfi_evt_args;
  421 
  422 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED     0x0152
  423 #define MR_EVT_PD_REMOVED                       0x0070
  424 #define MR_EVT_PD_INSERTED                      0x005b
  425 #define MR_EVT_LD_CHANGE                        0x0051
  426 
  427 typedef enum {
  428         MR_LD_CACHE_WRITE_BACK =        0x01,
  429         MR_LD_CACHE_WRITE_ADAPTIVE =    0x02,
  430         MR_LD_CACHE_READ_AHEAD =        0x04,
  431         MR_LD_CACHE_READ_ADAPTIVE =     0x08,
  432         MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
  433         MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
  434         MR_LD_CACHE_ALLOW_READ_CACHE =  0x40
  435 } mfi_ld_cache;
  436 #define MR_LD_CACHE_MASK        0x7f
  437 
  438 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE              0
  439 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS            MR_LD_CACHE_READ_AHEAD
  440 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE          \
  441         (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE)
  442 #define MR_LD_CACHE_POLICY_WRITE_THROUGH                0
  443 #define MR_LD_CACHE_POLICY_WRITE_BACK                   MR_LD_CACHE_WRITE_BACK
  444 #define MR_LD_CACHE_POLICY_IO_CACHED                    \
  445         (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE)
  446 #define MR_LD_CACHE_POLICY_IO_DIRECT                    0
  447 
  448 typedef enum {
  449         MR_PD_CACHE_UNCHANGED  =        0,
  450         MR_PD_CACHE_ENABLE =            1,
  451         MR_PD_CACHE_DISABLE =           2
  452 } mfi_pd_cache;
  453 
  454 typedef enum {
  455         MR_PD_QUERY_TYPE_ALL =          0,
  456         MR_PD_QUERY_TYPE_STATE =        1,
  457         MR_PD_QUERY_TYPE_POWER_STATE =  2,
  458         MR_PD_QUERY_TYPE_MEDIA_TYPE =   3,
  459         MR_PD_QUERY_TYPE_SPEED =        4,
  460         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */
  461 } mfi_pd_query_type;
  462 
  463 /*
  464  * Other propertities and definitions
  465  */
  466 #define MFI_MAX_PD_CHANNELS     2
  467 #define MFI_MAX_LD_CHANNELS     2
  468 #define MFI_MAX_CHANNELS        (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
  469 #define MFI_MAX_CHANNEL_DEVS    128
  470 #define MFI_DEFAULT_ID          -1
  471 #define MFI_MAX_LUN             8
  472 #define MFI_MAX_LD              64
  473 #define MFI_MAX_PD              256
  474 
  475 #define MFI_FRAME_SIZE          64
  476 #define MFI_MBOX_SIZE           12
  477 
  478 /* Firmware flashing can take 50+ seconds */
  479 #define MFI_POLL_TIMEOUT_SECS   60
  480 
  481 /* Allow for speedier math calculations */
  482 #define MFI_SECTOR_LEN          512
  483 
  484 /* Scatter Gather elements */
  485 struct mfi_sg32 {
  486         uint32_t        addr;
  487         uint32_t        len;
  488 } __packed;
  489 
  490 struct mfi_sg64 {
  491         uint64_t        addr;
  492         uint32_t        len;
  493 } __packed;
  494 
  495 struct mfi_sg_skinny {
  496         uint64_t        addr;
  497         uint32_t        len;
  498         uint32_t        flag;
  499 } __packed;
  500 
  501 union mfi_sgl {
  502         struct mfi_sg32         sg32[1];
  503         struct mfi_sg64         sg64[1];
  504         struct mfi_sg_skinny    sg_skinny[1];
  505 } __packed;
  506 
  507 /* Message frames.  All messages have a common header */
  508 struct mfi_frame_header {
  509         uint8_t         cmd;
  510         uint8_t         sense_len;
  511         uint8_t         cmd_status;
  512         uint8_t         scsi_status;
  513         uint8_t         target_id;
  514         uint8_t         lun_id;
  515         uint8_t         cdb_len;
  516         uint8_t         sg_count;
  517         uint32_t        context;
  518         /*
  519          * pad0 is MSI Specific. Not used by Driver. Zero the value before
  520          * sending the command to f/w.
  521          */
  522         uint32_t        pad0;
  523         uint16_t        flags;
  524 #define MFI_FRAME_DATAOUT       0x08
  525 #define MFI_FRAME_DATAIN        0x10
  526         uint16_t        timeout;
  527         uint32_t        data_len;
  528 } __packed;
  529 
  530 struct mfi_init_frame {
  531         struct mfi_frame_header header;
  532         uint32_t        qinfo_new_addr_lo;
  533         uint32_t        qinfo_new_addr_hi;
  534         uint32_t        qinfo_old_addr_lo;
  535         uint32_t        qinfo_old_addr_hi;
  536         // Start LSIP200113393
  537         uint32_t        driver_ver_lo;      /*28h */
  538         uint32_t        driver_ver_hi;      /*2Ch */
  539 
  540         uint32_t        reserved[4];
  541         // End LSIP200113393
  542 } __packed;
  543 
  544 /*
  545  * Define MFI Address Context union.
  546  */
  547 #ifdef MFI_ADDRESS_IS_uint64_t
  548     typedef uint64_t     MFI_ADDRESS;
  549 #else
  550     typedef union _MFI_ADDRESS {
  551         struct {
  552             uint32_t     addressLow;
  553             uint32_t     addressHigh;
  554         } u;
  555         uint64_t     address;
  556     } MFI_ADDRESS, *PMFI_ADDRESS;
  557 #endif
  558 
  559 #define MFI_IO_FRAME_SIZE 40
  560 struct mfi_io_frame {
  561         struct mfi_frame_header header;
  562         uint32_t        sense_addr_lo;
  563         uint32_t        sense_addr_hi;
  564         uint32_t        lba_lo;
  565         uint32_t        lba_hi;
  566         union mfi_sgl   sgl;
  567 } __packed;
  568 
  569 #define MFI_PASS_FRAME_SIZE 48
  570 struct mfi_pass_frame {
  571         struct mfi_frame_header header;
  572         uint32_t        sense_addr_lo;
  573         uint32_t        sense_addr_hi;
  574         uint8_t         cdb[16];
  575         union mfi_sgl   sgl;
  576 } __packed;
  577 
  578 #define MFI_DCMD_FRAME_SIZE 40
  579 struct mfi_dcmd_frame {
  580         struct mfi_frame_header header;
  581         uint32_t        opcode;
  582         uint8_t         mbox[MFI_MBOX_SIZE];
  583         union mfi_sgl   sgl;
  584 } __packed;
  585 
  586 struct mfi_abort_frame {
  587         struct mfi_frame_header header;
  588         uint32_t        abort_context;
  589         /* pad is changed to reserved.*/
  590         uint32_t        reserved0;
  591         uint32_t        abort_mfi_addr_lo;
  592         uint32_t        abort_mfi_addr_hi;
  593         uint32_t        reserved1[6];
  594 } __packed;
  595 
  596 struct mfi_smp_frame {
  597         struct mfi_frame_header header;
  598         uint64_t        sas_addr;
  599         union {
  600                 struct mfi_sg32 sg32[2];
  601                 struct mfi_sg64 sg64[2];
  602         } sgl;
  603 } __packed;
  604 
  605 struct mfi_stp_frame {
  606         struct mfi_frame_header header;
  607         uint16_t        fis[10];
  608         uint32_t        stp_flags;
  609         union {
  610                 struct mfi_sg32 sg32[2];
  611                 struct mfi_sg64 sg64[2];
  612         } sgl;
  613 } __packed;
  614 
  615 union mfi_frame {
  616         struct mfi_frame_header header;
  617         struct mfi_init_frame   init;
  618         /* ThunderBolt Initialization */
  619         struct mfi_io_frame     io;
  620         struct mfi_pass_frame   pass;
  621         struct mfi_dcmd_frame   dcmd;
  622         struct mfi_abort_frame  abort;
  623         struct mfi_smp_frame    smp;
  624         struct mfi_stp_frame    stp;
  625         uint8_t                 bytes[MFI_FRAME_SIZE];
  626 };
  627 
  628 #define MFI_SENSE_LEN 128
  629 struct mfi_sense {
  630         uint8_t         data[MFI_SENSE_LEN];
  631 };
  632 
  633 /* The queue init structure that is passed with the init message */
  634 struct mfi_init_qinfo {
  635         uint32_t        flags;
  636         uint32_t        rq_entries;
  637         uint32_t        rq_addr_lo;
  638         uint32_t        rq_addr_hi;
  639         uint32_t        pi_addr_lo;
  640         uint32_t        pi_addr_hi;
  641         uint32_t        ci_addr_lo;
  642         uint32_t        ci_addr_hi;
  643 } __packed;
  644 
  645 /* SAS (?) controller properties, part of mfi_ctrl_info */
  646 struct mfi_ctrl_props {
  647         uint16_t        seq_num;
  648         uint16_t        pred_fail_poll_interval;
  649         uint16_t        intr_throttle_cnt;
  650         uint16_t        intr_throttle_timeout;
  651         uint8_t         rebuild_rate;
  652         uint8_t         patrol_read_rate;
  653         uint8_t         bgi_rate;
  654         uint8_t         cc_rate;
  655         uint8_t         recon_rate;
  656         uint8_t         cache_flush_interval;
  657         uint8_t         spinup_drv_cnt;
  658         uint8_t         spinup_delay;
  659         uint8_t         cluster_enable;
  660         uint8_t         coercion_mode;
  661         uint8_t         alarm_enable;
  662         uint8_t         disable_auto_rebuild;
  663         uint8_t         disable_battery_warn;
  664         uint8_t         ecc_bucket_size;
  665         uint16_t        ecc_bucket_leak_rate;
  666         uint8_t         restore_hotspare_on_insertion;
  667         uint8_t         expose_encl_devices;
  668         uint8_t         maintainPdFailHistory;
  669         uint8_t         disallowHostRequestReordering;
  670         /* set TRUE to abort CC on detecting an inconsistency */
  671         uint8_t         abortCCOnError;
  672         /* load balance mode (MR_LOAD_BALANCE_MODE) */
  673         uint8_t         loadBalanceMode;
  674         /*
  675          * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using
  676          *     h/w mechansim like GPIO pins
  677          * 1 - disable auto detect SGPIO,
  678          * 2 - disable i2c SEP auto detect
  679          * 3 - disable both auto detect
  680          */
  681         uint8_t         disableAutoDetectBackplane;
  682         /*
  683          * % of source LD to be reserved for a VDs snapshot in snapshot
  684          * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on
  685          */
  686         uint8_t         snapVDSpace;
  687 
  688         /*
  689          * Add properties that can be controlled by a bit in the following
  690          * structure.
  691          */
  692         struct {
  693                 /* set TRUE to disable copyBack (0=copback enabled) */
  694                 uint32_t        copyBackDisabled                :1;
  695                 uint32_t        SMARTerEnabled                  :1;
  696                 uint32_t        prCorrectUnconfiguredAreas      :1;
  697                 uint32_t        useFdeOnly                      :1;
  698                 uint32_t        disableNCQ                      :1;
  699                 uint32_t        SSDSMARTerEnabled               :1;
  700                 uint32_t        SSDPatrolReadEnabled            :1;
  701                 uint32_t        enableSpinDownUnconfigured      :1;
  702                 uint32_t        autoEnhancedImport              :1;
  703                 uint32_t        enableSecretKeyControl          :1;
  704                 uint32_t        disableOnlineCtrlReset          :1;
  705                 uint32_t        allowBootWithPinnedCache        :1;
  706                 uint32_t        disableSpinDownHS               :1;
  707                 uint32_t        enableJBOD                      :1;
  708                 uint32_t        reserved                        :18;
  709         } OnOffProperties;
  710         /*
  711          * % of source LD to be reserved for auto snapshot in snapshot
  712          * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on.
  713          */
  714         uint8_t         autoSnapVDSpace;
  715         /*
  716          * Snapshot writeable VIEWs capacity as a % of source LD capacity:
  717          * 0=READ only, 1=5%, 2=10%, 3=15% and so on.
  718          */
  719         uint8_t         viewSpace;
  720         /* # of idle minutes before device is spun down (0=use FW defaults) */
  721         uint16_t        spinDownTime;
  722         uint8_t         reserved[24];
  723 } __packed;
  724 
  725 /* PCI information about the card. */
  726 struct mfi_info_pci {
  727         uint16_t        vendor;
  728         uint16_t        device;
  729         uint16_t        subvendor;
  730         uint16_t        subdevice;
  731         uint8_t         reserved[24];
  732 } __packed;
  733 
  734 /* Host (front end) interface information */
  735 struct mfi_info_host {
  736         uint8_t         type;
  737 #define MFI_INFO_HOST_PCIX      0x01
  738 #define MFI_INFO_HOST_PCIE      0x02
  739 #define MFI_INFO_HOST_ISCSI     0x04
  740 #define MFI_INFO_HOST_SAS3G     0x08
  741         uint8_t         reserved[6];
  742         uint8_t         port_count;
  743         uint64_t        port_addr[8];
  744 } __packed;
  745 
  746 /* Device (back end) interface information */
  747 struct mfi_info_device {
  748         uint8_t         type;
  749 #define MFI_INFO_DEV_SPI        0x01
  750 #define MFI_INFO_DEV_SAS3G      0x02
  751 #define MFI_INFO_DEV_SATA1      0x04
  752 #define MFI_INFO_DEV_SATA3G     0x08
  753         uint8_t         reserved[6];
  754         uint8_t         port_count;
  755         uint64_t        port_addr[8];
  756 } __packed;
  757 
  758 /* Firmware component information */
  759 struct mfi_info_component {
  760         char             name[8];
  761         char             version[32];
  762         char             build_date[16];
  763         char             build_time[16];
  764 } __packed;
  765 
  766 /* Controller default settings */
  767 struct mfi_defaults {
  768         uint64_t        sas_addr;
  769         uint8_t         phy_polarity;
  770         uint8_t         background_rate;
  771         uint8_t         stripe_size;
  772         uint8_t         flush_time;
  773         uint8_t         write_back;
  774         uint8_t         read_ahead;
  775         uint8_t         cache_when_bbu_bad;
  776         uint8_t         cached_io;
  777         uint8_t         smart_mode;
  778         uint8_t         alarm_disable;
  779         uint8_t         coercion;
  780         uint8_t         zrc_config;
  781         uint8_t         dirty_led_shows_drive_activity;
  782         uint8_t         bios_continue_on_error;
  783         uint8_t         spindown_mode;
  784         uint8_t         allowed_device_types;
  785         uint8_t         allow_mix_in_enclosure;
  786         uint8_t         allow_mix_in_ld;
  787         uint8_t         allow_sata_in_cluster;
  788         uint8_t         max_chained_enclosures;
  789         uint8_t         disable_ctrl_r;
  790         uint8_t         enabel_web_bios;
  791         uint8_t         phy_polarity_split;
  792         uint8_t         direct_pd_mapping;
  793         uint8_t         bios_enumerate_lds;
  794         uint8_t         restored_hot_spare_on_insertion;
  795         uint8_t         expose_enclosure_devices;
  796         uint8_t         maintain_pd_fail_history;
  797         uint8_t         resv[28];
  798 } __packed;
  799 
  800 /* Controller default settings */
  801 struct mfi_bios_data {
  802         uint16_t        boot_target_id;
  803         uint8_t         do_not_int_13;
  804         uint8_t         continue_on_error;
  805         uint8_t         verbose;
  806         uint8_t         geometry;
  807         uint8_t         expose_all_drives;
  808         uint8_t         reserved[56];
  809         uint8_t         check_sum;
  810 } __packed;
  811 
  812 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
  813 struct mfi_ctrl_info {
  814         struct mfi_info_pci     pci;
  815         struct mfi_info_host    host;
  816         struct mfi_info_device  device;
  817 
  818         /* Firmware components that are present and active. */
  819         uint32_t                image_check_word;
  820         uint32_t                image_component_count;
  821         struct mfi_info_component image_component[8];
  822 
  823         /* Firmware components that have been flashed but are inactive */
  824         uint32_t                pending_image_component_count;
  825         struct mfi_info_component pending_image_component[8];
  826 
  827         uint8_t                 max_arms;
  828         uint8_t                 max_spans;
  829         uint8_t                 max_arrays;
  830         uint8_t                 max_lds;
  831         char                    product_name[80];
  832         char                    serial_number[32];
  833         uint32_t                hw_present;
  834 #define MFI_INFO_HW_BBU         0x01
  835 #define MFI_INFO_HW_ALARM       0x02
  836 #define MFI_INFO_HW_NVRAM       0x04
  837 #define MFI_INFO_HW_UART        0x08
  838         uint32_t                current_fw_time;
  839         uint16_t                max_cmds;
  840         uint16_t                max_sg_elements;
  841         uint32_t                max_request_size;
  842         uint16_t                lds_present;
  843         uint16_t                lds_degraded;
  844         uint16_t                lds_offline;
  845         uint16_t                pd_present;
  846         uint16_t                pd_disks_present;
  847         uint16_t                pd_disks_pred_failure;
  848         uint16_t                pd_disks_failed;
  849         uint16_t                nvram_size;
  850         uint16_t                memory_size;
  851         uint16_t                flash_size;
  852         uint16_t                ram_correctable_errors;
  853         uint16_t                ram_uncorrectable_errors;
  854         uint8_t                 cluster_allowed;
  855         uint8_t                 cluster_active;
  856         uint16_t                max_strips_per_io;
  857 
  858         uint32_t                raid_levels;
  859 #define MFI_INFO_RAID_0         0x01
  860 #define MFI_INFO_RAID_1         0x02
  861 #define MFI_INFO_RAID_5         0x04
  862 #define MFI_INFO_RAID_1E        0x08
  863 #define MFI_INFO_RAID_6         0x10
  864 
  865         uint32_t                adapter_ops;
  866 #define MFI_INFO_AOPS_RBLD_RATE         0x0001
  867 #define MFI_INFO_AOPS_CC_RATE           0x0002
  868 #define MFI_INFO_AOPS_BGI_RATE          0x0004
  869 #define MFI_INFO_AOPS_RECON_RATE        0x0008
  870 #define MFI_INFO_AOPS_PATROL_RATE       0x0010
  871 #define MFI_INFO_AOPS_ALARM_CONTROL     0x0020
  872 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
  873 #define MFI_INFO_AOPS_BBU               0x0080
  874 #define MFI_INFO_AOPS_SPANNING_ALLOWED  0x0100
  875 #define MFI_INFO_AOPS_DEDICATED_SPARES  0x0200
  876 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
  877 #define MFI_INFO_AOPS_FOREIGN_IMPORT    0x0800
  878 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC   0x1000
  879 #define MFI_INFO_AOPS_MIXED_ARRAY       0x2000
  880 #define MFI_INFO_AOPS_GLOBAL_SPARES     0x4000
  881 
  882         uint32_t                ld_ops;
  883 #define MFI_INFO_LDOPS_READ_POLICY      0x01
  884 #define MFI_INFO_LDOPS_WRITE_POLICY     0x02
  885 #define MFI_INFO_LDOPS_IO_POLICY        0x04
  886 #define MFI_INFO_LDOPS_ACCESS_POLICY    0x08
  887 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
  888 
  889         struct {
  890                 uint8_t         min;
  891                 uint8_t         max;
  892                 uint8_t         reserved[2];
  893         } __packed stripe_sz_ops;
  894 
  895         uint32_t                pd_ops;
  896 #define MFI_INFO_PDOPS_FORCE_ONLINE     0x01
  897 #define MFI_INFO_PDOPS_FORCE_OFFLINE    0x02
  898 #define MFI_INFO_PDOPS_FORCE_REBUILD    0x04
  899 
  900         uint32_t                pd_mix_support;
  901 #define MFI_INFO_PDMIX_SAS              0x01
  902 #define MFI_INFO_PDMIX_SATA             0x02
  903 #define MFI_INFO_PDMIX_ENCL             0x04
  904 #define MFI_INFO_PDMIX_LD               0x08
  905 #define MFI_INFO_PDMIX_SATA_CLUSTER     0x10
  906 
  907         uint8_t                 ecc_bucket_count;
  908         uint8_t                 reserved2[11];
  909         struct mfi_ctrl_props   properties;
  910         char                    package_version[0x60];
  911         uint8_t                 pad[0x800 - 0x6a0];
  912 } __packed;
  913 
  914 /* keep track of an event. */
  915 union mfi_evt {
  916         struct {
  917                 uint16_t        locale;
  918                 uint8_t         reserved;
  919                 int8_t          evt_class;
  920         } members;
  921         uint32_t                word;
  922 } __packed;
  923 
  924 /* event log state. */
  925 struct mfi_evt_log_state {
  926         uint32_t                newest_seq_num;
  927         uint32_t                oldest_seq_num;
  928         uint32_t                clear_seq_num;
  929         uint32_t                shutdown_seq_num;
  930         uint32_t                boot_seq_num;
  931 } __packed;
  932 
  933 struct mfi_progress {
  934         uint16_t                progress;
  935         uint16_t                elapsed_seconds;
  936 } __packed;
  937 
  938 struct mfi_evt_ld {
  939         uint16_t                target_id;
  940         uint8_t                 ld_index;
  941         uint8_t                 reserved;
  942 } __packed;
  943 
  944 struct mfi_evt_pd {
  945         uint16_t                device_id;
  946         uint8_t                 enclosure_index;
  947         uint8_t                 slot_number;
  948 } __packed;
  949 
  950 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
  951 struct mfi_evt_detail {
  952         uint32_t                seq;
  953         uint32_t                time;
  954         uint32_t                code;
  955         union mfi_evt           evt_class;
  956         uint8_t                 arg_type;
  957         uint8_t                 reserved1[15];
  958 
  959         union {
  960                 struct {
  961                         struct mfi_evt_pd       pd;
  962                         uint8_t                 cdb_len;
  963                         uint8_t                 sense_len;
  964                         uint8_t                 reserved[2];
  965                         uint8_t                 cdb[16];
  966                         uint8_t                 sense[64];
  967                 } cdb_sense;
  968 
  969                 struct mfi_evt_ld               ld;
  970 
  971                 struct {
  972                         struct mfi_evt_ld       ld;
  973                         uint64_t                count;
  974                 } ld_count;
  975 
  976                 struct {
  977                         uint64_t                lba;
  978                         struct mfi_evt_ld       ld;
  979                 } ld_lba;
  980 
  981                 struct {
  982                         struct mfi_evt_ld       ld;
  983                         uint32_t                pre_owner;
  984                         uint32_t                new_owner;
  985                 } ld_owner;
  986 
  987                 struct {
  988                         uint64_t                ld_lba;
  989                         uint64_t                pd_lba;
  990                         struct mfi_evt_ld       ld;
  991                         struct mfi_evt_pd       pd;
  992                 } ld_lba_pd_lba;
  993 
  994                 struct {
  995                         struct mfi_evt_ld       ld;
  996                         struct mfi_progress     prog;
  997                 } ld_prog;
  998 
  999                 struct {
 1000                         struct mfi_evt_ld       ld;
 1001                         uint32_t                prev_state;
 1002                         uint32_t                new_state;
 1003                 } ld_state;
 1004 
 1005                 struct {
 1006                         uint64_t                strip;
 1007                         struct mfi_evt_ld       ld;
 1008                 } ld_strip;
 1009 
 1010                 struct mfi_evt_pd               pd;
 1011 
 1012                 struct {
 1013                         struct mfi_evt_pd       pd;
 1014                         uint32_t                err;
 1015                 } pd_err;
 1016 
 1017                 struct {
 1018                         uint64_t                lba;
 1019                         struct mfi_evt_pd       pd;
 1020                 } pd_lba;
 1021 
 1022                 struct {
 1023                         uint64_t                lba;
 1024                         struct mfi_evt_pd       pd;
 1025                         struct mfi_evt_ld       ld;
 1026                 } pd_lba_ld;
 1027 
 1028                 struct {
 1029                         struct mfi_evt_pd       pd;
 1030                         struct mfi_progress     prog;
 1031                 } pd_prog;
 1032 
 1033                 struct {
 1034                         struct mfi_evt_pd       ld;
 1035                         uint32_t                prev_state;
 1036                         uint32_t                new_state;
 1037                 } pd_state;
 1038 
 1039                 struct {
 1040                         uint16_t                venderId;
 1041                         uint16_t                deviceId;
 1042                         uint16_t                subVenderId;
 1043                         uint16_t                subDeviceId;
 1044                 } pci;
 1045 
 1046                 uint32_t                        rate;
 1047 
 1048                 char                            str[96];
 1049 
 1050                 struct {
 1051                         uint32_t                rtc;
 1052                         uint16_t                elapsedSeconds;
 1053                 } time;
 1054 
 1055                 struct {
 1056                         uint32_t                ecar;
 1057                         uint32_t                elog;
 1058                         char                    str[64];
 1059                 } ecc;
 1060 
 1061                 uint8_t         b[96];
 1062                 uint16_t        s[48];
 1063                 uint32_t        w[24];
 1064                 uint64_t        d[12];
 1065         } args;
 1066 
 1067         char description[128];
 1068 } __packed;
 1069 
 1070 struct mfi_evt_list {
 1071         uint32_t                count;
 1072         uint32_t                reserved;
 1073         struct mfi_evt_detail   event[1];
 1074 } __packed;
 1075 
 1076 union mfi_pd_ref {
 1077         struct {
 1078                 uint16_t        device_id;
 1079                 uint16_t        seq_num;
 1080         } v;
 1081         uint32_t        ref;
 1082 } __packed;
 1083 
 1084 union mfi_pd_ddf_type {
 1085         struct {
 1086                 union {
 1087                         struct {
 1088                                 uint16_t        forced_pd_guid  : 1;
 1089                                 uint16_t        in_vd           : 1;
 1090                                 uint16_t        is_global_spare : 1;
 1091                                 uint16_t        is_spare        : 1;
 1092                                 uint16_t        is_foreign      : 1;
 1093                                 uint16_t        reserved        : 7;
 1094                                 uint16_t        intf            : 4;
 1095                         } pd_type;
 1096                         uint16_t        type;
 1097                 } v;
 1098                 uint16_t                reserved;
 1099         } ddf;
 1100         struct {
 1101                 uint32_t                reserved;
 1102         } non_disk;
 1103         uint32_t                        type;
 1104 } __packed;
 1105 
 1106 struct mfi_pd_progress {
 1107         uint32_t                        active;
 1108 #define MFI_PD_PROGRESS_REBUILD (1<<0)
 1109 #define MFI_PD_PROGRESS_PATROL  (1<<1)
 1110 #define MFI_PD_PROGRESS_CLEAR   (1<<2)
 1111         struct mfi_progress             rbld;
 1112         struct mfi_progress             patrol;
 1113         struct mfi_progress             clear;
 1114         struct mfi_progress             reserved[4];
 1115 } __packed;
 1116 
 1117 struct mfi_pd_info {
 1118         union mfi_pd_ref                ref;
 1119         uint8_t                         inquiry_data[96];
 1120         uint8_t                         vpd_page83[64];
 1121         uint8_t                         not_supported;
 1122         uint8_t                         scsi_dev_type;
 1123         uint8_t                         connected_port_bitmap;
 1124         uint8_t                         device_speed;
 1125         uint32_t                        media_err_count;
 1126         uint32_t                        other_err_count;
 1127         uint32_t                        pred_fail_count;
 1128         uint32_t                        last_pred_fail_event_seq_num;
 1129         uint16_t                        fw_state;       /* MFI_PD_STATE_* */
 1130         uint8_t                         disabled_for_removal;
 1131         uint8_t                         link_speed;
 1132         union mfi_pd_ddf_type           state;
 1133         struct {
 1134                 uint8_t                 count;
 1135                 uint8_t                 is_path_broken;
 1136                 uint8_t                 reserved[6];
 1137                 uint64_t                sas_addr[4];
 1138         } path_info;
 1139         uint64_t                        raw_size;
 1140         uint64_t                        non_coerced_size;
 1141         uint64_t                        coerced_size;
 1142         uint16_t                        encl_device_id;
 1143         uint8_t                         encl_index;
 1144         uint8_t                         slot_number;
 1145         struct mfi_pd_progress          prog_info;
 1146         uint8_t                         bad_block_table_full;
 1147         uint8_t                         unusable_in_current_config;
 1148         uint8_t                         vpd_page83_ext[64];
 1149         uint8_t                         reserved[512-358];
 1150 } __packed;
 1151 
 1152 struct mfi_pd_address {
 1153         uint16_t                device_id;
 1154         uint16_t                encl_device_id;
 1155         uint8_t                 encl_index;
 1156         uint8_t                 slot_number;
 1157         uint8_t                 scsi_dev_type;  /* 0 = disk */
 1158         uint8_t                 connect_port_bitmap;
 1159         uint64_t                sas_addr[2];
 1160 } __packed;
 1161 
 1162 #define MAX_SYS_PDS 240
 1163 struct mfi_pd_list {
 1164         uint32_t                size;
 1165         uint32_t                count;
 1166         struct mfi_pd_address   addr[MAX_SYS_PDS];
 1167 } __packed;
 1168 
 1169 enum mfi_pd_state {
 1170         MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
 1171         MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
 1172         MFI_PD_STATE_HOT_SPARE = 0x02,
 1173         MFI_PD_STATE_OFFLINE = 0x10,
 1174         MFI_PD_STATE_FAILED = 0x11,
 1175         MFI_PD_STATE_REBUILD = 0x14,
 1176         MFI_PD_STATE_ONLINE = 0x18,
 1177         MFI_PD_STATE_COPYBACK = 0x20,
 1178         MFI_PD_STATE_SYSTEM = 0x40
 1179 };
 1180 
 1181 /*
 1182  * "SYSTEM" disk appears to be "JBOD" support from the RAID controller.
 1183  * Adding a #define to denote this.
 1184  */
 1185 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM
 1186 
 1187 union mfi_ld_ref {
 1188         struct {
 1189                 uint8_t         target_id;
 1190                 uint8_t         reserved;
 1191                 uint16_t        seq;
 1192         } v;
 1193         uint32_t                ref;
 1194 } __packed;
 1195 
 1196 struct mfi_ld_list {
 1197         uint32_t                ld_count;
 1198         uint32_t                reserved1;
 1199         struct {
 1200                 union mfi_ld_ref        ld;
 1201                 uint8_t         state;
 1202                 uint8_t         reserved2[3];
 1203                 uint64_t        size;
 1204         } ld_list[MFI_MAX_LD];
 1205 } __packed;
 1206 
 1207 enum mfi_ld_access {
 1208         MFI_LD_ACCESS_RW =      0,
 1209         MFI_LD_ACCSSS_RO =      2,
 1210         MFI_LD_ACCESS_BLOCKED = 3,
 1211 };
 1212 #define MFI_LD_ACCESS_MASK      3
 1213 
 1214 enum mfi_ld_state {
 1215         MFI_LD_STATE_OFFLINE =                  0,
 1216         MFI_LD_STATE_PARTIALLY_DEGRADED =       1,
 1217         MFI_LD_STATE_DEGRADED =                 2,
 1218         MFI_LD_STATE_OPTIMAL =                  3
 1219 };
 1220 
 1221 struct mfi_ld_props {
 1222         union mfi_ld_ref        ld;
 1223         char                    name[16];
 1224         uint8_t                 default_cache_policy;
 1225         uint8_t                 access_policy;
 1226         uint8_t                 disk_cache_policy;
 1227         uint8_t                 current_cache_policy;
 1228         uint8_t                 no_bgi;
 1229         uint8_t                 reserved[7];
 1230 } __packed;
 1231 
 1232 struct mfi_ld_params {
 1233         uint8_t                 primary_raid_level;
 1234         uint8_t                 raid_level_qualifier;
 1235         uint8_t                 secondary_raid_level;
 1236         uint8_t                 stripe_size;
 1237         uint8_t                 num_drives;
 1238         uint8_t                 span_depth;
 1239         uint8_t                 state;
 1240         uint8_t                 init_state;
 1241 #define MFI_LD_PARAMS_INIT_NO           0
 1242 #define MFI_LD_PARAMS_INIT_QUICK        1
 1243 #define MFI_LD_PARAMS_INIT_FULL         2
 1244         uint8_t                 is_consistent;
 1245         uint8_t                 reserved1[6];
 1246         uint8_t                 isSSCD;
 1247         uint8_t                 reserved2[16];
 1248 } __packed;
 1249 
 1250 struct mfi_ld_progress {
 1251         uint32_t                active;
 1252 #define MFI_LD_PROGRESS_CC      (1<<0)
 1253 #define MFI_LD_PROGRESS_BGI     (1<<1)
 1254 #define MFI_LD_PROGRESS_FGI     (1<<2)
 1255 #define MFI_LD_PROGRESS_RECON   (1<<3)
 1256         struct mfi_progress     cc;
 1257         struct mfi_progress     bgi;
 1258         struct mfi_progress     fgi;
 1259         struct mfi_progress     recon;
 1260         struct mfi_progress     reserved[4];
 1261 } __packed;
 1262 
 1263 struct mfi_span {
 1264         uint64_t                start_block;
 1265         uint64_t                num_blocks;
 1266         uint16_t                array_ref;
 1267         uint8_t                 reserved[6];
 1268 } __packed;
 1269 
 1270 #define MFI_MAX_SPAN_DEPTH      8
 1271 struct mfi_ld_config {
 1272         struct mfi_ld_props     properties;
 1273         struct mfi_ld_params    params;
 1274         struct mfi_span         span[MFI_MAX_SPAN_DEPTH];
 1275 } __packed;
 1276 
 1277 struct mfi_ld_info {
 1278         struct mfi_ld_config    ld_config;
 1279         uint64_t                size;
 1280         struct mfi_ld_progress  progress;
 1281         uint16_t                cluster_owner;
 1282         uint8_t                 reconstruct_active;
 1283         uint8_t                 reserved1[1];
 1284         uint8_t                 vpd_page83[64];
 1285         uint8_t                 reserved2[16];
 1286 } __packed;
 1287 
 1288 #define MFI_MAX_ARRAYS 16
 1289 struct mfi_spare {
 1290         union mfi_pd_ref        ref;
 1291         uint8_t                 spare_type;
 1292 #define MFI_SPARE_DEDICATED     (1 << 0)
 1293 #define MFI_SPARE_REVERTIBLE    (1 << 1)
 1294 #define MFI_SPARE_ENCL_AFFINITY (1 << 2)
 1295         uint8_t                 reserved[2];
 1296         uint8_t                 array_count;
 1297         uint16_t                array_ref[MFI_MAX_ARRAYS];
 1298 } __packed;
 1299 
 1300 #define MFI_MAX_ROW_SIZE 32
 1301 struct mfi_array {
 1302         uint64_t                        size;
 1303         uint8_t                         num_drives;
 1304         uint8_t                         reserved;
 1305         uint16_t                        array_ref;
 1306         uint8_t                         pad[20];
 1307         struct {
 1308                 union mfi_pd_ref        ref;    /* 0xffff == missing drive */
 1309                 uint16_t                fw_state;       /* MFI_PD_STATE_* */
 1310                 struct {
 1311                         uint8_t         pd;
 1312                         uint8_t         slot;
 1313                 } encl;
 1314         } pd[MFI_MAX_ROW_SIZE];
 1315 } __packed;
 1316 
 1317 struct mfi_config_data {
 1318         uint32_t                size;
 1319         uint16_t                array_count;
 1320         uint16_t                array_size;
 1321         uint16_t                log_drv_count;
 1322         uint16_t                log_drv_size;
 1323         uint16_t                spares_count;
 1324         uint16_t                spares_size;
 1325         uint8_t                 reserved[16];
 1326         struct mfi_array        array[0];
 1327         struct mfi_ld_config    ld[0];
 1328         struct mfi_spare        spare[0];
 1329 } __packed;
 1330 
 1331 struct mfi_bbu_capacity_info {
 1332         uint16_t                relative_charge;
 1333         uint16_t                absolute_charge;
 1334         uint16_t                remaining_capacity;
 1335         uint16_t                full_charge_capacity;
 1336         uint16_t                run_time_to_empty;
 1337         uint16_t                average_time_to_empty;
 1338         uint16_t                average_time_to_full;
 1339         uint16_t                cycle_count;
 1340         uint16_t                max_error;
 1341         uint16_t                remaining_capacity_alarm;
 1342         uint16_t                remaining_time_alarm;
 1343         uint8_t                 reserved[26];
 1344 } __packed;
 1345 
 1346 struct mfi_bbu_design_info {
 1347         uint32_t                mfg_date;
 1348         uint16_t                design_capacity;
 1349         uint16_t                design_voltage;
 1350         uint16_t                spec_info;
 1351         uint16_t                serial_number;
 1352         uint16_t                pack_stat_config;
 1353         uint8_t                 mfg_name[12];
 1354         uint8_t                 device_name[8];
 1355         uint8_t                 device_chemistry[8];
 1356         uint8_t                 mfg_data[8];
 1357         uint8_t                 reserved[17];
 1358 } __packed;
 1359 
 1360 struct mfi_ibbu_state {
 1361         uint16_t                gas_guage_status;
 1362         uint16_t                relative_charge;
 1363         uint16_t                charger_system_state;
 1364         uint16_t                charger_system_ctrl;
 1365         uint16_t                charging_current;
 1366         uint16_t                absolute_charge;
 1367         uint16_t                max_error;
 1368         uint8_t                 reserved[18];
 1369 } __packed;
 1370 
 1371 struct mfi_bbu_state {
 1372         uint16_t                gas_guage_status;
 1373         uint16_t                relative_charge;
 1374         uint16_t                charger_status;
 1375         uint16_t                remaining_capacity;
 1376         uint16_t                full_charge_capacity;
 1377         uint8_t                 is_SOH_good;
 1378         uint8_t                 reserved[21];
 1379 } __packed;
 1380 
 1381 struct mfi_bbu_properties {
 1382         uint32_t                auto_learn_period;
 1383         uint32_t                next_learn_time;
 1384         uint8_t                 learn_delay_interval;
 1385         uint8_t                 auto_learn_mode;
 1386         uint8_t                 bbu_mode;
 1387         uint8_t                 reserved[21];
 1388 } __packed;
 1389 
 1390 union mfi_bbu_status_detail {
 1391         struct mfi_ibbu_state   ibbu;
 1392         struct mfi_bbu_state    bbu;
 1393 };
 1394 
 1395 struct mfi_bbu_status {
 1396         uint8_t                 battery_type;
 1397 #define MFI_BBU_TYPE_NONE       0
 1398 #define MFI_BBU_TYPE_IBBU       1
 1399 #define MFI_BBU_TYPE_BBU        2
 1400         uint8_t                 reserved;
 1401         uint16_t                voltage;
 1402         int16_t                 current;
 1403         uint16_t                temperature;
 1404         uint32_t                fw_status;
 1405 #define MFI_BBU_STATE_PACK_MISSING      (1 << 0)
 1406 #define MFI_BBU_STATE_VOLTAGE_LOW       (1 << 1)
 1407 #define MFI_BBU_STATE_TEMPERATURE_HIGH  (1 << 2)
 1408 #define MFI_BBU_STATE_CHARGE_ACTIVE     (1 << 3)
 1409 #define MFI_BBU_STATE_DISCHARGE_ACTIVE  (1 << 4)
 1410 #define MFI_BBU_STATE_LEARN_CYC_REQ     (1 << 5)
 1411 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE  (1 << 6)
 1412 #define MFI_BBU_STATE_LEARN_CYC_FAIL    (1 << 7)
 1413 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8)
 1414 #define MFI_BBU_STATE_I2C_ERR_DETECT    (1 << 9)
 1415         uint8_t                 pad[20];
 1416         union mfi_bbu_status_detail detail;
 1417 } __packed;
 1418 
 1419 enum mfi_pr_state {
 1420         MFI_PR_STATE_STOPPED = 0,
 1421         MFI_PR_STATE_READY = 1,
 1422         MFI_PR_STATE_ACTIVE = 2,
 1423         MFI_PR_STATE_ABORTED = 0xff
 1424 };
 1425 
 1426 struct mfi_pr_status {
 1427         uint32_t                num_iteration;
 1428         uint8_t                 state;
 1429         uint8_t                 num_pd_done;
 1430         uint8_t                 reserved[10];
 1431 };
 1432 
 1433 enum mfi_pr_opmode {
 1434         MFI_PR_OPMODE_AUTO = 0,
 1435         MFI_PR_OPMODE_MANUAL = 1,
 1436         MFI_PR_OPMODE_DISABLED = 2
 1437 };
 1438 
 1439 struct mfi_pr_properties {
 1440         uint8_t                 op_mode;
 1441         uint8_t                 max_pd;
 1442         uint8_t                 reserved;
 1443         uint8_t                 exclude_ld_count;
 1444         uint16_t                excluded_ld[MFI_MAX_LD];
 1445         uint8_t                 cur_pd_map[MFI_MAX_PD / 8];
 1446         uint8_t                 last_pd_map[MFI_MAX_PD / 8];
 1447         uint32_t                next_exec;
 1448         uint32_t                exec_freq;
 1449         uint32_t                clear_freq;
 1450 };
 1451 
 1452 /* ThunderBolt support */
 1453 
 1454 /*
 1455  * Raid Context structure which describes MegaRAID specific IO Paramenters
 1456  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 1457  */
 1458 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE {
 1459         uint16_t        resvd0;         /* 0x00 - 0x01 */
 1460         uint16_t        timeoutValue;   /* 0x02 - 0x03 */
 1461         uint8_t         regLockFlags;
 1462         uint8_t         armId;
 1463         uint16_t        TargetID;       /* 0x06 - 0x07 */
 1464 
 1465         uint64_t        RegLockLBA;     /* 0x08 - 0x0F */
 1466 
 1467         uint32_t        RegLockLength;  /* 0x10 - 0x13 */
 1468 
 1469         uint16_t        SMID;           /* 0x14 - 0x15 nextLMId */
 1470         uint8_t         exStatus;       /* 0x16 */
 1471         uint8_t         Status;         /* 0x17 status */
 1472 
 1473         uint8_t         RAIDFlags;      /* 0x18 */
 1474         uint8_t         numSGE;         /* 0x19 numSge */
 1475         uint16_t        configSeqNum;   /* 0x1A - 0x1B */
 1476         uint8_t         spanArm;        /* 0x1C */
 1477         uint8_t         resvd2[3];      /* 0x1D - 0x1F */
 1478 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE;
 1479 
 1480 /*****************************************************************************
 1481 *
 1482 *        Message Functions
 1483 *
 1484 *****************************************************************************/
 1485 
 1486 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST            (0x00) /* SCSI IO */
 1487 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 1488 #define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 1489 #define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 1490 #define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 1491 #define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 1492 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 1493 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 1494 #define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 1495 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 1496 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 1497 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 1498 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 1499 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 1500 #define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 1501 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 1502 #define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 1503 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 1504 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 1505 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 1506 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 1507 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 1508 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 1509 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 1510 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 1511 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator */
 1512 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F) /* Host Based Discovery Action */
 1513 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30) /* Power Management Control */
 1514 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0) /* beginning of product-specific range */
 1515 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF) /* end of product-specific range */
 1516 
 1517 /* Doorbell functions */
 1518 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 1519 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 1520 
 1521 /*****************************************************************************
 1522 *
 1523 *        MPI Version Definitions
 1524 *
 1525 *****************************************************************************/
 1526 
 1527 #define MPI2_VERSION_MAJOR                  (0x02)
 1528 #define MPI2_VERSION_MINOR                  (0x00)
 1529 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 1530 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 1531 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 1532 #define MPI2_VERSION_MINOR_SHIFT            (0)
 1533 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
 1534                                       MPI2_VERSION_MINOR)
 1535 
 1536 #define MPI2_VERSION_02_00                  (0x0200)
 1537 
 1538 /* versioning for this MPI header set */
 1539 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 1540 #define MPI2_HEADER_VERSION_DEV             (0x00)
 1541 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 1542 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 1543 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 1544 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 1545 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) |          \
 1546                                         MPI2_HEADER_VERSION_DEV)
 1547 
 1548 
 1549 /* IOCInit Request message */
 1550 struct MPI2_IOC_INIT_REQUEST {
 1551         uint8_t         WhoInit;                        /* 0x00 */
 1552         uint8_t         Reserved1;                      /* 0x01 */
 1553         uint8_t         ChainOffset;                    /* 0x02 */
 1554         uint8_t         Function;                       /* 0x03 */
 1555         uint16_t        Reserved2;                      /* 0x04 */
 1556         uint8_t         Reserved3;                      /* 0x06 */
 1557         uint8_t         MsgFlags;                       /* 0x07 */
 1558         uint8_t         VP_ID;                          /* 0x08 */
 1559         uint8_t         VF_ID;                          /* 0x09 */
 1560         uint16_t        Reserved4;                      /* 0x0A */
 1561         uint16_t        MsgVersion;                     /* 0x0C */
 1562         uint16_t        HeaderVersion;                  /* 0x0E */
 1563         uint32_t        Reserved5;                      /* 0x10 */
 1564         uint16_t        Reserved6;                      /* 0x14 */
 1565         uint8_t         Reserved7;                      /* 0x16 */
 1566         uint8_t         HostMSIxVectors;                /* 0x17 */
 1567         uint16_t        Reserved8;                      /* 0x18 */
 1568         uint16_t        SystemRequestFrameSize;         /* 0x1A */
 1569         uint16_t        ReplyDescriptorPostQueueDepth;  /* 0x1C */
 1570         uint16_t        ReplyFreeQueueDepth;            /* 0x1E */
 1571         uint32_t        SenseBufferAddressHigh;         /* 0x20 */
 1572         uint32_t        SystemReplyAddressHigh;         /* 0x24 */
 1573         uint64_t        SystemRequestFrameBaseAddress;  /* 0x28 */
 1574         uint64_t        ReplyDescriptorPostQueueAddress;/* 0x30 */
 1575         uint64_t        ReplyFreeQueueAddress;          /* 0x38 */
 1576         uint64_t        TimeStamp;                      /* 0x40 */
 1577 };
 1578 
 1579 /* WhoInit values */
 1580 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 1581 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 1582 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 1583 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 1584 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 1585 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 1586 
 1587 struct MPI2_SGE_CHAIN_UNION {
 1588         uint16_t        Length;
 1589         uint8_t         NextChainOffset;
 1590         uint8_t         Flags;
 1591         union {
 1592                 uint32_t        Address32;
 1593                 uint64_t        Address64;
 1594         } u;
 1595 };
 1596 
 1597 struct MPI2_IEEE_SGE_SIMPLE32 {
 1598         uint32_t        Address;
 1599         uint32_t        FlagsLength;
 1600 };
 1601 
 1602 struct MPI2_IEEE_SGE_SIMPLE64 {
 1603         uint64_t        Address;
 1604         uint32_t        Length;
 1605         uint16_t        Reserved1;
 1606         uint8_t         Reserved2;
 1607         uint8_t         Flags;
 1608 };
 1609 
 1610 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
 1611         struct MPI2_IEEE_SGE_SIMPLE32   Simple32;
 1612         struct MPI2_IEEE_SGE_SIMPLE64   Simple64;
 1613 } MPI2_IEEE_SGE_SIMPLE_UNION;
 1614 
 1615 typedef struct _MPI2_SGE_SIMPLE_UNION {
 1616         uint32_t        FlagsLength;
 1617         union {
 1618                 uint32_t        Address32;
 1619                 uint64_t        Address64;
 1620         } u;
 1621 } MPI2_SGE_SIMPLE_UNION;
 1622 
 1623 /****************************************************************************
 1624 *  IEEE SGE field definitions and masks
 1625 ****************************************************************************/
 1626 
 1627 /* Flags field bit definitions */
 1628 
 1629 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
 1630 
 1631 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
 1632 
 1633 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
 1634 
 1635 /* Element Type */
 1636 
 1637 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
 1638 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
 1639 
 1640 /* Data Location Address Space */
 1641 
 1642 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
 1643 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
 1644 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
 1645 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
 1646 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 1647 
 1648 /* Address Size */
 1649 
 1650 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 1651 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 1652 
 1653 /*******************/
 1654 /* SCSI IO Control bits */
 1655 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK      (0xFC000000)
 1656 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT     (26)
 1657 
 1658 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK  (0x03000000)
 1659 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER      (0x00000000)
 1660 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 1661 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 1662 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL       (0x03000000)
 1663 
 1664 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK        (0x00007800)
 1665 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT       (11)
 1666 
 1667 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK  (0x00000700)
 1668 #define MPI2_SCSIIO_CONTROL_SIMPLEQ             (0x00000000)
 1669 #define MPI2_SCSIIO_CONTROL_HEADOFQ             (0x00000100)
 1670 #define MPI2_SCSIIO_CONTROL_ORDEREDQ            (0x00000200)
 1671 #define MPI2_SCSIIO_CONTROL_ACAQ                (0x00000400)
 1672 
 1673 #define MPI2_SCSIIO_CONTROL_TLR_MASK            (0x000000C0)
 1674 #define MPI2_SCSIIO_CONTROL_NO_TLR              (0x00000000)
 1675 #define MPI2_SCSIIO_CONTROL_TLR_ON              (0x00000040)
 1676 #define MPI2_SCSIIO_CONTROL_TLR_OFF             (0x00000080)
 1677 
 1678 /*******************/
 1679 
 1680 typedef struct {
 1681         uint8_t         CDB[20];                    /* 0x00 */
 1682         uint32_t        PrimaryReferenceTag;        /* 0x14 */
 1683         uint16_t        PrimaryApplicationTag;      /* 0x18 */
 1684         uint16_t        PrimaryApplicationTagMask;  /* 0x1A */
 1685         uint32_t        TransferLength;             /* 0x1C */
 1686 } MPI2_SCSI_IO_CDB_EEDP32;
 1687 
 1688 
 1689 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
 1690         struct MPI2_IEEE_SGE_SIMPLE32   Chain32;
 1691         struct MPI2_IEEE_SGE_SIMPLE64   Chain64;
 1692 } MPI2_IEEE_SGE_CHAIN_UNION;
 1693 
 1694 typedef union _MPI2_SIMPLE_SGE_UNION {
 1695         MPI2_SGE_SIMPLE_UNION           MpiSimple;
 1696         MPI2_IEEE_SGE_SIMPLE_UNION      IeeeSimple;
 1697 } MPI2_SIMPLE_SGE_UNION;
 1698 
 1699 typedef union _MPI2_SGE_IO_UNION {
 1700         MPI2_SGE_SIMPLE_UNION           MpiSimple;
 1701         struct MPI2_SGE_CHAIN_UNION     MpiChain;
 1702         MPI2_IEEE_SGE_SIMPLE_UNION      IeeeSimple;
 1703         MPI2_IEEE_SGE_CHAIN_UNION       IeeeChain;
 1704 } MPI2_SGE_IO_UNION;
 1705 
 1706 typedef union {
 1707         uint8_t                 CDB32[32];
 1708         MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 1709         MPI2_SGE_SIMPLE_UNION   SGE;
 1710 } MPI2_SCSI_IO_CDB_UNION;
 1711 
 1712 
 1713 /* MPI 2.5 SGLs */
 1714 
 1715 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST        (0x40)
 1716 
 1717 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
 1718         uint64_t        Address;
 1719         uint32_t        Length;
 1720         uint16_t        Reserved1;
 1721         uint8_t         NextChainOffset;
 1722         uint8_t         Flags;
 1723 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t;
 1724 
 1725 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */
 1726 
 1727 
 1728 /********/
 1729 
 1730 /*
 1731  * RAID SCSI IO Request Message
 1732  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 1733  */
 1734 struct mfi_mpi2_request_raid_scsi_io {
 1735         uint16_t                DevHandle;                      /* 0x00 */
 1736         uint8_t                 ChainOffset;                    /* 0x02 */
 1737         uint8_t                 Function;                       /* 0x03 */
 1738         uint16_t                Reserved1;                      /* 0x04 */
 1739         uint8_t                 Reserved2;                      /* 0x06 */
 1740         uint8_t                 MsgFlags;                       /* 0x07 */
 1741         uint8_t                 VP_ID;                          /* 0x08 */
 1742         uint8_t                 VF_ID;                          /* 0x09 */
 1743         uint16_t                Reserved3;                      /* 0x0A */
 1744         uint32_t                SenseBufferLowAddress;          /* 0x0C */
 1745         uint16_t                SGLFlags;                       /* 0x10 */
 1746         uint8_t                 SenseBufferLength;              /* 0x12 */
 1747         uint8_t                 Reserved4;                      /* 0x13 */
 1748         uint8_t                 SGLOffset0;                     /* 0x14 */
 1749         uint8_t                 SGLOffset1;                     /* 0x15 */
 1750         uint8_t                 SGLOffset2;                     /* 0x16 */
 1751         uint8_t                 SGLOffset3;                     /* 0x17 */
 1752         uint32_t                SkipCount;                      /* 0x18 */
 1753         uint32_t                DataLength;                     /* 0x1C */
 1754         uint32_t                BidirectionalDataLength;        /* 0x20 */
 1755         uint16_t                IoFlags;                        /* 0x24 */
 1756         uint16_t                EEDPFlags;                      /* 0x26 */
 1757         uint32_t                EEDPBlockSize;                  /* 0x28 */
 1758         uint32_t                SecondaryReferenceTag;          /* 0x2C */
 1759         uint16_t                SecondaryApplicationTag;        /* 0x30 */
 1760         uint16_t                ApplicationTagTranslationMask;  /* 0x32 */
 1761         uint8_t                 LUN[8];                         /* 0x34 */
 1762         uint32_t                Control;                        /* 0x3C */
 1763         MPI2_SCSI_IO_CDB_UNION  CDB;                            /* 0x40 */
 1764         MPI2_SCSI_IO_VENDOR_UNIQUE      RaidContext;              /* 0x60 */
 1765         MPI2_SGE_IO_UNION       SGL;                            /* 0x80 */
 1766 } __packed;
 1767 
 1768 /*
 1769  * MPT RAID MFA IO Descriptor.
 1770  */
 1771 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR {
 1772         uint32_t        RequestFlags : 8;
 1773         uint32_t        MessageAddress1 : 24; /* bits 31:8*/
 1774         uint32_t        MessageAddress2;      /* bits 61:32 */
 1775 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR;
 1776 
 1777 struct mfi_mpi2_request_header {
 1778         uint8_t         RequestFlags;       /* 0x00 */
 1779         uint8_t         MSIxIndex;          /* 0x01 */
 1780         uint16_t        SMID;               /* 0x02 */
 1781         uint16_t        LMID;               /* 0x04 */
 1782 };
 1783 
 1784 /* defines for the RequestFlags field */
 1785 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 1786 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 1787 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 1788 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 1789 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 1790 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 1791 
 1792 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 1793 
 1794 struct mfi_mpi2_request_high_priority {
 1795         struct mfi_mpi2_request_header  header;
 1796         uint16_t                        reserved;
 1797 };
 1798 
 1799 struct mfi_mpi2_request_scsi_io {
 1800         struct mfi_mpi2_request_header  header;
 1801         uint16_t                        scsi_io_dev_handle;
 1802 };
 1803 
 1804 struct mfi_mpi2_request_scsi_target {
 1805         struct mfi_mpi2_request_header  header;
 1806         uint16_t                        scsi_target_io_index;
 1807 };
 1808 
 1809 /* Request Descriptors */
 1810 union mfi_mpi2_request_descriptor {
 1811         struct mfi_mpi2_request_header          header;
 1812         struct mfi_mpi2_request_high_priority   high_priority;
 1813         struct mfi_mpi2_request_scsi_io         scsi_io;
 1814         struct mfi_mpi2_request_scsi_target     scsi_target;
 1815         uint64_t                                words;
 1816 };
 1817 
 1818 
 1819 struct mfi_mpi2_reply_header {
 1820         uint8_t         ReplyFlags;                 /* 0x00 */
 1821         uint8_t         MSIxIndex;                  /* 0x01 */
 1822         uint16_t        SMID;                       /* 0x02 */
 1823 };
 1824 
 1825 /* defines for the ReplyFlags field */
 1826 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 1827 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 1828 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 1829 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 1830 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 1831 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 1832 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 1833 
 1834 /* values for marking a reply descriptor as unused */
 1835 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 1836 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 1837 
 1838 struct mfi_mpi2_reply_default {
 1839         struct mfi_mpi2_reply_header    header;
 1840         uint32_t                        DescriptorTypeDependent2;
 1841 };
 1842 
 1843 struct mfi_mpi2_reply_address {
 1844         struct mfi_mpi2_reply_header    header;
 1845         uint32_t                        ReplyFrameAddress;
 1846 };
 1847 
 1848 struct mfi_mpi2_reply_scsi_io {
 1849         struct mfi_mpi2_reply_header    header;
 1850         uint16_t                        TaskTag;                /* 0x04 */
 1851         uint16_t                        Reserved1;              /* 0x06 */
 1852 };
 1853 
 1854 struct mfi_mpi2_reply_target_assist {
 1855         struct mfi_mpi2_reply_header    header;
 1856         uint8_t                         SequenceNumber;         /* 0x04 */
 1857         uint8_t                         Reserved1;              /* 0x04 */
 1858         uint16_t                        IoIndex;                /* 0x06 */
 1859 };
 1860 
 1861 struct mfi_mpi2_reply_target_cmd_buffer {
 1862         struct mfi_mpi2_reply_header    header;
 1863         uint8_t                         SequenceNumber;         /* 0x04 */
 1864         uint8_t                         Flags;                  /* 0x04 */
 1865         uint16_t                        InitiatorDevHandle;     /* 0x06 */
 1866         uint16_t                        IoIndex;                /* 0x06 */
 1867 };
 1868 
 1869 struct mfi_mpi2_reply_raid_accel {
 1870         struct mfi_mpi2_reply_header    header;
 1871         uint8_t                         SequenceNumber;         /* 0x04 */
 1872         uint32_t                        Reserved;               /* 0x04 */
 1873 };
 1874 
 1875 /* union of Reply Descriptors */
 1876 union mfi_mpi2_reply_descriptor {
 1877         struct mfi_mpi2_reply_header            header;
 1878         struct mfi_mpi2_reply_scsi_io           scsi_io;
 1879         struct mfi_mpi2_reply_target_assist     target_assist;
 1880         struct mfi_mpi2_reply_target_cmd_buffer target_cmd;
 1881         struct mfi_mpi2_reply_raid_accel        raid_accel;
 1882         struct mfi_mpi2_reply_default           reply_default;
 1883         uint64_t                                words;
 1884 };
 1885 
 1886 struct IO_REQUEST_INFO {
 1887         uint64_t        ldStartBlock;
 1888         uint32_t        numBlocks;
 1889         uint16_t        ldTgtId;
 1890         uint8_t         isRead;
 1891         uint16_t        devHandle;
 1892         uint64_t        pdBlock;
 1893         uint8_t         fpOkForIo;
 1894 };
 1895 
 1896 #define MFI_SCSI_MAX_TARGETS    128
 1897 #define MFI_SCSI_MAX_LUNS       8
 1898 #define MFI_SCSI_INITIATOR_ID   255
 1899 #define MFI_SCSI_MAX_CMDS       8
 1900 #define MFI_SCSI_MAX_CDB_LEN    16
 1901 
 1902 #endif /* _MFIREG_H */
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FreeBSD/Linux Kernel Cross Reference sys/dev/mfi/mfireg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/mfi/mfireg.h
