The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mfi/mfireg.h

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    1 /*-
    2  * Copyright (c) 2006 IronPort Systems
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 /*-
   27  * Copyright (c) 2007 LSI Corp.
   28  * Copyright (c) 2007 Rajesh Prabhakaran.
   29  * All rights reserved.
   30  *
   31  * Redistribution and use in source and binary forms, with or without
   32  * modification, are permitted provided that the following conditions
   33  * are met:
   34  * 1. Redistributions of source code must retain the above copyright
   35  *    notice, this list of conditions and the following disclaimer.
   36  * 2. Redistributions in binary form must reproduce the above copyright
   37  *    notice, this list of conditions and the following disclaimer in the
   38  *    documentation and/or other materials provided with the distribution.
   39  *
   40  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   41  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   42  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   43  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   44  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   45  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   46  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   47  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   48  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   49  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   50  * SUCH DAMAGE.
   51  */
   52 
   53 #ifndef _MFIREG_H
   54 #define _MFIREG_H
   55 
   56 #include <sys/cdefs.h>
   57 __FBSDID("$FreeBSD$");
   58 
   59 /*
   60  * MegaRAID SAS MFI firmware definitions
   61  *
   62  * Calling this driver 'MegaRAID SAS' is a bit misleading.  It's a completely
   63  * new firmware interface from the old AMI MegaRAID one, and there is no
   64  * reason why this interface should be limited to just SAS.  In any case, LSI
   65  * seems to also call this interface 'MFI', so that will be used here.
   66  */
   67 
   68 /*
   69  * Start with the register set.  All registers are 32 bits wide.
   70  * The usual Intel IOP style setup.
   71  */
   72 #define MFI_IMSG0       0x10    /* Inbound message 0 */
   73 #define MFI_IMSG1       0x14    /* Inbound message 1 */
   74 #define MFI_OMSG0       0x18    /* Outbound message 0 */
   75 #define MFI_OMSG1       0x1c    /* Outbound message 1 */
   76 #define MFI_IDB         0x20    /* Inbound doorbell */
   77 #define MFI_ISTS        0x24    /* Inbound interrupt status */
   78 #define MFI_IMSK        0x28    /* Inbound interrupt mask */
   79 #define MFI_ODB         0x2c    /* Outbound doorbell */
   80 #define MFI_OSTS        0x30    /* Outbound interrupt status */
   81 #define MFI_OMSK        0x34    /* Outbound interrupt mask */
   82 #define MFI_IQP         0x40    /* Inbound queue port */
   83 #define MFI_OQP         0x44    /* Outbound queue port */
   84 
   85 /*
   86  * 1078 specific related register
   87  */
   88 #define MFI_ODR0        0x9c            /* outbound doorbell register0 */
   89 #define MFI_ODCR0       0xa0            /* outbound doorbell clear register0  */
   90 #define MFI_OSP0        0xb0            /* outbound scratch pad0  */
   91 #define MFI_1078_EIM    0x80000004      /* 1078 enable intrrupt mask  */
   92 #define MFI_RMI         0x2             /* reply message interrupt  */
   93 #define MFI_1078_RM     0x80000000      /* reply 1078 message interrupt  */
   94 #define MFI_ODC         0x4             /* outbound doorbell change interrupt */
   95 
   96 /*
   97  * GEN2 specific changes
   98  */
   99 #define MFI_GEN2_EIM    0x00000005      /* GEN2 enable interrupt mask */
  100 #define MFI_GEN2_RM     0x00000001      /* reply GEN2 message interrupt */
  101 
  102 /* Bits for MFI_OSTS */
  103 #define MFI_OSTS_INTR_VALID     0x00000002
  104 
  105 /*
  106  * Firmware state values.  Found in OMSG0 during initialization.
  107  */
  108 #define MFI_FWSTATE_MASK                0xf0000000
  109 #define MFI_FWSTATE_UNDEFINED           0x00000000
  110 #define MFI_FWSTATE_BB_INIT             0x10000000
  111 #define MFI_FWSTATE_FW_INIT             0x40000000
  112 #define MFI_FWSTATE_WAIT_HANDSHAKE      0x60000000
  113 #define MFI_FWSTATE_FW_INIT_2           0x70000000
  114 #define MFI_FWSTATE_DEVICE_SCAN         0x80000000
  115 #define MFI_FWSTATE_FLUSH_CACHE         0xa0000000
  116 #define MFI_FWSTATE_READY               0xb0000000
  117 #define MFI_FWSTATE_OPERATIONAL         0xc0000000
  118 #define MFI_FWSTATE_FAULT               0xf0000000
  119 #define MFI_FWSTATE_MAXSGL_MASK         0x00ff0000
  120 #define MFI_FWSTATE_MAXCMD_MASK         0x0000ffff
  121 
  122 /*
  123  * Control bits to drive the card to ready state.  These go into the IDB
  124  * register.
  125  */
  126 #define MFI_FWINIT_ABORT        0x00000000 /* Abort all pending commands */
  127 #define MFI_FWINIT_READY        0x00000002 /* Move from operational to ready */
  128 #define MFI_FWINIT_MFIMODE      0x00000004 /* unknown */
  129 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
  130 
  131 /* MFI Commands */
  132 typedef enum {
  133         MFI_CMD_INIT =          0x00,
  134         MFI_CMD_LD_READ,
  135         MFI_CMD_LD_WRITE,
  136         MFI_CMD_LD_SCSI_IO,
  137         MFI_CMD_PD_SCSI_IO,
  138         MFI_CMD_DCMD,
  139         MFI_CMD_ABORT,
  140         MFI_CMD_SMP,
  141         MFI_CMD_STP
  142 } mfi_cmd_t;
  143 
  144 /* Direct commands */
  145 typedef enum {
  146         MFI_DCMD_CTRL_GETINFO =         0x01010000,
  147         MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
  148         MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
  149         MFI_DCMD_CTRL_FLUSHCACHE =      0x01101000,
  150         MFI_DCMD_CTRL_SHUTDOWN =        0x01050000,
  151         MFI_DCMD_CTRL_EVENT_GETINFO =   0x01040100,
  152         MFI_DCMD_CTRL_EVENT_GET =       0x01040300,
  153         MFI_DCMD_CTRL_EVENT_WAIT =      0x01040500,
  154         MFI_DCMD_LD_GET_LIST =          0x03010000,
  155         MFI_DCMD_LD_GET_INFO =          0x03020000,
  156         MFI_DCMD_LD_GET_PROP =          0x03030000,
  157         MFI_DCMD_LD_SET_PROP =          0x03040000,
  158         MFI_DCMD_LD_DELETE =            0x03090000,
  159         MFI_DCMD_CFG_READ =             0x04010000,
  160         MFI_DCMD_CFG_ADD =              0x04020000,
  161         MFI_DCMD_CFG_CLEAR =            0x04030000,
  162         MFI_DCMD_CFG_FOREIGN_IMPORT =   0x04060400,
  163         MFI_DCMD_CLUSTER =              0x08000000,
  164         MFI_DCMD_CLUSTER_RESET_ALL =    0x08010100,
  165         MFI_DCMD_CLUSTER_RESET_LD =     0x08010200
  166 } mfi_dcmd_t;
  167 
  168 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
  169 #define MFI_FLUSHCACHE_CTRL     0x01
  170 #define MFI_FLUSHCACHE_DISK     0x02
  171 
  172 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
  173 #define MFI_SHUTDOWN_SPINDOWN   0x01
  174 
  175 /*
  176  * MFI Frame flags
  177  */
  178 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
  179 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
  180 #define MFI_FRAME_SGL32                         0x0000
  181 #define MFI_FRAME_SGL64                         0x0002
  182 #define MFI_FRAME_SENSE32                       0x0000
  183 #define MFI_FRAME_SENSE64                       0x0004
  184 #define MFI_FRAME_DIR_NONE                      0x0000
  185 #define MFI_FRAME_DIR_WRITE                     0x0008
  186 #define MFI_FRAME_DIR_READ                      0x0010
  187 #define MFI_FRAME_DIR_BOTH                      0x0018
  188 
  189 /* MFI Status codes */
  190 typedef enum {
  191         MFI_STAT_OK =                   0x00,
  192         MFI_STAT_INVALID_CMD,
  193         MFI_STAT_INVALID_DCMD,
  194         MFI_STAT_INVALID_PARAMETER,
  195         MFI_STAT_INVALID_SEQUENCE_NUMBER,
  196         MFI_STAT_ABORT_NOT_POSSIBLE,
  197         MFI_STAT_APP_HOST_CODE_NOT_FOUND,
  198         MFI_STAT_APP_IN_USE,
  199         MFI_STAT_APP_NOT_INITIALIZED,
  200         MFI_STAT_ARRAY_INDEX_INVALID,
  201         MFI_STAT_ARRAY_ROW_NOT_EMPTY,
  202         MFI_STAT_CONFIG_RESOURCE_CONFLICT,
  203         MFI_STAT_DEVICE_NOT_FOUND,
  204         MFI_STAT_DRIVE_TOO_SMALL,
  205         MFI_STAT_FLASH_ALLOC_FAIL,
  206         MFI_STAT_FLASH_BUSY,
  207         MFI_STAT_FLASH_ERROR =          0x10,
  208         MFI_STAT_FLASH_IMAGE_BAD,
  209         MFI_STAT_FLASH_IMAGE_INCOMPLETE,
  210         MFI_STAT_FLASH_NOT_OPEN,
  211         MFI_STAT_FLASH_NOT_STARTED,
  212         MFI_STAT_FLUSH_FAILED,
  213         MFI_STAT_HOST_CODE_NOT_FOUNT,
  214         MFI_STAT_LD_CC_IN_PROGRESS,
  215         MFI_STAT_LD_INIT_IN_PROGRESS,
  216         MFI_STAT_LD_LBA_OUT_OF_RANGE,
  217         MFI_STAT_LD_MAX_CONFIGURED,
  218         MFI_STAT_LD_NOT_OPTIMAL,
  219         MFI_STAT_LD_RBLD_IN_PROGRESS,
  220         MFI_STAT_LD_RECON_IN_PROGRESS,
  221         MFI_STAT_LD_WRONG_RAID_LEVEL,
  222         MFI_STAT_MAX_SPARES_EXCEEDED,
  223         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
  224         MFI_STAT_MFC_HW_ERROR,
  225         MFI_STAT_NO_HW_PRESENT,
  226         MFI_STAT_NOT_FOUND,
  227         MFI_STAT_NOT_IN_ENCL,
  228         MFI_STAT_PD_CLEAR_IN_PROGRESS,
  229         MFI_STAT_PD_TYPE_WRONG,
  230         MFI_STAT_PR_DISABLED,
  231         MFI_STAT_ROW_INDEX_INVALID,
  232         MFI_STAT_SAS_CONFIG_INVALID_ACTION,
  233         MFI_STAT_SAS_CONFIG_INVALID_DATA,
  234         MFI_STAT_SAS_CONFIG_INVALID_PAGE,
  235         MFI_STAT_SAS_CONFIG_INVALID_TYPE,
  236         MFI_STAT_SCSI_DONE_WITH_ERROR,
  237         MFI_STAT_SCSI_IO_FAILED,
  238         MFI_STAT_SCSI_RESERVATION_CONFLICT,
  239         MFI_STAT_SHUTDOWN_FAILED =      0x30,
  240         MFI_STAT_TIME_NOT_SET,
  241         MFI_STAT_WRONG_STATE,
  242         MFI_STAT_LD_OFFLINE,
  243         MFI_STAT_PEER_NOTIFICATION_REJECTED,
  244         MFI_STAT_PEER_NOTIFICATION_FAILED,
  245         MFI_STAT_RESERVATION_IN_PROGRESS,
  246         MFI_STAT_I2C_ERRORS_DETECTED,
  247         MFI_STAT_PCI_ERRORS_DETECTED,
  248         MFI_STAT_INVALID_STATUS =       0xFF
  249 } mfi_status_t;
  250 
  251 typedef enum {
  252         MFI_EVT_CLASS_DEBUG =           -2,
  253         MFI_EVT_CLASS_PROGRESS =        -1,
  254         MFI_EVT_CLASS_INFO =            0,
  255         MFI_EVT_CLASS_WARNING =         1,
  256         MFI_EVT_CLASS_CRITICAL =        2,
  257         MFI_EVT_CLASS_FATAL =           3,
  258         MFI_EVT_CLASS_DEAD =            4
  259 } mfi_evt_class_t;
  260 
  261 typedef enum {
  262         MFI_EVT_LOCALE_LD =             0x0001,
  263         MFI_EVT_LOCALE_PD =             0x0002,
  264         MFI_EVT_LOCALE_ENCL =           0x0004,
  265         MFI_EVT_LOCALE_BBU =            0x0008,
  266         MFI_EVT_LOCALE_SAS =            0x0010,
  267         MFI_EVT_LOCALE_CTRL =           0x0020,
  268         MFI_EVT_LOCALE_CONFIG =         0x0040,
  269         MFI_EVT_LOCALE_CLUSTER =        0x0080,
  270         MFI_EVT_LOCALE_ALL =            0xffff
  271 } mfi_evt_locale_t;
  272 
  273 typedef enum {
  274         MR_EVT_ARGS_NONE =              0x00,
  275         MR_EVT_ARGS_CDB_SENSE,
  276         MR_EVT_ARGS_LD,
  277         MR_EVT_ARGS_LD_COUNT,
  278         MR_EVT_ARGS_LD_LBA,
  279         MR_EVT_ARGS_LD_OWNER,
  280         MR_EVT_ARGS_LD_LBA_PD_LBA,
  281         MR_EVT_ARGS_LD_PROG,
  282         MR_EVT_ARGS_LD_STATE,
  283         MR_EVT_ARGS_LD_STRIP,
  284         MR_EVT_ARGS_PD,
  285         MR_EVT_ARGS_PD_ERR,
  286         MR_EVT_ARGS_PD_LBA,
  287         MR_EVT_ARGS_PD_LBA_LD,
  288         MR_EVT_ARGS_PD_PROG,
  289         MR_EVT_ARGS_PD_STATE,
  290         MR_EVT_ARGS_PCI,
  291         MR_EVT_ARGS_RATE,
  292         MR_EVT_ARGS_STR,
  293         MR_EVT_ARGS_TIME,
  294         MR_EVT_ARGS_ECC
  295 } mfi_evt_args;
  296 
  297 typedef enum {
  298         MR_LD_CACHE_WRITE_BACK =        0x01,
  299         MR_LD_CACHE_WRITE_ADAPTIVE =    0x02,
  300         MR_LD_CACHE_READ_AHEAD =        0x04,
  301         MR_LD_CACHE_READ_ADAPTIVE =     0x08,
  302         MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
  303         MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
  304         MR_LD_CACHE_ALLOW_READ_CACHE =  0x40
  305 } mfi_ld_cache;
  306 
  307 typedef enum {
  308         MR_PD_CACHE_UNCHANGED  =        0,
  309         MR_PD_CACHE_ENABLE =            1,
  310         MR_PD_CACHE_DISABLE =           2
  311 } mfi_pd_cache;
  312 
  313 /*
  314  * Other propertities and definitions
  315  */
  316 #define MFI_MAX_PD_CHANNELS     2
  317 #define MFI_MAX_LD_CHANNELS     2
  318 #define MFI_MAX_CHANNELS        (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
  319 #define MFI_MAX_CHANNEL_DEVS    128
  320 #define MFI_DEFAULT_ID          -1
  321 #define MFI_MAX_LUN             8
  322 #define MFI_MAX_LD              64
  323 
  324 #define MFI_FRAME_SIZE          64
  325 #define MFI_MBOX_SIZE           12
  326 
  327 /* Firmware flashing can take 40s */
  328 #define MFI_POLL_TIMEOUT_SECS   50
  329 
  330 /* Allow for speedier math calculations */
  331 #define MFI_SECTOR_LEN          512
  332 
  333 /* Scatter Gather elements */
  334 struct mfi_sg32 {
  335         uint32_t        addr;
  336         uint32_t        len;
  337 } __packed;
  338 
  339 struct mfi_sg64 {
  340         uint64_t        addr;
  341         uint32_t        len;
  342 } __packed;
  343 
  344 union mfi_sgl {
  345         struct mfi_sg32 sg32[1];
  346         struct mfi_sg64 sg64[1];
  347 } __packed;
  348 
  349 /* Message frames.  All messages have a common header */
  350 struct mfi_frame_header {
  351         uint8_t         cmd;
  352         uint8_t         sense_len;
  353         uint8_t         cmd_status;
  354         uint8_t         scsi_status;
  355         uint8_t         target_id;
  356         uint8_t         lun_id;
  357         uint8_t         cdb_len;
  358         uint8_t         sg_count;
  359         uint32_t        context;
  360         uint32_t        pad0;
  361         uint16_t        flags;
  362 #define MFI_FRAME_DATAOUT       0x08
  363 #define MFI_FRAME_DATAIN        0x10
  364         uint16_t        timeout;
  365         uint32_t        data_len;
  366 } __packed;
  367 
  368 struct mfi_init_frame {
  369         struct mfi_frame_header header;
  370         uint32_t        qinfo_new_addr_lo;
  371         uint32_t        qinfo_new_addr_hi;
  372         uint32_t        qinfo_old_addr_lo;
  373         uint32_t        qinfo_old_addr_hi;
  374         uint32_t        reserved[6];
  375 } __packed;
  376 
  377 #define MFI_IO_FRAME_SIZE 40
  378 struct mfi_io_frame {
  379         struct mfi_frame_header header;
  380         uint32_t        sense_addr_lo;
  381         uint32_t        sense_addr_hi;
  382         uint32_t        lba_lo;
  383         uint32_t        lba_hi;
  384         union mfi_sgl   sgl;
  385 } __packed;
  386 
  387 #define MFI_PASS_FRAME_SIZE 48
  388 struct mfi_pass_frame {
  389         struct mfi_frame_header header;
  390         uint32_t        sense_addr_lo;
  391         uint32_t        sense_addr_hi;
  392         uint8_t         cdb[16];
  393         union mfi_sgl   sgl;
  394 } __packed;
  395 
  396 #define MFI_DCMD_FRAME_SIZE 40
  397 struct mfi_dcmd_frame {
  398         struct mfi_frame_header header;
  399         uint32_t        opcode;
  400         uint8_t         mbox[MFI_MBOX_SIZE];
  401         union mfi_sgl   sgl;
  402 } __packed;
  403 
  404 struct mfi_abort_frame {
  405         struct mfi_frame_header header;
  406         uint32_t        abort_context;
  407         uint32_t        pad;
  408         uint32_t        abort_mfi_addr_lo;
  409         uint32_t        abort_mfi_addr_hi;
  410         uint32_t        reserved[6];
  411 } __packed;
  412 
  413 struct mfi_smp_frame {
  414         struct mfi_frame_header header;
  415         uint64_t        sas_addr;
  416         union {
  417                 struct mfi_sg32 sg32[2];
  418                 struct mfi_sg64 sg64[2];
  419         } sgl;
  420 } __packed;
  421 
  422 struct mfi_stp_frame {
  423         struct mfi_frame_header header;
  424         uint16_t        fis[10];
  425         uint32_t        stp_flags;
  426         union {
  427                 struct mfi_sg32 sg32[2];
  428                 struct mfi_sg64 sg64[2];
  429         } sgl;
  430 } __packed;
  431 
  432 union mfi_frame {
  433         struct mfi_frame_header header;
  434         struct mfi_init_frame   init;
  435         struct mfi_io_frame     io;
  436         struct mfi_pass_frame   pass;
  437         struct mfi_dcmd_frame   dcmd;
  438         struct mfi_abort_frame  abort;
  439         struct mfi_smp_frame    smp;
  440         struct mfi_stp_frame    stp;
  441         uint8_t                 bytes[MFI_FRAME_SIZE];
  442 };
  443 
  444 #define MFI_SENSE_LEN 128
  445 struct mfi_sense {
  446         uint8_t         data[MFI_SENSE_LEN];
  447 };
  448 
  449 /* The queue init structure that is passed with the init message */
  450 struct mfi_init_qinfo {
  451         uint32_t        flags;
  452         uint32_t        rq_entries;
  453         uint32_t        rq_addr_lo;
  454         uint32_t        rq_addr_hi;
  455         uint32_t        pi_addr_lo;
  456         uint32_t        pi_addr_hi;
  457         uint32_t        ci_addr_lo;
  458         uint32_t        ci_addr_hi;
  459 } __packed;
  460 
  461 /* SAS (?) controller properties, part of mfi_ctrl_info */
  462 struct mfi_ctrl_props {
  463         uint16_t        seq_num;
  464         uint16_t        pred_fail_poll_interval;
  465         uint16_t        intr_throttle_cnt;
  466         uint16_t        intr_throttle_timeout;
  467         uint8_t         rebuild_rate;
  468         uint8_t         patrol_read_rate;
  469         uint8_t         bgi_rate;
  470         uint8_t         cc_rate;
  471         uint8_t         recon_rate;
  472         uint8_t         cache_flush_interval;
  473         uint8_t         spinup_drv_cnt;
  474         uint8_t         spinup_delay;
  475         uint8_t         cluster_enable;
  476         uint8_t         coercion_mode;
  477         uint8_t         alarm_enable;
  478         uint8_t         disable_auto_rebuild;
  479         uint8_t         disable_battery_warn;
  480         uint8_t         ecc_bucket_size;
  481         uint16_t        ecc_bucket_leak_rate;
  482         uint8_t         restore_hotspare_on_insertion;
  483         uint8_t         expose_encl_devices;
  484         uint8_t         reserved[38];
  485 } __packed;
  486 
  487 /* PCI information about the card. */
  488 struct mfi_info_pci {
  489         uint16_t        vendor;
  490         uint16_t        device;
  491         uint16_t        subvendor;
  492         uint16_t        subdevice;
  493         uint8_t         reserved[24];
  494 } __packed;
  495 
  496 /* Host (front end) interface information */
  497 struct mfi_info_host {
  498         uint8_t         type;
  499 #define MFI_INFO_HOST_PCIX      0x01
  500 #define MFI_INFO_HOST_PCIE      0x02
  501 #define MFI_INFO_HOST_ISCSI     0x04
  502 #define MFI_INFO_HOST_SAS3G     0x08
  503         uint8_t         reserved[6];
  504         uint8_t         port_count;
  505         uint64_t        port_addr[8];
  506 } __packed;
  507 
  508 /* Device (back end) interface information */
  509 struct mfi_info_device {
  510         uint8_t         type;
  511 #define MFI_INFO_DEV_SPI        0x01
  512 #define MFI_INFO_DEV_SAS3G      0x02
  513 #define MFI_INFO_DEV_SATA1      0x04
  514 #define MFI_INFO_DEV_SATA3G     0x08
  515         uint8_t         reserved[6];
  516         uint8_t         port_count;
  517         uint64_t        port_addr[8];
  518 } __packed;
  519 
  520 /* Firmware component information */
  521 struct mfi_info_component {
  522         char             name[8];
  523         char             version[32];
  524         char             build_date[16];
  525         char             build_time[16];
  526 } __packed;
  527 
  528 /* Controller default settings */
  529 struct mfi_defaults {
  530         uint64_t        sas_addr;
  531         uint8_t         phy_polarity;
  532         uint8_t         background_rate;
  533         uint8_t         stripe_size;
  534         uint8_t         flush_time;
  535         uint8_t         write_back;
  536         uint8_t         read_ahead;
  537         uint8_t         cache_when_bbu_bad;
  538         uint8_t         cached_io;
  539         uint8_t         smart_mode;
  540         uint8_t         alarm_disable;
  541         uint8_t         coercion;
  542         uint8_t         zrc_config;
  543         uint8_t         dirty_led_shows_drive_activity;
  544         uint8_t         bios_continue_on_error;
  545         uint8_t         spindown_mode;
  546         uint8_t         allowed_device_types;
  547         uint8_t         allow_mix_in_enclosure;
  548         uint8_t         allow_mix_in_ld;
  549         uint8_t         allow_sata_in_cluster;
  550         uint8_t         max_chained_enclosures;
  551         uint8_t         disable_ctrl_r;
  552         uint8_t         enabel_web_bios;
  553         uint8_t         phy_polarity_split;
  554         uint8_t         direct_pd_mapping;
  555         uint8_t         bios_enumerate_lds;
  556         uint8_t         restored_hot_spare_on_insertion;
  557         uint8_t         expose_enclosure_devices;
  558         uint8_t         maintain_pd_fail_history;
  559         uint8_t         resv[28];
  560 } __packed;
  561 
  562 /* Controller default settings */
  563 struct mfi_bios_data {
  564         uint16_t        boot_target_id;
  565         uint8_t         do_not_int_13;
  566         uint8_t         continue_on_error;
  567         uint8_t         verbose;
  568         uint8_t         geometry;
  569         uint8_t         expose_all_drives;
  570         uint8_t         reserved[56];
  571         uint8_t         check_sum;
  572 } __packed;
  573 
  574 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
  575 struct mfi_ctrl_info {
  576         struct mfi_info_pci     pci;
  577         struct mfi_info_host    host;
  578         struct mfi_info_device  device;
  579 
  580         /* Firmware components that are present and active. */
  581         uint32_t                image_check_word;
  582         uint32_t                image_component_count;
  583         struct mfi_info_component image_component[8];
  584 
  585         /* Firmware components that have been flashed but are inactive */
  586         uint32_t                pending_image_component_count;
  587         struct mfi_info_component pending_image_component[8];
  588 
  589         uint8_t                 max_arms;
  590         uint8_t                 max_spans;
  591         uint8_t                 max_arrays;
  592         uint8_t                 max_lds;
  593         char                    product_name[80];
  594         char                    serial_number[32];
  595         uint32_t                hw_present;
  596 #define MFI_INFO_HW_BBU         0x01
  597 #define MFI_INFO_HW_ALARM       0x02
  598 #define MFI_INFO_HW_NVRAM       0x04
  599 #define MFI_INFO_HW_UART        0x08
  600         uint32_t                current_fw_time;
  601         uint16_t                max_cmds;
  602         uint16_t                max_sg_elements;
  603         uint32_t                max_request_size;
  604         uint16_t                lds_present;
  605         uint16_t                lds_degraded;
  606         uint16_t                lds_offline;
  607         uint16_t                pd_present;
  608         uint16_t                pd_disks_present;
  609         uint16_t                pd_disks_pred_failure;
  610         uint16_t                pd_disks_failed;
  611         uint16_t                nvram_size;
  612         uint16_t                memory_size;
  613         uint16_t                flash_size;
  614         uint16_t                ram_correctable_errors;
  615         uint16_t                ram_uncorrectable_errors;
  616         uint8_t                 cluster_allowed;
  617         uint8_t                 cluster_active;
  618         uint16_t                max_strips_per_io;
  619 
  620         uint32_t                raid_levels;
  621 #define MFI_INFO_RAID_0         0x01
  622 #define MFI_INFO_RAID_1         0x02
  623 #define MFI_INFO_RAID_5         0x04
  624 #define MFI_INFO_RAID_1E        0x08
  625 #define MFI_INFO_RAID_6         0x10
  626 
  627         uint32_t                adapter_ops;
  628 #define MFI_INFO_AOPS_RBLD_RATE         0x0001
  629 #define MFI_INFO_AOPS_CC_RATE           0x0002
  630 #define MFI_INFO_AOPS_BGI_RATE          0x0004
  631 #define MFI_INFO_AOPS_RECON_RATE        0x0008
  632 #define MFI_INFO_AOPS_PATROL_RATE       0x0010
  633 #define MFI_INFO_AOPS_ALARM_CONTROL     0x0020
  634 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
  635 #define MFI_INFO_AOPS_BBU               0x0080
  636 #define MFI_INFO_AOPS_SPANNING_ALLOWED  0x0100
  637 #define MFI_INFO_AOPS_DEDICATED_SPARES  0x0200
  638 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
  639 #define MFI_INFO_AOPS_FOREIGN_IMPORT    0x0800
  640 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC   0x1000
  641 #define MFI_INFO_AOPS_MIXED_ARRAY       0x2000
  642 #define MFI_INFO_AOPS_GLOBAL_SPARES     0x4000
  643 
  644         uint32_t                ld_ops;
  645 #define MFI_INFO_LDOPS_READ_POLICY      0x01
  646 #define MFI_INFO_LDOPS_WRITE_POLICY     0x02
  647 #define MFI_INFO_LDOPS_IO_POLICY        0x04
  648 #define MFI_INFO_LDOPS_ACCESS_POLICY    0x08
  649 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
  650 
  651         struct {
  652                 uint8_t         min;
  653                 uint8_t         max;
  654                 uint8_t         reserved[2];
  655         } __packed stripe_sz_ops;
  656 
  657         uint32_t                pd_ops;
  658 #define MFI_INFO_PDOPS_FORCE_ONLINE     0x01
  659 #define MFI_INFO_PDOPS_FORCE_OFFLINE    0x02
  660 #define MFI_INFO_PDOPS_FORCE_REBUILD    0x04
  661 
  662         uint32_t                pd_mix_support;
  663 #define MFI_INFO_PDMIX_SAS              0x01
  664 #define MFI_INFO_PDMIX_SATA             0x02
  665 #define MFI_INFO_PDMIX_ENCL             0x04
  666 #define MFI_INFO_PDMIX_LD               0x08
  667 #define MFI_INFO_PDMIX_SATA_CLUSTER     0x10
  668 
  669         uint8_t                 ecc_bucket_count;
  670         uint8_t                 reserved2[11];
  671         struct mfi_ctrl_props   properties;
  672         char                    package_version[0x60];
  673         uint8_t                 pad[0x800 - 0x6a0];
  674 } __packed;
  675 
  676 /* keep track of an event. */
  677 union mfi_evt {
  678         struct {
  679                 uint16_t        locale;
  680                 uint8_t         reserved;
  681                 int8_t          class;
  682         } members;
  683         uint32_t                word;
  684 } __packed;
  685 
  686 /* event log state. */
  687 struct mfi_evt_log_state {
  688         uint32_t                newest_seq_num;
  689         uint32_t                oldest_seq_num;
  690         uint32_t                clear_seq_num;
  691         uint32_t                shutdown_seq_num;
  692         uint32_t                boot_seq_num;
  693 } __packed;
  694 
  695 struct mfi_progress {
  696         uint16_t                progress;
  697         uint16_t                elapsed_seconds;
  698 } __packed;
  699 
  700 struct mfi_evt_ld {
  701         uint16_t                target_id;
  702         uint8_t                 ld_index;
  703         uint8_t                 reserved;
  704 } __packed;
  705 
  706 struct mfi_evt_pd {
  707         uint16_t                device_id;
  708         uint8_t                 enclosure_index;
  709         uint8_t                 slot_number;
  710 } __packed;
  711 
  712 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
  713 struct mfi_evt_detail {
  714         uint32_t                seq;
  715         uint32_t                time;
  716         uint32_t                code;
  717         union mfi_evt           class;
  718         uint8_t                 arg_type;
  719         uint8_t                 reserved1[15];
  720 
  721         union {
  722                 struct {
  723                         struct mfi_evt_pd       pd;
  724                         uint8_t                 cdb_len;
  725                         uint8_t                 sense_len;
  726                         uint8_t                 reserved[2];
  727                         uint8_t                 cdb[16];
  728                         uint8_t                 sense[64];
  729                 } cdb_sense;
  730 
  731                 struct mfi_evt_ld               ld;
  732 
  733                 struct {
  734                         struct mfi_evt_ld       ld;
  735                         uint64_t                count;
  736                 } ld_count;
  737 
  738                 struct {
  739                         uint64_t                lba;
  740                         struct mfi_evt_ld       ld;
  741                 } ld_lba;
  742 
  743                 struct {
  744                         struct mfi_evt_ld       ld;
  745                         uint32_t                pre_owner;
  746                         uint32_t                new_owner;
  747                 } ld_owner;
  748 
  749                 struct {
  750                         uint64_t                ld_lba;
  751                         uint64_t                pd_lba;
  752                         struct mfi_evt_ld       ld;
  753                         struct mfi_evt_pd       pd;
  754                 } ld_lba_pd_lba;
  755 
  756                 struct {
  757                         struct mfi_evt_ld       ld;
  758                         struct mfi_progress     prog;
  759                 } ld_prog;
  760 
  761                 struct {
  762                         struct mfi_evt_ld       ld;
  763                         uint32_t                prev_state;
  764                         uint32_t                new_state;
  765                 } ld_state;
  766 
  767                 struct {
  768                         uint64_t                strip;
  769                         struct mfi_evt_ld       ld;
  770                 } ld_strip;
  771 
  772                 struct mfi_evt_pd               pd;
  773 
  774                 struct {
  775                         struct mfi_evt_pd       pd;
  776                         uint32_t                err;
  777                 } pd_err;
  778 
  779                 struct {
  780                         uint64_t                lba;
  781                         struct mfi_evt_pd       pd;
  782                 } pd_lba;
  783 
  784                 struct {
  785                         uint64_t                lba;
  786                         struct mfi_evt_pd       pd;
  787                         struct mfi_evt_ld       ld;
  788                 } pd_lba_ld;
  789 
  790                 struct {
  791                         struct mfi_evt_pd       pd;
  792                         struct mfi_progress     prog;
  793                 } pd_prog;
  794 
  795                 struct {
  796                         struct mfi_evt_pd       ld;
  797                         uint32_t                prev_state;
  798                         uint32_t                new_state;
  799                 } pd_state;
  800 
  801                 struct {
  802                         uint16_t                venderId;
  803                         uint16_t                deviceId;
  804                         uint16_t                subVenderId;
  805                         uint16_t                subDeviceId;
  806                 } pci;
  807 
  808                 uint32_t                        rate;
  809 
  810                 char                            str[96];
  811 
  812                 struct {
  813                         uint32_t                rtc;
  814                         uint16_t                elapsedSeconds;
  815                 } time;
  816 
  817                 struct {
  818                         uint32_t                ecar;
  819                         uint32_t                elog;
  820                         char                    str[64];
  821                 } ecc;
  822 
  823                 uint8_t         b[96];
  824                 uint16_t        s[48];
  825                 uint32_t        w[24];
  826                 uint64_t        d[12];
  827         } args;
  828 
  829         char description[128];
  830 } __packed;
  831 
  832 struct mfi_evt_list {
  833         uint32_t                count;
  834         uint32_t                reserved;
  835         struct mfi_evt_detail   event[1];
  836 } __packed;
  837 
  838 union mfi_pd_ref {
  839         struct {
  840                 uint16_t        device_id;
  841                 uint16_t        seq_num;
  842         } v;
  843         uint32_t        ref;
  844 } __packed;
  845 
  846 union mfi_pd_ddf_type {
  847         struct {
  848                 union {
  849                         struct {
  850                                 uint16_t        forced_pd_guid  : 1;
  851                                 uint16_t        in_vd           : 1;
  852                                 uint16_t        is_global_spare : 1;
  853                                 uint16_t        is_spare        : 1;
  854                                 uint16_t        is_foreign      : 1;
  855                                 uint16_t        reserved        : 7;
  856                                 uint16_t        intf            : 4;
  857                         } pd_type;
  858                         uint16_t        type;
  859                 } v;
  860                 uint16_t                reserved;
  861         } ddf;
  862         struct {
  863                 uint32_t                reserved;
  864         } non_disk;
  865         uint32_t                        type;
  866 } __packed;
  867 
  868 struct mfi_pd_progress {
  869         struct {
  870                 uint32_t                rbld    : 1;
  871                 uint32_t                patrol  : 1;
  872                 uint32_t                clear   : 1;
  873                 uint32_t                reserved: 29;
  874         } active;
  875         struct mfi_progress             rbld;
  876         struct mfi_progress             patrol;
  877         struct mfi_progress             clear;
  878         struct mfi_progress             reserved[4];
  879 } __packed;
  880 
  881 struct mfi_pd_info {
  882         union mfi_pd_ref                ref;
  883         uint8_t                         inquiry_data[96];
  884         uint8_t                         vpd_page83[64];
  885         uint8_t                         not_supported;
  886         uint8_t                         scsi_dev_type;
  887         uint8_t                         connected_port_bitmap;
  888         uint8_t                         device_speed;
  889         uint32_t                        media_err_count;
  890         uint32_t                        other_err_count;
  891         uint32_t                        pred_fail_count;
  892         uint32_t                        last_pred_fail_event_seq_num;
  893         uint16_t                        fw_state;
  894         uint8_t                         disable_for_removal;
  895         uint8_t                         link_speed;
  896         union mfi_pd_ddf_type           state;
  897         struct {
  898                 uint8_t                 count;
  899                 uint8_t                 is_path_broken;
  900                 uint8_t                 reserved[6];
  901                 uint64_t                sas_addr[4];
  902         } path_info;
  903         uint64_t                        raw_size;
  904         uint64_t                        non_coerced_size;
  905         uint64_t                        coerced_size;
  906         uint16_t                        encl_device_id;
  907         uint8_t                         encl_index;
  908         uint8_t                         slot_number;
  909         struct mfi_pd_progress          prog_info;
  910         uint8_t                         bad_block_table_full;
  911         uint8_t                         unusable_in_current_config;
  912         uint8_t                         vpd_page83_ext[64];
  913         uint8_t                         reserved[512-358];
  914 } __packed;
  915 
  916 struct mfi_pd_address {
  917         uint16_t                device_id;
  918         uint16_t                encl_device_id;
  919         uint8_t                 encl_index;
  920         uint8_t                 slot_number;
  921         uint8_t                 scsi_dev_type;
  922         uint8_t                 connect_port_bitmap;
  923         uint64_t                sas_addr[2];
  924 } __packed;
  925 
  926 struct mfi_pd_list {
  927         uint32_t                size;
  928         uint32_t                count;
  929         uint8_t                 data;
  930         /*
  931         struct mfi_pd_address   addr[];
  932         */
  933 } __packed;
  934 
  935 union mfi_ld_ref {
  936         struct {
  937                 uint8_t         target_id;
  938                 uint8_t         reserved;
  939                 uint16_t        seq;
  940         } v;
  941         uint32_t                ref;
  942 } __packed;
  943 
  944 struct mfi_ld_list {
  945         uint32_t                ld_count;
  946         uint32_t                reserved1;
  947         struct {
  948                 union mfi_ld_ref        ld;
  949                 uint8_t         state;
  950                 uint8_t         reserved2[3];
  951                 uint64_t        size;
  952         } ld_list[MFI_MAX_LD];
  953 } __packed;
  954 
  955 enum mfi_ld_access {
  956         MFI_LD_ACCESS_RW =      0,
  957         MFI_LD_ACCSSS_RO =      2,
  958         MFI_LD_ACCESS_BLOCKED = 3,
  959 };
  960 #define MFI_LD_ACCESS_MASK      3
  961 
  962 enum mfi_ld_state {
  963         MFI_LD_STATE_OFFLINE =                  0,
  964         MFI_LD_STATE_PARTIALLY_DEGRADED =       1,
  965         MFI_LD_STATE_DEGRADED =                 2,
  966         MFI_LD_STATE_OPTIMAL =                  3
  967 };
  968 
  969 struct mfi_ld_props {
  970         union mfi_ld_ref        ld;
  971         char                    name[16];
  972         uint8_t                 default_cache_policy;
  973         uint8_t                 access_policy;
  974         uint8_t                 disk_cache_policy;
  975         uint8_t                 current_cache_policy;
  976         uint8_t                 no_bgi;
  977         uint8_t                 reserved[7];
  978 } __packed;
  979 
  980 struct mfi_ld_params {
  981         uint8_t                 primary_raid_level;
  982         uint8_t                 raid_level_qualifier;
  983         uint8_t                 secondary_raid_level;
  984         uint8_t                 stripe_size;
  985         uint8_t                 num_drives;
  986         uint8_t                 span_depth;
  987         uint8_t                 state;
  988         uint8_t                 init_state;
  989         uint8_t                 is_consistent;
  990         uint8_t                 reserved[23];
  991 } __packed;
  992 
  993 struct mfi_ld_progress {
  994         uint32_t                active;
  995 #define MFI_LD_PROGRESS_CC      (1<<0)
  996 #define MFI_LD_PROGRESS_BGI     (1<<1)
  997 #define MFI_LD_PROGRESS_FGI     (1<<2)
  998 #define MFI_LD_PORGRESS_RECON   (1<<3)
  999         struct mfi_progress     cc;
 1000         struct mfi_progress     bgi;
 1001         struct mfi_progress     fgi;
 1002         struct mfi_progress     recon;
 1003         struct mfi_progress     reserved[4];
 1004 } __packed;
 1005 
 1006 struct mfi_span {
 1007         uint64_t                start_block;
 1008         uint64_t                num_blocks;
 1009         uint16_t                array_ref;
 1010         uint8_t                 reserved[6];
 1011 } __packed;
 1012 
 1013 #define MFI_MAX_SPAN_DEPTH      8
 1014 struct mfi_ld_config {
 1015         struct mfi_ld_props     properties;
 1016         struct mfi_ld_params    params;
 1017         struct mfi_span         span[MFI_MAX_SPAN_DEPTH];
 1018 } __packed;
 1019 
 1020 struct mfi_ld_info {
 1021         struct mfi_ld_config    ld_config;
 1022         uint64_t                size;
 1023         struct mfi_ld_progress  progress;
 1024         uint16_t                cluster_owner;
 1025         uint8_t                 reconstruct_active;
 1026         uint8_t                 reserved1[1];
 1027         uint8_t                 vpd_page83[64];
 1028         uint8_t                 reserved2[16];
 1029 } __packed;
 1030 
 1031 union mfi_spare_type {
 1032         struct {
 1033                 uint8_t         is_dedicate             :1;
 1034                 uint8_t         is_revertable           :1;
 1035                 uint8_t         is_encl_affinity        :1;
 1036                 uint8_t         reserved                :5;
 1037         } v;
 1038         uint8_t         type;
 1039 } __packed;
 1040 
 1041 #define MAX_ARRAYS 16
 1042 struct mfi_spare {
 1043         union mfi_pd_ref        ref;
 1044         union mfi_spare_type    spare_type;
 1045         uint8_t                 reserved[2];
 1046         uint8_t                 array_count;
 1047         uint16_t                array_refd[MAX_ARRAYS];
 1048 } __packed;
 1049 
 1050 #define MAX_ROW_SIZE 32
 1051 struct mfi_array {
 1052         uint64_t                        size;
 1053         uint8_t                         num_drives;
 1054         uint8_t                         reserved;
 1055         uint16_t                        array_ref;
 1056         uint8_t                         pad[20];
 1057         struct {
 1058                 union mfi_pd_ref        ref;
 1059                 uint16_t                fw_state;
 1060                 struct {
 1061                         uint8_t         pd;
 1062                         uint8_t         slot;
 1063                 } encl;
 1064         } pd[MAX_ROW_SIZE];
 1065 } __packed;
 1066 
 1067 struct mfi_config_data {
 1068         uint32_t                size;
 1069         uint16_t                array_count;
 1070         uint16_t                array_size;
 1071         uint16_t                log_drv_count;
 1072         uint16_t                log_drv_size;
 1073         uint16_t                spares_count;
 1074         uint16_t                spares_size;
 1075         uint8_t                 reserved[16];
 1076         uint8_t                 data;
 1077         /*
 1078         struct mfi_array        array[];
 1079         struct mfi_ld_config    ld[];
 1080         struct mfi_spare        spare[];
 1081         */
 1082 } __packed;
 1083 
 1084 #define MFI_SCSI_MAX_TARGETS    128
 1085 #define MFI_SCSI_MAX_LUNS       8
 1086 #define MFI_SCSI_INITIATOR_ID   255
 1087 #define MFI_SCSI_MAX_CMDS       8
 1088 #define MFI_SCSI_MAX_CDB_LEN    16
 1089 
 1090 #endif /* _MFIREG_H */

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