mfireg.h

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    1 /*-
    2  * Copyright (c) 2006 IronPort Systems
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 /*-
   27  * Copyright (c) 2007 LSI Corp.
   28  * Copyright (c) 2007 Rajesh Prabhakaran.
   29  * All rights reserved.
   30  *
   31  * Redistribution and use in source and binary forms, with or without
   32  * modification, are permitted provided that the following conditions
   33  * are met:
   34  * 1. Redistributions of source code must retain the above copyright
   35  *    notice, this list of conditions and the following disclaimer.
   36  * 2. Redistributions in binary form must reproduce the above copyright
   37  *    notice, this list of conditions and the following disclaimer in the
   38  *    documentation and/or other materials provided with the distribution.
   39  *
   40  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   41  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   42  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   43  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   44  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   45  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   46  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   47  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   48  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   49  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   50  * SUCH DAMAGE.
   51  */
   52 
   53 #ifndef _MFIREG_H
   54 #define _MFIREG_H
   55 
   56 #include <sys/cdefs.h>
   57 __FBSDID("$FreeBSD$");
   58 
   59 /*
   60  * MegaRAID SAS MFI firmware definitions
   61  *
   62  * Calling this driver 'MegaRAID SAS' is a bit misleading.  It's a completely
   63  * new firmware interface from the old AMI MegaRAID one, and there is no
   64  * reason why this interface should be limited to just SAS.  In any case, LSI
   65  * seems to also call this interface 'MFI', so that will be used here.
   66  */
   67 #define MEGAMFI_FRAME_SIZE              64
   68 /*
   69  * Start with the register set.  All registers are 32 bits wide.
   70  * The usual Intel IOP style setup.
   71  */
   72 #define MFI_IMSG0       0x10    /* Inbound message 0 */
   73 #define MFI_IMSG1       0x14    /* Inbound message 1 */
   74 #define MFI_OMSG0       0x18    /* Outbound message 0 */
   75 #define MFI_OMSG1       0x1c    /* Outbound message 1 */
   76 #define MFI_IDB         0x20    /* Inbound doorbell */
   77 #define MFI_ISTS        0x24    /* Inbound interrupt status */
   78 #define MFI_IMSK        0x28    /* Inbound interrupt mask */
   79 #define MFI_ODB         0x2c    /* Outbound doorbell */
   80 #define MFI_OSTS        0x30    /* Outbound interrupt status */
   81 #define MFI_OMSK        0x34    /* Outbound interrupt mask */
   82 #define MFI_IQP         0x40    /* Inbound queue port */
   83 #define MFI_OQP         0x44    /* Outbound queue port */
   84 
   85 /*
   86 *  ThunderBolt specific Register
   87 */
   88 
   89 #define MFI_RFPI        0x48            /* reply_free_post_host_index */
   90 #define MFI_RPI         0x6c            /* reply_post_host_index */
   91 #define MFI_ILQP        0xc0            /* inbound_low_queue_port */
   92 #define MFI_IHQP        0xc4            /* inbound_high_queue_port */
   93 
   94 /*
   95  * 1078 specific related register
   96  */
   97 #define MFI_ODR0        0x9c            /* outbound doorbell register0 */
   98 #define MFI_ODCR0       0xa0            /* outbound doorbell clear register0  */
   99 #define MFI_OSP0        0xb0            /* outbound scratch pad0  */
  100 #define MFI_1078_EIM    0x80000004      /* 1078 enable intrrupt mask  */
  101 #define MFI_RMI         0x2             /* reply message interrupt  */
  102 #define MFI_1078_RM     0x80000000      /* reply 1078 message interrupt  */
  103 #define MFI_ODC         0x4             /* outbound doorbell change interrupt */
  104 
  105 /* OCR registers */
  106 #define MFI_WSR         0x004           /* write sequence register */
  107 #define MFI_HDR         0x008           /* host diagnostic register */
  108 #define MFI_RSR         0x3c3           /* Reset Status Register */
  109 
  110 /*
  111  * GEN2 specific changes
  112  */
  113 #define MFI_GEN2_EIM    0x00000005      /* GEN2 enable interrupt mask */
  114 #define MFI_GEN2_RM     0x00000001      /* reply GEN2 message interrupt */
  115 
  116 /*
  117  * skinny specific changes
  118  */
  119 #define MFI_SKINNY_IDB  0x00    /* Inbound doorbell is at 0x00 for skinny */
  120 #define MFI_IQPL        0x000000c0
  121 #define MFI_IQPH        0x000000c4
  122 #define MFI_SKINNY_RM   0x00000001      /* reply skinny message interrupt */
  123 
  124 /* Bits for MFI_OSTS */
  125 #define MFI_OSTS_INTR_VALID     0x00000002
  126 
  127 /* OCR specific flags */
  128 #define MFI_FIRMWARE_STATE_CHANGE       0x00000002
  129 #define MFI_STATE_CHANGE_INTERRUPT      0x00000004  /* MFI state change interrrupt */
  130 
  131 /*
  132  * Firmware state values.  Found in OMSG0 during initialization.
  133  */
  134 #define MFI_FWSTATE_MASK                0xf0000000
  135 #define MFI_FWSTATE_UNDEFINED           0x00000000
  136 #define MFI_FWSTATE_BB_INIT             0x10000000
  137 #define MFI_FWSTATE_FW_INIT             0x40000000
  138 #define MFI_FWSTATE_WAIT_HANDSHAKE      0x60000000
  139 #define MFI_FWSTATE_FW_INIT_2           0x70000000
  140 #define MFI_FWSTATE_DEVICE_SCAN         0x80000000
  141 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING        0x90000000
  142 #define MFI_FWSTATE_FLUSH_CACHE         0xa0000000
  143 #define MFI_FWSTATE_READY               0xb0000000
  144 #define MFI_FWSTATE_OPERATIONAL         0xc0000000
  145 #define MFI_FWSTATE_FAULT               0xf0000000
  146 #define MFI_FWSTATE_MAXSGL_MASK         0x00ff0000
  147 #define MFI_FWSTATE_MAXCMD_MASK         0x0000ffff
  148 #define MFI_FWSTATE_HOSTMEMREQD_MASK    0x08000000
  149 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING        0x90000000
  150 #define MFI_RESET_REQUIRED              0x00000001
  151 
  152 /* ThunderBolt Support */
  153 #define MFI_FWSTATE_TB_MASK             0xf0000000
  154 #define MFI_FWSTATE_TB_RESET            0x00000000
  155 #define MFI_FWSTATE_TB_READY            0x10000000
  156 #define MFI_FWSTATE_TB_OPERATIONAL      0x20000000
  157 #define MFI_FWSTATE_TB_FAULT            0x40000000
  158 
  159 /*
  160  * Control bits to drive the card to ready state.  These go into the IDB
  161  * register.
  162  */
  163 #define MFI_FWINIT_ABORT        0x00000000 /* Abort all pending commands */
  164 #define MFI_FWINIT_READY        0x00000002 /* Move from operational to ready */
  165 #define MFI_FWINIT_MFIMODE      0x00000004 /* unknown */
  166 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
  167 #define MFI_FWINIT_HOTPLUG      0x00000010
  168 
  169 /* ADP reset flags */
  170 #define MFI_STOP_ADP            0x00000020
  171 #define MFI_ADP_RESET           0x00000040
  172 #define DIAG_WRITE_ENABLE       0x00000080
  173 #define DIAG_RESET_ADAPTER      0x00000004
  174 
  175 /* MFI Commands */
  176 typedef enum {
  177         MFI_CMD_INIT =          0x00,
  178         MFI_CMD_LD_READ,
  179         MFI_CMD_LD_WRITE,
  180         MFI_CMD_LD_SCSI_IO,
  181         MFI_CMD_PD_SCSI_IO,
  182         MFI_CMD_DCMD,
  183         MFI_CMD_ABORT,
  184         MFI_CMD_SMP,
  185         MFI_CMD_STP
  186 } mfi_cmd_t;
  187 
  188 /* Direct commands */
  189 typedef enum {
  190         MFI_DCMD_CTRL_GETINFO =         0x01010000,
  191         MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100,
  192         MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
  193         MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
  194         MFI_DCMD_CTRL_FLUSHCACHE =      0x01101000,
  195         MFI_DCMD_CTRL_SHUTDOWN =        0x01050000,
  196         MFI_DCMD_CTRL_EVENT_GETINFO =   0x01040100,
  197         MFI_DCMD_CTRL_EVENT_GET =       0x01040300,
  198         MFI_DCMD_CTRL_EVENT_WAIT =      0x01040500,
  199         MFI_DCMD_PR_GET_STATUS =        0x01070100,
  200         MFI_DCMD_PR_GET_PROPERTIES =    0x01070200,
  201         MFI_DCMD_PR_SET_PROPERTIES =    0x01070300,
  202         MFI_DCMD_PR_START =             0x01070400,
  203         MFI_DCMD_PR_STOP =              0x01070500,
  204         MFI_DCMD_TIME_SECS_GET =        0x01080201,
  205         MFI_DCMD_FLASH_FW_OPEN =        0x010f0100,
  206         MFI_DCMD_FLASH_FW_DOWNLOAD =    0x010f0200,
  207         MFI_DCMD_FLASH_FW_FLASH =       0x010f0300,
  208         MFI_DCMD_FLASH_FW_CLOSE =       0x010f0400,
  209         MFI_DCMD_PD_GET_LIST =          0x02010000,
  210         MFI_DCMD_PD_LIST_QUERY =        0x02010100,
  211         MFI_DCMD_PD_GET_INFO =          0x02020000,
  212         MFI_DCMD_PD_STATE_SET =         0x02030100,
  213         MFI_DCMD_PD_REBUILD_START =     0x02040100,
  214         MFI_DCMD_PD_REBUILD_ABORT =     0x02040200,
  215         MFI_DCMD_PD_CLEAR_START =       0x02050100,
  216         MFI_DCMD_PD_CLEAR_ABORT =       0x02050200,
  217         MFI_DCMD_PD_GET_PROGRESS =      0x02060000,
  218         MFI_DCMD_PD_LOCATE_START =      0x02070100,
  219         MFI_DCMD_PD_LOCATE_STOP =       0x02070200,
  220         MFI_DCMD_LD_MAP_GET_INFO =      0x0300e101,
  221         MFI_DCMD_LD_SYNC =              0x0300e102,
  222         MFI_DCMD_LD_GET_LIST =          0x03010000,
  223         MFI_DCMD_LD_GET_INFO =          0x03020000,
  224         MFI_DCMD_LD_GET_PROP =          0x03030000,
  225         MFI_DCMD_LD_SET_PROP =          0x03040000,
  226         MFI_DCMD_LD_INIT_START =        0x03060100,
  227         MFI_DCMD_LD_DELETE =            0x03090000,
  228         MFI_DCMD_CFG_READ =             0x04010000,
  229         MFI_DCMD_CFG_ADD =              0x04020000,
  230         MFI_DCMD_CFG_CLEAR =            0x04030000,
  231         MFI_DCMD_CFG_MAKE_SPARE =       0x04040000,
  232         MFI_DCMD_CFG_REMOVE_SPARE =     0x04050000,
  233         MFI_DCMD_CFG_FOREIGN_SCAN =     0x04060100,
  234         MFI_DCMD_CFG_FOREIGN_DISPLAY =  0x04060200,
  235         MFI_DCMD_CFG_FOREIGN_PREVIEW =  0x04060300,
  236         MFI_DCMD_CFG_FOREIGN_IMPORT =   0x04060400,
  237         MFI_DCMD_CFG_FOREIGN_CLEAR =    0x04060500,
  238         MFI_DCMD_BBU_GET_STATUS =       0x05010000,
  239         MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000,
  240         MFI_DCMD_BBU_GET_DESIGN_INFO =  0x05030000,
  241         MFI_DCMD_BBU_START_LEARN =      0x05040000,
  242         MFI_DCMD_BBU_GET_PROP =         0x05050100,
  243         MFI_DCMD_BBU_SET_PROP =         0x05050200,
  244         MFI_DCMD_CLUSTER =              0x08000000,
  245         MFI_DCMD_CLUSTER_RESET_ALL =    0x08010100,
  246         MFI_DCMD_CLUSTER_RESET_LD =     0x08010200
  247 } mfi_dcmd_t;
  248 
  249 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
  250 #define MFI_FLUSHCACHE_CTRL     0x01
  251 #define MFI_FLUSHCACHE_DISK     0x02
  252 
  253 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
  254 #define MFI_SHUTDOWN_SPINDOWN   0x01
  255 
  256 /*
  257  * MFI Frame flags
  258  */
  259 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
  260 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
  261 #define MFI_FRAME_SGL32                         0x0000
  262 #define MFI_FRAME_SGL64                         0x0002
  263 #define MFI_FRAME_SENSE32                       0x0000
  264 #define MFI_FRAME_SENSE64                       0x0004
  265 #define MFI_FRAME_DIR_NONE                      0x0000
  266 #define MFI_FRAME_DIR_WRITE                     0x0008
  267 #define MFI_FRAME_DIR_READ                      0x0010
  268 #define MFI_FRAME_DIR_BOTH                      0x0018
  269 #define MFI_FRAME_IEEE_SGL                      0x0020
  270 #define MFI_FRAME_FMT "\2" \
  271     "\1NOPOST" \
  272     "\2SGL64" \
  273     "\3SENSE64" \
  274     "\4WRITE" \
  275     "\5READ" \
  276     "\6IEEESGL"
  277 
  278 /* ThunderBolt Specific */
  279 
  280 /*
  281  * Pre-TB command size and TB command size.
  282  * We will be checking it at the load time for the time being
  283  */
  284 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */
  285 
  286 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT  256
  287 /*
  288  * We are defining only 128 byte message to reduce memory move over head
  289  * and also it will reduce the SRB extension size by 128byte compared with
  290  * 256 message size
  291  */
  292 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE        256
  293 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS        1024
  294 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT     1024
  295 #define MEGASAS_THUNDERBOLT_REPLY_SIZE          8
  296 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT     1
  297 #define MEGASAS_MAX_SZ_CHAIN_FRAME              1024
  298 
  299 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST       0xF0
  300 #define MPI2_FUNCTION_LD_IO_REQUEST             0xF1
  301 
  302 #define MR_INTERNAL_MFI_FRAMES_SMID             1
  303 #define MR_CTRL_EVENT_WAIT_SMID                 2
  304 #define MR_INTERNAL_DRIVER_RESET_SMID           3
  305 
  306 
  307 /* MFI Status codes */
  308 typedef enum {
  309         MFI_STAT_OK =                   0x00,
  310         MFI_STAT_INVALID_CMD,
  311         MFI_STAT_INVALID_DCMD,
  312         MFI_STAT_INVALID_PARAMETER,
  313         MFI_STAT_INVALID_SEQUENCE_NUMBER,
  314         MFI_STAT_ABORT_NOT_POSSIBLE,
  315         MFI_STAT_APP_HOST_CODE_NOT_FOUND,
  316         MFI_STAT_APP_IN_USE,
  317         MFI_STAT_APP_NOT_INITIALIZED,
  318         MFI_STAT_ARRAY_INDEX_INVALID,
  319         MFI_STAT_ARRAY_ROW_NOT_EMPTY,
  320         MFI_STAT_CONFIG_RESOURCE_CONFLICT,
  321         MFI_STAT_DEVICE_NOT_FOUND,
  322         MFI_STAT_DRIVE_TOO_SMALL,
  323         MFI_STAT_FLASH_ALLOC_FAIL,
  324         MFI_STAT_FLASH_BUSY,
  325         MFI_STAT_FLASH_ERROR =          0x10,
  326         MFI_STAT_FLASH_IMAGE_BAD,
  327         MFI_STAT_FLASH_IMAGE_INCOMPLETE,
  328         MFI_STAT_FLASH_NOT_OPEN,
  329         MFI_STAT_FLASH_NOT_STARTED,
  330         MFI_STAT_FLUSH_FAILED,
  331         MFI_STAT_HOST_CODE_NOT_FOUNT,
  332         MFI_STAT_LD_CC_IN_PROGRESS,
  333         MFI_STAT_LD_INIT_IN_PROGRESS,
  334         MFI_STAT_LD_LBA_OUT_OF_RANGE,
  335         MFI_STAT_LD_MAX_CONFIGURED,
  336         MFI_STAT_LD_NOT_OPTIMAL,
  337         MFI_STAT_LD_RBLD_IN_PROGRESS,
  338         MFI_STAT_LD_RECON_IN_PROGRESS,
  339         MFI_STAT_LD_WRONG_RAID_LEVEL,
  340         MFI_STAT_MAX_SPARES_EXCEEDED,
  341         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
  342         MFI_STAT_MFC_HW_ERROR,
  343         MFI_STAT_NO_HW_PRESENT,
  344         MFI_STAT_NOT_FOUND,
  345         MFI_STAT_NOT_IN_ENCL,
  346         MFI_STAT_PD_CLEAR_IN_PROGRESS,
  347         MFI_STAT_PD_TYPE_WRONG,
  348         MFI_STAT_PR_DISABLED,
  349         MFI_STAT_ROW_INDEX_INVALID,
  350         MFI_STAT_SAS_CONFIG_INVALID_ACTION,
  351         MFI_STAT_SAS_CONFIG_INVALID_DATA,
  352         MFI_STAT_SAS_CONFIG_INVALID_PAGE,
  353         MFI_STAT_SAS_CONFIG_INVALID_TYPE,
  354         MFI_STAT_SCSI_DONE_WITH_ERROR,
  355         MFI_STAT_SCSI_IO_FAILED,
  356         MFI_STAT_SCSI_RESERVATION_CONFLICT,
  357         MFI_STAT_SHUTDOWN_FAILED =      0x30,
  358         MFI_STAT_TIME_NOT_SET,
  359         MFI_STAT_WRONG_STATE,
  360         MFI_STAT_LD_OFFLINE,
  361         MFI_STAT_PEER_NOTIFICATION_REJECTED,
  362         MFI_STAT_PEER_NOTIFICATION_FAILED,
  363         MFI_STAT_RESERVATION_IN_PROGRESS,
  364         MFI_STAT_I2C_ERRORS_DETECTED,
  365         MFI_STAT_PCI_ERRORS_DETECTED,
  366         MFI_STAT_DIAG_FAILED,
  367         MFI_STAT_BOOT_MSG_PENDING,
  368         MFI_STAT_FOREIGN_CONFIG_INCOMPLETE,
  369         MFI_STAT_INVALID_STATUS =       0xFF
  370 } mfi_status_t;
  371 
  372 typedef enum {
  373         MFI_EVT_CLASS_DEBUG =           -2,
  374         MFI_EVT_CLASS_PROGRESS =        -1,
  375         MFI_EVT_CLASS_INFO =            0,
  376         MFI_EVT_CLASS_WARNING =         1,
  377         MFI_EVT_CLASS_CRITICAL =        2,
  378         MFI_EVT_CLASS_FATAL =           3,
  379         MFI_EVT_CLASS_DEAD =            4
  380 } mfi_evt_class_t;
  381 
  382 typedef enum {
  383         MFI_EVT_LOCALE_LD =             0x0001,
  384         MFI_EVT_LOCALE_PD =             0x0002,
  385         MFI_EVT_LOCALE_ENCL =           0x0004,
  386         MFI_EVT_LOCALE_BBU =            0x0008,
  387         MFI_EVT_LOCALE_SAS =            0x0010,
  388         MFI_EVT_LOCALE_CTRL =           0x0020,
  389         MFI_EVT_LOCALE_CONFIG =         0x0040,
  390         MFI_EVT_LOCALE_CLUSTER =        0x0080,
  391         MFI_EVT_LOCALE_ALL =            0xffff
  392 } mfi_evt_locale_t;
  393 
  394 typedef enum {
  395         MR_EVT_ARGS_NONE =              0x00,
  396         MR_EVT_ARGS_CDB_SENSE,
  397         MR_EVT_ARGS_LD,
  398         MR_EVT_ARGS_LD_COUNT,
  399         MR_EVT_ARGS_LD_LBA,
  400         MR_EVT_ARGS_LD_OWNER,
  401         MR_EVT_ARGS_LD_LBA_PD_LBA,
  402         MR_EVT_ARGS_LD_PROG,
  403         MR_EVT_ARGS_LD_STATE,
  404         MR_EVT_ARGS_LD_STRIP,
  405         MR_EVT_ARGS_PD,
  406         MR_EVT_ARGS_PD_ERR,
  407         MR_EVT_ARGS_PD_LBA,
  408         MR_EVT_ARGS_PD_LBA_LD,
  409         MR_EVT_ARGS_PD_PROG,
  410         MR_EVT_ARGS_PD_STATE,
  411         MR_EVT_ARGS_PCI,
  412         MR_EVT_ARGS_RATE,
  413         MR_EVT_ARGS_STR,
  414         MR_EVT_ARGS_TIME,
  415         MR_EVT_ARGS_ECC
  416 } mfi_evt_args;
  417 
  418 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED     0x0152
  419 #define MR_EVT_PD_REMOVED                       0x0070
  420 #define MR_EVT_PD_INSERTED                      0x005b
  421 #define MR_EVT_LD_CHANGE                        0x0051
  422 
  423 typedef enum {
  424         MR_LD_CACHE_WRITE_BACK =        0x01,
  425         MR_LD_CACHE_WRITE_ADAPTIVE =    0x02,
  426         MR_LD_CACHE_READ_AHEAD =        0x04,
  427         MR_LD_CACHE_READ_ADAPTIVE =     0x08,
  428         MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
  429         MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
  430         MR_LD_CACHE_ALLOW_READ_CACHE =  0x40
  431 } mfi_ld_cache;
  432 #define MR_LD_CACHE_MASK        0x7f
  433 
  434 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE              0
  435 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS            MR_LD_CACHE_READ_AHEAD
  436 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE          \
  437         (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE)
  438 #define MR_LD_CACHE_POLICY_WRITE_THROUGH                0
  439 #define MR_LD_CACHE_POLICY_WRITE_BACK                   MR_LD_CACHE_WRITE_BACK
  440 #define MR_LD_CACHE_POLICY_IO_CACHED                    \
  441         (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE)
  442 #define MR_LD_CACHE_POLICY_IO_DIRECT                    0
  443 
  444 typedef enum {
  445         MR_PD_CACHE_UNCHANGED  =        0,
  446         MR_PD_CACHE_ENABLE =            1,
  447         MR_PD_CACHE_DISABLE =           2
  448 } mfi_pd_cache;
  449 
  450 typedef enum {
  451         MR_PD_QUERY_TYPE_ALL =          0,
  452         MR_PD_QUERY_TYPE_STATE =        1,
  453         MR_PD_QUERY_TYPE_POWER_STATE =  2,
  454         MR_PD_QUERY_TYPE_MEDIA_TYPE =   3,
  455         MR_PD_QUERY_TYPE_SPEED =        4,
  456         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */
  457 } mfi_pd_query_type;
  458 
  459 /*
  460  * Other propertities and definitions
  461  */
  462 #define MFI_MAX_PD_CHANNELS     2
  463 #define MFI_MAX_LD_CHANNELS     2
  464 #define MFI_MAX_CHANNELS        (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
  465 #define MFI_MAX_CHANNEL_DEVS    128
  466 #define MFI_DEFAULT_ID          -1
  467 #define MFI_MAX_LUN             8
  468 #define MFI_MAX_LD              64
  469 #define MFI_MAX_PD              256
  470 
  471 #define MFI_FRAME_SIZE          64
  472 #define MFI_MBOX_SIZE           12
  473 
  474 /* Firmware flashing can take 50+ seconds */
  475 #define MFI_POLL_TIMEOUT_SECS   60
  476 
  477 /* Allow for speedier math calculations */
  478 #define MFI_SECTOR_LEN          512
  479 
  480 /* Scatter Gather elements */
  481 struct mfi_sg32 {
  482         uint32_t        addr;
  483         uint32_t        len;
  484 } __packed;
  485 
  486 struct mfi_sg64 {
  487         uint64_t        addr;
  488         uint32_t        len;
  489 } __packed;
  490 
  491 struct mfi_sg_skinny {
  492         uint64_t        addr;
  493         uint32_t        len;
  494         uint32_t        flag;
  495 } __packed;
  496 
  497 union mfi_sgl {
  498         struct mfi_sg32         sg32[1];
  499         struct mfi_sg64         sg64[1];
  500         struct mfi_sg_skinny    sg_skinny[1];
  501 } __packed;
  502 
  503 /* Message frames.  All messages have a common header */
  504 struct mfi_frame_header {
  505         uint8_t         cmd;
  506         uint8_t         sense_len;
  507         uint8_t         cmd_status;
  508         uint8_t         scsi_status;
  509         uint8_t         target_id;
  510         uint8_t         lun_id;
  511         uint8_t         cdb_len;
  512         uint8_t         sg_count;
  513         uint32_t        context;
  514         /*
  515          * pad0 is MSI Specific. Not used by Driver. Zero the value before
  516          * sending the command to f/w.
  517          */
  518         uint32_t        pad0;
  519         uint16_t        flags;
  520 #define MFI_FRAME_DATAOUT       0x08
  521 #define MFI_FRAME_DATAIN        0x10
  522         uint16_t        timeout;
  523         uint32_t        data_len;
  524 } __packed;
  525 
  526 struct mfi_init_frame {
  527         struct mfi_frame_header header;
  528         uint32_t        qinfo_new_addr_lo;
  529         uint32_t        qinfo_new_addr_hi;
  530         uint32_t        qinfo_old_addr_lo;
  531         uint32_t        qinfo_old_addr_hi;
  532         // Start LSIP200113393
  533         uint32_t        driver_ver_lo;      /*28h */
  534         uint32_t        driver_ver_hi;      /*2Ch */
  535 
  536         uint32_t        reserved[4];
  537         // End LSIP200113393
  538 } __packed;
  539 
  540 /*
  541  * Define MFI Address Context union.
  542  */
  543 #ifdef MFI_ADDRESS_IS_uint64_t
  544     typedef uint64_t     MFI_ADDRESS;
  545 #else
  546     typedef union _MFI_ADDRESS {
  547         struct {
  548             uint32_t     addressLow;
  549             uint32_t     addressHigh;
  550         } u;
  551         uint64_t     address;
  552     } MFI_ADDRESS, *PMFI_ADDRESS;
  553 #endif
  554 
  555 #define MFI_IO_FRAME_SIZE 40
  556 struct mfi_io_frame {
  557         struct mfi_frame_header header;
  558         uint32_t        sense_addr_lo;
  559         uint32_t        sense_addr_hi;
  560         uint32_t        lba_lo;
  561         uint32_t        lba_hi;
  562         union mfi_sgl   sgl;
  563 } __packed;
  564 
  565 #define MFI_PASS_FRAME_SIZE 48
  566 struct mfi_pass_frame {
  567         struct mfi_frame_header header;
  568         uint32_t        sense_addr_lo;
  569         uint32_t        sense_addr_hi;
  570         uint8_t         cdb[16];
  571         union mfi_sgl   sgl;
  572 } __packed;
  573 
  574 #define MFI_DCMD_FRAME_SIZE 40
  575 struct mfi_dcmd_frame {
  576         struct mfi_frame_header header;
  577         uint32_t        opcode;
  578         uint8_t         mbox[MFI_MBOX_SIZE];
  579         union mfi_sgl   sgl;
  580 } __packed;
  581 
  582 struct mfi_abort_frame {
  583         struct mfi_frame_header header;
  584         uint32_t        abort_context;
  585         /* pad is changed to reserved.*/
  586         uint32_t        reserved0;
  587         uint32_t        abort_mfi_addr_lo;
  588         uint32_t        abort_mfi_addr_hi;
  589         uint32_t        reserved1[6];
  590 } __packed;
  591 
  592 struct mfi_smp_frame {
  593         struct mfi_frame_header header;
  594         uint64_t        sas_addr;
  595         union {
  596                 struct mfi_sg32 sg32[2];
  597                 struct mfi_sg64 sg64[2];
  598         } sgl;
  599 } __packed;
  600 
  601 struct mfi_stp_frame {
  602         struct mfi_frame_header header;
  603         uint16_t        fis[10];
  604         uint32_t        stp_flags;
  605         union {
  606                 struct mfi_sg32 sg32[2];
  607                 struct mfi_sg64 sg64[2];
  608         } sgl;
  609 } __packed;
  610 
  611 union mfi_frame {
  612         struct mfi_frame_header header;
  613         struct mfi_init_frame   init;
  614         /* ThunderBolt Initialization */
  615         struct mfi_io_frame     io;
  616         struct mfi_pass_frame   pass;
  617         struct mfi_dcmd_frame   dcmd;
  618         struct mfi_abort_frame  abort;
  619         struct mfi_smp_frame    smp;
  620         struct mfi_stp_frame    stp;
  621         uint8_t                 bytes[MFI_FRAME_SIZE];
  622 };
  623 
  624 #define MFI_SENSE_LEN 128
  625 struct mfi_sense {
  626         uint8_t         data[MFI_SENSE_LEN];
  627 };
  628 
  629 /* The queue init structure that is passed with the init message */
  630 struct mfi_init_qinfo {
  631         uint32_t        flags;
  632         uint32_t        rq_entries;
  633         uint32_t        rq_addr_lo;
  634         uint32_t        rq_addr_hi;
  635         uint32_t        pi_addr_lo;
  636         uint32_t        pi_addr_hi;
  637         uint32_t        ci_addr_lo;
  638         uint32_t        ci_addr_hi;
  639 } __packed;
  640 
  641 /* SAS (?) controller properties, part of mfi_ctrl_info */
  642 struct mfi_ctrl_props {
  643         uint16_t        seq_num;
  644         uint16_t        pred_fail_poll_interval;
  645         uint16_t        intr_throttle_cnt;
  646         uint16_t        intr_throttle_timeout;
  647         uint8_t         rebuild_rate;
  648         uint8_t         patrol_read_rate;
  649         uint8_t         bgi_rate;
  650         uint8_t         cc_rate;
  651         uint8_t         recon_rate;
  652         uint8_t         cache_flush_interval;
  653         uint8_t         spinup_drv_cnt;
  654         uint8_t         spinup_delay;
  655         uint8_t         cluster_enable;
  656         uint8_t         coercion_mode;
  657         uint8_t         alarm_enable;
  658         uint8_t         disable_auto_rebuild;
  659         uint8_t         disable_battery_warn;
  660         uint8_t         ecc_bucket_size;
  661         uint16_t        ecc_bucket_leak_rate;
  662         uint8_t         restore_hotspare_on_insertion;
  663         uint8_t         expose_encl_devices;
  664         uint8_t         maintainPdFailHistory;
  665         uint8_t         disallowHostRequestReordering;
  666         /* set TRUE to abort CC on detecting an inconsistency */
  667         uint8_t         abortCCOnError;
  668         /* load balance mode (MR_LOAD_BALANCE_MODE) */
  669         uint8_t         loadBalanceMode;
  670         /*
  671          * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using
  672          *     h/w mechansim like GPIO pins
  673          * 1 - disable auto detect SGPIO,
  674          * 2 - disable i2c SEP auto detect
  675          * 3 - disable both auto detect
  676          */
  677         uint8_t         disableAutoDetectBackplane;
  678         /*
  679          * % of source LD to be reserved for a VDs snapshot in snapshot
  680          * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on
  681          */
  682         uint8_t         snapVDSpace;
  683 
  684         /*
  685          * Add properties that can be controlled by a bit in the following
  686          * structure.
  687          */
  688         struct {
  689                 /* set TRUE to disable copyBack (0=copback enabled) */
  690                 uint32_t        copyBackDisabled                :1;
  691                 uint32_t        SMARTerEnabled                  :1;
  692                 uint32_t        prCorrectUnconfiguredAreas      :1;
  693                 uint32_t        useFdeOnly                      :1;
  694                 uint32_t        disableNCQ                      :1;
  695                 uint32_t        SSDSMARTerEnabled               :1;
  696                 uint32_t        SSDPatrolReadEnabled            :1;
  697                 uint32_t        enableSpinDownUnconfigured      :1;
  698                 uint32_t        autoEnhancedImport              :1;
  699                 uint32_t        enableSecretKeyControl          :1;
  700                 uint32_t        disableOnlineCtrlReset          :1;
  701                 uint32_t        allowBootWithPinnedCache        :1;
  702                 uint32_t        disableSpinDownHS               :1;
  703                 uint32_t        enableJBOD                      :1;
  704                 uint32_t        reserved                        :18;
  705         } OnOffProperties;
  706         /*
  707          * % of source LD to be reserved for auto snapshot in snapshot
  708          * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on.
  709          */
  710         uint8_t         autoSnapVDSpace;
  711         /*
  712          * Snapshot writeable VIEWs capacity as a % of source LD capacity:
  713          * 0=READ only, 1=5%, 2=10%, 3=15% and so on.
  714          */
  715         uint8_t         viewSpace;
  716         /* # of idle minutes before device is spun down (0=use FW defaults) */
  717         uint16_t        spinDownTime;
  718         uint8_t         reserved[24];
  719 } __packed;
  720 
  721 /* PCI information about the card. */
  722 struct mfi_info_pci {
  723         uint16_t        vendor;
  724         uint16_t        device;
  725         uint16_t        subvendor;
  726         uint16_t        subdevice;
  727         uint8_t         reserved[24];
  728 } __packed;
  729 
  730 /* Host (front end) interface information */
  731 struct mfi_info_host {
  732         uint8_t         type;
  733 #define MFI_INFO_HOST_PCIX      0x01
  734 #define MFI_INFO_HOST_PCIE      0x02
  735 #define MFI_INFO_HOST_ISCSI     0x04
  736 #define MFI_INFO_HOST_SAS3G     0x08
  737         uint8_t         reserved[6];
  738         uint8_t         port_count;
  739         uint64_t        port_addr[8];
  740 } __packed;
  741 
  742 /* Device (back end) interface information */
  743 struct mfi_info_device {
  744         uint8_t         type;
  745 #define MFI_INFO_DEV_SPI        0x01
  746 #define MFI_INFO_DEV_SAS3G      0x02
  747 #define MFI_INFO_DEV_SATA1      0x04
  748 #define MFI_INFO_DEV_SATA3G     0x08
  749         uint8_t         reserved[6];
  750         uint8_t         port_count;
  751         uint64_t        port_addr[8];
  752 } __packed;
  753 
  754 /* Firmware component information */
  755 struct mfi_info_component {
  756         char             name[8];
  757         char             version[32];
  758         char             build_date[16];
  759         char             build_time[16];
  760 } __packed;
  761 
  762 /* Controller default settings */
  763 struct mfi_defaults {
  764         uint64_t        sas_addr;
  765         uint8_t         phy_polarity;
  766         uint8_t         background_rate;
  767         uint8_t         stripe_size;
  768         uint8_t         flush_time;
  769         uint8_t         write_back;
  770         uint8_t         read_ahead;
  771         uint8_t         cache_when_bbu_bad;
  772         uint8_t         cached_io;
  773         uint8_t         smart_mode;
  774         uint8_t         alarm_disable;
  775         uint8_t         coercion;
  776         uint8_t         zrc_config;
  777         uint8_t         dirty_led_shows_drive_activity;
  778         uint8_t         bios_continue_on_error;
  779         uint8_t         spindown_mode;
  780         uint8_t         allowed_device_types;
  781         uint8_t         allow_mix_in_enclosure;
  782         uint8_t         allow_mix_in_ld;
  783         uint8_t         allow_sata_in_cluster;
  784         uint8_t         max_chained_enclosures;
  785         uint8_t         disable_ctrl_r;
  786         uint8_t         enabel_web_bios;
  787         uint8_t         phy_polarity_split;
  788         uint8_t         direct_pd_mapping;
  789         uint8_t         bios_enumerate_lds;
  790         uint8_t         restored_hot_spare_on_insertion;
  791         uint8_t         expose_enclosure_devices;
  792         uint8_t         maintain_pd_fail_history;
  793         uint8_t         resv[28];
  794 } __packed;
  795 
  796 /* Controller default settings */
  797 struct mfi_bios_data {
  798         uint16_t        boot_target_id;
  799         uint8_t         do_not_int_13;
  800         uint8_t         continue_on_error;
  801         uint8_t         verbose;
  802         uint8_t         geometry;
  803         uint8_t         expose_all_drives;
  804         uint8_t         reserved[56];
  805         uint8_t         check_sum;
  806 } __packed;
  807 
  808 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
  809 struct mfi_ctrl_info {
  810         struct mfi_info_pci     pci;
  811         struct mfi_info_host    host;
  812         struct mfi_info_device  device;
  813 
  814         /* Firmware components that are present and active. */
  815         uint32_t                image_check_word;
  816         uint32_t                image_component_count;
  817         struct mfi_info_component image_component[8];
  818 
  819         /* Firmware components that have been flashed but are inactive */
  820         uint32_t                pending_image_component_count;
  821         struct mfi_info_component pending_image_component[8];
  822 
  823         uint8_t                 max_arms;
  824         uint8_t                 max_spans;
  825         uint8_t                 max_arrays;
  826         uint8_t                 max_lds;
  827         char                    product_name[80];
  828         char                    serial_number[32];
  829         uint32_t                hw_present;
  830 #define MFI_INFO_HW_BBU         0x01
  831 #define MFI_INFO_HW_ALARM       0x02
  832 #define MFI_INFO_HW_NVRAM       0x04
  833 #define MFI_INFO_HW_UART        0x08
  834         uint32_t                current_fw_time;
  835         uint16_t                max_cmds;
  836         uint16_t                max_sg_elements;
  837         uint32_t                max_request_size;
  838         uint16_t                lds_present;
  839         uint16_t                lds_degraded;
  840         uint16_t                lds_offline;
  841         uint16_t                pd_present;
  842         uint16_t                pd_disks_present;
  843         uint16_t                pd_disks_pred_failure;
  844         uint16_t                pd_disks_failed;
  845         uint16_t                nvram_size;
  846         uint16_t                memory_size;
  847         uint16_t                flash_size;
  848         uint16_t                ram_correctable_errors;
  849         uint16_t                ram_uncorrectable_errors;
  850         uint8_t                 cluster_allowed;
  851         uint8_t                 cluster_active;
  852         uint16_t                max_strips_per_io;
  853 
  854         uint32_t                raid_levels;
  855 #define MFI_INFO_RAID_0         0x01
  856 #define MFI_INFO_RAID_1         0x02
  857 #define MFI_INFO_RAID_5         0x04
  858 #define MFI_INFO_RAID_1E        0x08
  859 #define MFI_INFO_RAID_6         0x10
  860 
  861         uint32_t                adapter_ops;
  862 #define MFI_INFO_AOPS_RBLD_RATE         0x0001
  863 #define MFI_INFO_AOPS_CC_RATE           0x0002
  864 #define MFI_INFO_AOPS_BGI_RATE          0x0004
  865 #define MFI_INFO_AOPS_RECON_RATE        0x0008
  866 #define MFI_INFO_AOPS_PATROL_RATE       0x0010
  867 #define MFI_INFO_AOPS_ALARM_CONTROL     0x0020
  868 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
  869 #define MFI_INFO_AOPS_BBU               0x0080
  870 #define MFI_INFO_AOPS_SPANNING_ALLOWED  0x0100
  871 #define MFI_INFO_AOPS_DEDICATED_SPARES  0x0200
  872 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
  873 #define MFI_INFO_AOPS_FOREIGN_IMPORT    0x0800
  874 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC   0x1000
  875 #define MFI_INFO_AOPS_MIXED_ARRAY       0x2000
  876 #define MFI_INFO_AOPS_GLOBAL_SPARES     0x4000
  877 
  878         uint32_t                ld_ops;
  879 #define MFI_INFO_LDOPS_READ_POLICY      0x01
  880 #define MFI_INFO_LDOPS_WRITE_POLICY     0x02
  881 #define MFI_INFO_LDOPS_IO_POLICY        0x04
  882 #define MFI_INFO_LDOPS_ACCESS_POLICY    0x08
  883 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
  884 
  885         struct {
  886                 uint8_t         min;
  887                 uint8_t         max;
  888                 uint8_t         reserved[2];
  889         } __packed stripe_sz_ops;
  890 
  891         uint32_t                pd_ops;
  892 #define MFI_INFO_PDOPS_FORCE_ONLINE     0x01
  893 #define MFI_INFO_PDOPS_FORCE_OFFLINE    0x02
  894 #define MFI_INFO_PDOPS_FORCE_REBUILD    0x04
  895 
  896         uint32_t                pd_mix_support;
  897 #define MFI_INFO_PDMIX_SAS              0x01
  898 #define MFI_INFO_PDMIX_SATA             0x02
  899 #define MFI_INFO_PDMIX_ENCL             0x04
  900 #define MFI_INFO_PDMIX_LD               0x08
  901 #define MFI_INFO_PDMIX_SATA_CLUSTER     0x10
  902 
  903         uint8_t                 ecc_bucket_count;
  904         uint8_t                 reserved2[11];
  905         struct mfi_ctrl_props   properties;
  906         char                    package_version[0x60];
  907         uint8_t                 pad[0x800 - 0x6a0];
  908 } __packed;
  909 
  910 /* keep track of an event. */
  911 union mfi_evt {
  912         struct {
  913                 uint16_t        locale;
  914                 uint8_t         reserved;
  915                 int8_t          evt_class;
  916         } members;
  917         uint32_t                word;
  918 } __packed;
  919 
  920 /* event log state. */
  921 struct mfi_evt_log_state {
  922         uint32_t                newest_seq_num;
  923         uint32_t                oldest_seq_num;
  924         uint32_t                clear_seq_num;
  925         uint32_t                shutdown_seq_num;
  926         uint32_t                boot_seq_num;
  927 } __packed;
  928 
  929 struct mfi_progress {
  930         uint16_t                progress;
  931         uint16_t                elapsed_seconds;
  932 } __packed;
  933 
  934 struct mfi_evt_ld {
  935         uint16_t                target_id;
  936         uint8_t                 ld_index;
  937         uint8_t                 reserved;
  938 } __packed;
  939 
  940 struct mfi_evt_pd {
  941         uint16_t                device_id;
  942         uint8_t                 enclosure_index;
  943         uint8_t                 slot_number;
  944 } __packed;
  945 
  946 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
  947 struct mfi_evt_detail {
  948         uint32_t                seq;
  949         uint32_t                time;
  950         uint32_t                code;
  951         union mfi_evt           evt_class;
  952         uint8_t                 arg_type;
  953         uint8_t                 reserved1[15];
  954 
  955         union {
  956                 struct {
  957                         struct mfi_evt_pd       pd;
  958                         uint8_t                 cdb_len;
  959                         uint8_t                 sense_len;
  960                         uint8_t                 reserved[2];
  961                         uint8_t                 cdb[16];
  962                         uint8_t                 sense[64];
  963                 } cdb_sense;
  964 
  965                 struct mfi_evt_ld               ld;
  966 
  967                 struct {
  968                         struct mfi_evt_ld       ld;
  969                         uint64_t                count;
  970                 } ld_count;
  971 
  972                 struct {
  973                         uint64_t                lba;
  974                         struct mfi_evt_ld       ld;
  975                 } ld_lba;
  976 
  977                 struct {
  978                         struct mfi_evt_ld       ld;
  979                         uint32_t                pre_owner;
  980                         uint32_t                new_owner;
  981                 } ld_owner;
  982 
  983                 struct {
  984                         uint64_t                ld_lba;
  985                         uint64_t                pd_lba;
  986                         struct mfi_evt_ld       ld;
  987                         struct mfi_evt_pd       pd;
  988                 } ld_lba_pd_lba;
  989 
  990                 struct {
  991                         struct mfi_evt_ld       ld;
  992                         struct mfi_progress     prog;
  993                 } ld_prog;
  994 
  995                 struct {
  996                         struct mfi_evt_ld       ld;
  997                         uint32_t                prev_state;
  998                         uint32_t                new_state;
  999                 } ld_state;
 1000 
 1001                 struct {
 1002                         uint64_t                strip;
 1003                         struct mfi_evt_ld       ld;
 1004                 } ld_strip;
 1005 
 1006                 struct mfi_evt_pd               pd;
 1007 
 1008                 struct {
 1009                         struct mfi_evt_pd       pd;
 1010                         uint32_t                err;
 1011                 } pd_err;
 1012 
 1013                 struct {
 1014                         uint64_t                lba;
 1015                         struct mfi_evt_pd       pd;
 1016                 } pd_lba;
 1017 
 1018                 struct {
 1019                         uint64_t                lba;
 1020                         struct mfi_evt_pd       pd;
 1021                         struct mfi_evt_ld       ld;
 1022                 } pd_lba_ld;
 1023 
 1024                 struct {
 1025                         struct mfi_evt_pd       pd;
 1026                         struct mfi_progress     prog;
 1027                 } pd_prog;
 1028 
 1029                 struct {
 1030                         struct mfi_evt_pd       ld;
 1031                         uint32_t                prev_state;
 1032                         uint32_t                new_state;
 1033                 } pd_state;
 1034 
 1035                 struct {
 1036                         uint16_t                venderId;
 1037                         uint16_t                deviceId;
 1038                         uint16_t                subVenderId;
 1039                         uint16_t                subDeviceId;
 1040                 } pci;
 1041 
 1042                 uint32_t                        rate;
 1043 
 1044                 char                            str[96];
 1045 
 1046                 struct {
 1047                         uint32_t                rtc;
 1048                         uint16_t                elapsedSeconds;
 1049                 } time;
 1050 
 1051                 struct {
 1052                         uint32_t                ecar;
 1053                         uint32_t                elog;
 1054                         char                    str[64];
 1055                 } ecc;
 1056 
 1057                 uint8_t         b[96];
 1058                 uint16_t        s[48];
 1059                 uint32_t        w[24];
 1060                 uint64_t        d[12];
 1061         } args;
 1062 
 1063         char description[128];
 1064 } __packed;
 1065 
 1066 struct mfi_evt_list {
 1067         uint32_t                count;
 1068         uint32_t                reserved;
 1069         struct mfi_evt_detail   event[1];
 1070 } __packed;
 1071 
 1072 union mfi_pd_ref {
 1073         struct {
 1074                 uint16_t        device_id;
 1075                 uint16_t        seq_num;
 1076         } v;
 1077         uint32_t        ref;
 1078 } __packed;
 1079 
 1080 union mfi_pd_ddf_type {
 1081         struct {
 1082                 union {
 1083                         struct {
 1084                                 uint16_t        forced_pd_guid  : 1;
 1085                                 uint16_t        in_vd           : 1;
 1086                                 uint16_t        is_global_spare : 1;
 1087                                 uint16_t        is_spare        : 1;
 1088                                 uint16_t        is_foreign      : 1;
 1089                                 uint16_t        reserved        : 7;
 1090                                 uint16_t        intf            : 4;
 1091                         } pd_type;
 1092                         uint16_t        type;
 1093                 } v;
 1094                 uint16_t                reserved;
 1095         } ddf;
 1096         struct {
 1097                 uint32_t                reserved;
 1098         } non_disk;
 1099         uint32_t                        type;
 1100 } __packed;
 1101 
 1102 struct mfi_pd_progress {
 1103         uint32_t                        active;
 1104 #define MFI_PD_PROGRESS_REBUILD (1<<0)
 1105 #define MFI_PD_PROGRESS_PATROL  (1<<1)
 1106 #define MFI_PD_PROGRESS_CLEAR   (1<<2)
 1107         struct mfi_progress             rbld;
 1108         struct mfi_progress             patrol;
 1109         struct mfi_progress             clear;
 1110         struct mfi_progress             reserved[4];
 1111 } __packed;
 1112 
 1113 struct mfi_pd_info {
 1114         union mfi_pd_ref                ref;
 1115         uint8_t                         inquiry_data[96];
 1116         uint8_t                         vpd_page83[64];
 1117         uint8_t                         not_supported;
 1118         uint8_t                         scsi_dev_type;
 1119         uint8_t                         connected_port_bitmap;
 1120         uint8_t                         device_speed;
 1121         uint32_t                        media_err_count;
 1122         uint32_t                        other_err_count;
 1123         uint32_t                        pred_fail_count;
 1124         uint32_t                        last_pred_fail_event_seq_num;
 1125         uint16_t                        fw_state;       /* MFI_PD_STATE_* */
 1126         uint8_t                         disabled_for_removal;
 1127         uint8_t                         link_speed;
 1128         union mfi_pd_ddf_type           state;
 1129         struct {
 1130                 uint8_t                 count;
 1131                 uint8_t                 is_path_broken;
 1132                 uint8_t                 reserved[6];
 1133                 uint64_t                sas_addr[4];
 1134         } path_info;
 1135         uint64_t                        raw_size;
 1136         uint64_t                        non_coerced_size;
 1137         uint64_t                        coerced_size;
 1138         uint16_t                        encl_device_id;
 1139         uint8_t                         encl_index;
 1140         uint8_t                         slot_number;
 1141         struct mfi_pd_progress          prog_info;
 1142         uint8_t                         bad_block_table_full;
 1143         uint8_t                         unusable_in_current_config;
 1144         uint8_t                         vpd_page83_ext[64];
 1145         uint8_t                         reserved[512-358];
 1146 } __packed;
 1147 
 1148 struct mfi_pd_address {
 1149         uint16_t                device_id;
 1150         uint16_t                encl_device_id;
 1151         uint8_t                 encl_index;
 1152         uint8_t                 slot_number;
 1153         uint8_t                 scsi_dev_type;  /* 0 = disk */
 1154         uint8_t                 connect_port_bitmap;
 1155         uint64_t                sas_addr[2];
 1156 } __packed;
 1157 
 1158 #define MAX_SYS_PDS 240
 1159 struct mfi_pd_list {
 1160         uint32_t                size;
 1161         uint32_t                count;
 1162         struct mfi_pd_address   addr[MAX_SYS_PDS];
 1163 } __packed;
 1164 
 1165 enum mfi_pd_state {
 1166         MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
 1167         MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
 1168         MFI_PD_STATE_HOT_SPARE = 0x02,
 1169         MFI_PD_STATE_OFFLINE = 0x10,
 1170         MFI_PD_STATE_FAILED = 0x11,
 1171         MFI_PD_STATE_REBUILD = 0x14,
 1172         MFI_PD_STATE_ONLINE = 0x18,
 1173         MFI_PD_STATE_COPYBACK = 0x20,
 1174         MFI_PD_STATE_SYSTEM = 0x40
 1175 };
 1176 
 1177 /*
 1178  * "SYSTEM" disk appears to be "JBOD" support from the RAID controller.
 1179  * Adding a #define to denote this.
 1180  */
 1181 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM
 1182 
 1183 union mfi_ld_ref {
 1184         struct {
 1185                 uint8_t         target_id;
 1186                 uint8_t         reserved;
 1187                 uint16_t        seq;
 1188         } v;
 1189         uint32_t                ref;
 1190 } __packed;
 1191 
 1192 struct mfi_ld_list {
 1193         uint32_t                ld_count;
 1194         uint32_t                reserved1;
 1195         struct {
 1196                 union mfi_ld_ref        ld;
 1197                 uint8_t         state;
 1198                 uint8_t         reserved2[3];
 1199                 uint64_t        size;
 1200         } ld_list[MFI_MAX_LD];
 1201 } __packed;
 1202 
 1203 enum mfi_ld_access {
 1204         MFI_LD_ACCESS_RW =      0,
 1205         MFI_LD_ACCSSS_RO =      2,
 1206         MFI_LD_ACCESS_BLOCKED = 3,
 1207 };
 1208 #define MFI_LD_ACCESS_MASK      3
 1209 
 1210 enum mfi_ld_state {
 1211         MFI_LD_STATE_OFFLINE =                  0,
 1212         MFI_LD_STATE_PARTIALLY_DEGRADED =       1,
 1213         MFI_LD_STATE_DEGRADED =                 2,
 1214         MFI_LD_STATE_OPTIMAL =                  3
 1215 };
 1216 
 1217 struct mfi_ld_props {
 1218         union mfi_ld_ref        ld;
 1219         char                    name[16];
 1220         uint8_t                 default_cache_policy;
 1221         uint8_t                 access_policy;
 1222         uint8_t                 disk_cache_policy;
 1223         uint8_t                 current_cache_policy;
 1224         uint8_t                 no_bgi;
 1225         uint8_t                 reserved[7];
 1226 } __packed;
 1227 
 1228 struct mfi_ld_params {
 1229         uint8_t                 primary_raid_level;
 1230         uint8_t                 raid_level_qualifier;
 1231         uint8_t                 secondary_raid_level;
 1232         uint8_t                 stripe_size;
 1233         uint8_t                 num_drives;
 1234         uint8_t                 span_depth;
 1235         uint8_t                 state;
 1236         uint8_t                 init_state;
 1237 #define MFI_LD_PARAMS_INIT_NO           0
 1238 #define MFI_LD_PARAMS_INIT_QUICK        1
 1239 #define MFI_LD_PARAMS_INIT_FULL         2
 1240         uint8_t                 is_consistent;
 1241         uint8_t                 reserved1[6];
 1242         uint8_t                 isSSCD;
 1243         uint8_t                 reserved2[16];
 1244 } __packed;
 1245 
 1246 struct mfi_ld_progress {
 1247         uint32_t                active;
 1248 #define MFI_LD_PROGRESS_CC      (1<<0)
 1249 #define MFI_LD_PROGRESS_BGI     (1<<1)
 1250 #define MFI_LD_PROGRESS_FGI     (1<<2)
 1251 #define MFI_LD_PROGRESS_RECON   (1<<3)
 1252         struct mfi_progress     cc;
 1253         struct mfi_progress     bgi;
 1254         struct mfi_progress     fgi;
 1255         struct mfi_progress     recon;
 1256         struct mfi_progress     reserved[4];
 1257 } __packed;
 1258 
 1259 struct mfi_span {
 1260         uint64_t                start_block;
 1261         uint64_t                num_blocks;
 1262         uint16_t                array_ref;
 1263         uint8_t                 reserved[6];
 1264 } __packed;
 1265 
 1266 #define MFI_MAX_SPAN_DEPTH      8
 1267 struct mfi_ld_config {
 1268         struct mfi_ld_props     properties;
 1269         struct mfi_ld_params    params;
 1270         struct mfi_span         span[MFI_MAX_SPAN_DEPTH];
 1271 } __packed;
 1272 
 1273 struct mfi_ld_info {
 1274         struct mfi_ld_config    ld_config;
 1275         uint64_t                size;
 1276         struct mfi_ld_progress  progress;
 1277         uint16_t                cluster_owner;
 1278         uint8_t                 reconstruct_active;
 1279         uint8_t                 reserved1[1];
 1280         uint8_t                 vpd_page83[64];
 1281         uint8_t                 reserved2[16];
 1282 } __packed;
 1283 
 1284 #define MFI_MAX_ARRAYS 16
 1285 struct mfi_spare {
 1286         union mfi_pd_ref        ref;
 1287         uint8_t                 spare_type;
 1288 #define MFI_SPARE_DEDICATED     (1 << 0)
 1289 #define MFI_SPARE_REVERTIBLE    (1 << 1)
 1290 #define MFI_SPARE_ENCL_AFFINITY (1 << 2)
 1291         uint8_t                 reserved[2];
 1292         uint8_t                 array_count;
 1293         uint16_t                array_ref[MFI_MAX_ARRAYS];
 1294 } __packed;
 1295 
 1296 #define MFI_MAX_ROW_SIZE 32
 1297 struct mfi_array {
 1298         uint64_t                        size;
 1299         uint8_t                         num_drives;
 1300         uint8_t                         reserved;
 1301         uint16_t                        array_ref;
 1302         uint8_t                         pad[20];
 1303         struct {
 1304                 union mfi_pd_ref        ref;    /* 0xffff == missing drive */
 1305                 uint16_t                fw_state;       /* MFI_PD_STATE_* */
 1306                 struct {
 1307                         uint8_t         pd;
 1308                         uint8_t         slot;
 1309                 } encl;
 1310         } pd[MFI_MAX_ROW_SIZE];
 1311 } __packed;
 1312 
 1313 struct mfi_config_data {
 1314         uint32_t                size;
 1315         uint16_t                array_count;
 1316         uint16_t                array_size;
 1317         uint16_t                log_drv_count;
 1318         uint16_t                log_drv_size;
 1319         uint16_t                spares_count;
 1320         uint16_t                spares_size;
 1321         uint8_t                 reserved[16];
 1322         struct mfi_array        array[0];
 1323         struct mfi_ld_config    ld[0];
 1324         struct mfi_spare        spare[0];
 1325 } __packed;
 1326 
 1327 struct mfi_bbu_capacity_info {
 1328         uint16_t                relative_charge;
 1329         uint16_t                absolute_charge;
 1330         uint16_t                remaining_capacity;
 1331         uint16_t                full_charge_capacity;
 1332         uint16_t                run_time_to_empty;
 1333         uint16_t                average_time_to_empty;
 1334         uint16_t                average_time_to_full;
 1335         uint16_t                cycle_count;
 1336         uint16_t                max_error;
 1337         uint16_t                remaining_capacity_alarm;
 1338         uint16_t                remaining_time_alarm;
 1339         uint8_t                 reserved[26];
 1340 } __packed;
 1341 
 1342 struct mfi_bbu_design_info {
 1343         uint32_t                mfg_date;
 1344         uint16_t                design_capacity;
 1345         uint16_t                design_voltage;
 1346         uint16_t                spec_info;
 1347         uint16_t                serial_number;
 1348         uint16_t                pack_stat_config;
 1349         uint8_t                 mfg_name[12];
 1350         uint8_t                 device_name[8];
 1351         uint8_t                 device_chemistry[8];
 1352         uint8_t                 mfg_data[8];
 1353         uint8_t                 reserved[17];
 1354 } __packed;
 1355 
 1356 struct mfi_ibbu_state {
 1357         uint16_t                gas_guage_status;
 1358         uint16_t                relative_charge;
 1359         uint16_t                charger_system_state;
 1360         uint16_t                charger_system_ctrl;
 1361         uint16_t                charging_current;
 1362         uint16_t                absolute_charge;
 1363         uint16_t                max_error;
 1364         uint8_t                 reserved[18];
 1365 } __packed;
 1366 
 1367 struct mfi_bbu_state {
 1368         uint16_t                gas_guage_status;
 1369         uint16_t                relative_charge;
 1370         uint16_t                charger_status;
 1371         uint16_t                remaining_capacity;
 1372         uint16_t                full_charge_capacity;
 1373         uint8_t                 is_SOH_good;
 1374         uint8_t                 reserved[21];
 1375 } __packed;
 1376 
 1377 struct mfi_bbu_properties {
 1378         uint32_t                auto_learn_period;
 1379         uint32_t                next_learn_time;
 1380         uint8_t                 learn_delay_interval;
 1381         uint8_t                 auto_learn_mode;
 1382         uint8_t                 bbu_mode;
 1383         uint8_t                 reserved[21];
 1384 } __packed;
 1385 
 1386 union mfi_bbu_status_detail {
 1387         struct mfi_ibbu_state   ibbu;
 1388         struct mfi_bbu_state    bbu;
 1389 };
 1390 
 1391 struct mfi_bbu_status {
 1392         uint8_t                 battery_type;
 1393 #define MFI_BBU_TYPE_NONE       0
 1394 #define MFI_BBU_TYPE_IBBU       1
 1395 #define MFI_BBU_TYPE_BBU        2
 1396         uint8_t                 reserved;
 1397         uint16_t                voltage;
 1398         int16_t                 current;
 1399         uint16_t                temperature;
 1400         uint32_t                fw_status;
 1401 #define MFI_BBU_STATE_PACK_MISSING      (1 << 0)
 1402 #define MFI_BBU_STATE_VOLTAGE_LOW       (1 << 1)
 1403 #define MFI_BBU_STATE_TEMPERATURE_HIGH  (1 << 2)
 1404 #define MFI_BBU_STATE_CHARGE_ACTIVE     (1 << 3)
 1405 #define MFI_BBU_STATE_DISCHARGE_ACTIVE  (1 << 4)
 1406 #define MFI_BBU_STATE_LEARN_CYC_REQ     (1 << 5)
 1407 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE  (1 << 6)
 1408 #define MFI_BBU_STATE_LEARN_CYC_FAIL    (1 << 7)
 1409 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8)
 1410 #define MFI_BBU_STATE_I2C_ERR_DETECT    (1 << 9)
 1411         uint8_t                 pad[20];
 1412         union mfi_bbu_status_detail detail;
 1413 } __packed;
 1414 
 1415 enum mfi_pr_state {
 1416         MFI_PR_STATE_STOPPED = 0,
 1417         MFI_PR_STATE_READY = 1,
 1418         MFI_PR_STATE_ACTIVE = 2,
 1419         MFI_PR_STATE_ABORTED = 0xff
 1420 };
 1421 
 1422 struct mfi_pr_status {
 1423         uint32_t                num_iteration;
 1424         uint8_t                 state;
 1425         uint8_t                 num_pd_done;
 1426         uint8_t                 reserved[10];
 1427 };
 1428 
 1429 enum mfi_pr_opmode {
 1430         MFI_PR_OPMODE_AUTO = 0,
 1431         MFI_PR_OPMODE_MANUAL = 1,
 1432         MFI_PR_OPMODE_DISABLED = 2
 1433 };
 1434 
 1435 struct mfi_pr_properties {
 1436         uint8_t                 op_mode;
 1437         uint8_t                 max_pd;
 1438         uint8_t                 reserved;
 1439         uint8_t                 exclude_ld_count;
 1440         uint16_t                excluded_ld[MFI_MAX_LD];
 1441         uint8_t                 cur_pd_map[MFI_MAX_PD / 8];
 1442         uint8_t                 last_pd_map[MFI_MAX_PD / 8];
 1443         uint32_t                next_exec;
 1444         uint32_t                exec_freq;
 1445         uint32_t                clear_freq;
 1446 };
 1447 
 1448 /* ThunderBolt support */
 1449 
 1450 /*
 1451  * Raid Context structure which describes MegaRAID specific IO Paramenters
 1452  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 1453  */
 1454 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE {
 1455         uint16_t        resvd0;         /* 0x00 - 0x01 */
 1456         uint16_t        timeoutValue;   /* 0x02 - 0x03 */
 1457         uint8_t         regLockFlags;
 1458         uint8_t         armId;
 1459         uint16_t        TargetID;       /* 0x06 - 0x07 */
 1460 
 1461         uint64_t        RegLockLBA;     /* 0x08 - 0x0F */
 1462 
 1463         uint32_t        RegLockLength;  /* 0x10 - 0x13 */
 1464 
 1465         uint16_t        SMID;           /* 0x14 - 0x15 nextLMId */
 1466         uint8_t         exStatus;       /* 0x16 */
 1467         uint8_t         Status;         /* 0x17 status */
 1468 
 1469         uint8_t         RAIDFlags;      /* 0x18 */
 1470         uint8_t         numSGE;         /* 0x19 numSge */
 1471         uint16_t        configSeqNum;   /* 0x1A - 0x1B */
 1472         uint8_t         spanArm;        /* 0x1C */
 1473         uint8_t         resvd2[3];      /* 0x1D - 0x1F */
 1474 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE;
 1475 
 1476 /*****************************************************************************
 1477 *
 1478 *        Message Functions
 1479 *
 1480 *****************************************************************************/
 1481 
 1482 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST            (0x00) /* SCSI IO */
 1483 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 1484 #define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 1485 #define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 1486 #define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 1487 #define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 1488 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 1489 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 1490 #define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 1491 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 1492 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 1493 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 1494 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 1495 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 1496 #define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 1497 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 1498 #define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 1499 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 1500 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 1501 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 1502 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 1503 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 1504 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 1505 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 1506 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 1507 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator */
 1508 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F) /* Host Based Discovery Action */
 1509 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30) /* Power Management Control */
 1510 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0) /* beginning of product-specific range */
 1511 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF) /* end of product-specific range */
 1512 
 1513 /* Doorbell functions */
 1514 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 1515 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 1516 
 1517 /*****************************************************************************
 1518 *
 1519 *        MPI Version Definitions
 1520 *
 1521 *****************************************************************************/
 1522 
 1523 #define MPI2_VERSION_MAJOR                  (0x02)
 1524 #define MPI2_VERSION_MINOR                  (0x00)
 1525 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 1526 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 1527 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 1528 #define MPI2_VERSION_MINOR_SHIFT            (0)
 1529 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
 1530                                       MPI2_VERSION_MINOR)
 1531 
 1532 #define MPI2_VERSION_02_00                  (0x0200)
 1533 
 1534 /* versioning for this MPI header set */
 1535 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 1536 #define MPI2_HEADER_VERSION_DEV             (0x00)
 1537 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 1538 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 1539 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 1540 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 1541 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) |          \
 1542                                         MPI2_HEADER_VERSION_DEV)
 1543 
 1544 
 1545 /* IOCInit Request message */
 1546 struct MPI2_IOC_INIT_REQUEST {
 1547         uint8_t         WhoInit;                        /* 0x00 */
 1548         uint8_t         Reserved1;                      /* 0x01 */
 1549         uint8_t         ChainOffset;                    /* 0x02 */
 1550         uint8_t         Function;                       /* 0x03 */
 1551         uint16_t        Reserved2;                      /* 0x04 */
 1552         uint8_t         Reserved3;                      /* 0x06 */
 1553         uint8_t         MsgFlags;                       /* 0x07 */
 1554         uint8_t         VP_ID;                          /* 0x08 */
 1555         uint8_t         VF_ID;                          /* 0x09 */
 1556         uint16_t        Reserved4;                      /* 0x0A */
 1557         uint16_t        MsgVersion;                     /* 0x0C */
 1558         uint16_t        HeaderVersion;                  /* 0x0E */
 1559         uint32_t        Reserved5;                      /* 0x10 */
 1560         uint16_t        Reserved6;                      /* 0x14 */
 1561         uint8_t         Reserved7;                      /* 0x16 */
 1562         uint8_t         HostMSIxVectors;                /* 0x17 */
 1563         uint16_t        Reserved8;                      /* 0x18 */
 1564         uint16_t        SystemRequestFrameSize;         /* 0x1A */
 1565         uint16_t        ReplyDescriptorPostQueueDepth;  /* 0x1C */
 1566         uint16_t        ReplyFreeQueueDepth;            /* 0x1E */
 1567         uint32_t        SenseBufferAddressHigh;         /* 0x20 */
 1568         uint32_t        SystemReplyAddressHigh;         /* 0x24 */
 1569         uint64_t        SystemRequestFrameBaseAddress;  /* 0x28 */
 1570         uint64_t        ReplyDescriptorPostQueueAddress;/* 0x30 */
 1571         uint64_t        ReplyFreeQueueAddress;          /* 0x38 */
 1572         uint64_t        TimeStamp;                      /* 0x40 */
 1573 };
 1574 
 1575 /* WhoInit values */
 1576 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 1577 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 1578 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 1579 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 1580 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 1581 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 1582 
 1583 struct MPI2_SGE_CHAIN_UNION {
 1584         uint16_t        Length;
 1585         uint8_t         NextChainOffset;
 1586         uint8_t         Flags;
 1587         union {
 1588                 uint32_t        Address32;
 1589                 uint64_t        Address64;
 1590         } u;
 1591 };
 1592 
 1593 struct MPI2_IEEE_SGE_SIMPLE32 {
 1594         uint32_t        Address;
 1595         uint32_t        FlagsLength;
 1596 };
 1597 
 1598 struct MPI2_IEEE_SGE_SIMPLE64 {
 1599         uint64_t        Address;
 1600         uint32_t        Length;
 1601         uint16_t        Reserved1;
 1602         uint8_t         Reserved2;
 1603         uint8_t         Flags;
 1604 };
 1605 
 1606 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
 1607         struct MPI2_IEEE_SGE_SIMPLE32   Simple32;
 1608         struct MPI2_IEEE_SGE_SIMPLE64   Simple64;
 1609 } MPI2_IEEE_SGE_SIMPLE_UNION;
 1610 
 1611 typedef struct _MPI2_SGE_SIMPLE_UNION {
 1612         uint32_t        FlagsLength;
 1613         union {
 1614                 uint32_t        Address32;
 1615                 uint64_t        Address64;
 1616         } u;
 1617 } MPI2_SGE_SIMPLE_UNION;
 1618 
 1619 /****************************************************************************
 1620 *  IEEE SGE field definitions and masks
 1621 ****************************************************************************/
 1622 
 1623 /* Flags field bit definitions */
 1624 
 1625 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
 1626 
 1627 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
 1628 
 1629 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
 1630 
 1631 /* Element Type */
 1632 
 1633 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
 1634 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
 1635 
 1636 /* Data Location Address Space */
 1637 
 1638 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
 1639 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
 1640 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
 1641 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
 1642 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 1643 
 1644 /* Address Size */
 1645 
 1646 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 1647 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 1648 
 1649 /*******************/
 1650 /* SCSI IO Control bits */
 1651 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK      (0xFC000000)
 1652 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT     (26)
 1653 
 1654 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK  (0x03000000)
 1655 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER      (0x00000000)
 1656 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 1657 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 1658 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL       (0x03000000)
 1659 
 1660 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK        (0x00007800)
 1661 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT       (11)
 1662 
 1663 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK  (0x00000700)
 1664 #define MPI2_SCSIIO_CONTROL_SIMPLEQ             (0x00000000)
 1665 #define MPI2_SCSIIO_CONTROL_HEADOFQ             (0x00000100)
 1666 #define MPI2_SCSIIO_CONTROL_ORDEREDQ            (0x00000200)
 1667 #define MPI2_SCSIIO_CONTROL_ACAQ                (0x00000400)
 1668 
 1669 #define MPI2_SCSIIO_CONTROL_TLR_MASK            (0x000000C0)
 1670 #define MPI2_SCSIIO_CONTROL_NO_TLR              (0x00000000)
 1671 #define MPI2_SCSIIO_CONTROL_TLR_ON              (0x00000040)
 1672 #define MPI2_SCSIIO_CONTROL_TLR_OFF             (0x00000080)
 1673 
 1674 /*******************/
 1675 
 1676 typedef struct {
 1677         uint8_t         CDB[20];                    /* 0x00 */
 1678         uint32_t        PrimaryReferenceTag;        /* 0x14 */
 1679         uint16_t        PrimaryApplicationTag;      /* 0x18 */
 1680         uint16_t        PrimaryApplicationTagMask;  /* 0x1A */
 1681         uint32_t        TransferLength;             /* 0x1C */
 1682 } MPI2_SCSI_IO_CDB_EEDP32;
 1683 
 1684 
 1685 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
 1686         struct MPI2_IEEE_SGE_SIMPLE32   Chain32;
 1687         struct MPI2_IEEE_SGE_SIMPLE64   Chain64;
 1688 } MPI2_IEEE_SGE_CHAIN_UNION;
 1689 
 1690 typedef union _MPI2_SIMPLE_SGE_UNION {
 1691         MPI2_SGE_SIMPLE_UNION           MpiSimple;
 1692         MPI2_IEEE_SGE_SIMPLE_UNION      IeeeSimple;
 1693 } MPI2_SIMPLE_SGE_UNION;
 1694 
 1695 typedef union _MPI2_SGE_IO_UNION {
 1696         MPI2_SGE_SIMPLE_UNION           MpiSimple;
 1697         struct MPI2_SGE_CHAIN_UNION     MpiChain;
 1698         MPI2_IEEE_SGE_SIMPLE_UNION      IeeeSimple;
 1699         MPI2_IEEE_SGE_CHAIN_UNION       IeeeChain;
 1700 } MPI2_SGE_IO_UNION;
 1701 
 1702 typedef union {
 1703         uint8_t                 CDB32[32];
 1704         MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 1705         MPI2_SGE_SIMPLE_UNION   SGE;
 1706 } MPI2_SCSI_IO_CDB_UNION;
 1707 
 1708 
 1709 /* MPI 2.5 SGLs */
 1710 
 1711 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST        (0x40)
 1712 
 1713 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
 1714         uint64_t        Address;
 1715         uint32_t        Length;
 1716         uint16_t        Reserved1;
 1717         uint8_t         NextChainOffset;
 1718         uint8_t         Flags;
 1719 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t;
 1720 
 1721 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */
 1722 
 1723 
 1724 /********/
 1725 
 1726 /*
 1727  * RAID SCSI IO Request Message
 1728  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 1729  */
 1730 struct mfi_mpi2_request_raid_scsi_io {
 1731         uint16_t                DevHandle;                      /* 0x00 */
 1732         uint8_t                 ChainOffset;                    /* 0x02 */
 1733         uint8_t                 Function;                       /* 0x03 */
 1734         uint16_t                Reserved1;                      /* 0x04 */
 1735         uint8_t                 Reserved2;                      /* 0x06 */
 1736         uint8_t                 MsgFlags;                       /* 0x07 */
 1737         uint8_t                 VP_ID;                          /* 0x08 */
 1738         uint8_t                 VF_ID;                          /* 0x09 */
 1739         uint16_t                Reserved3;                      /* 0x0A */
 1740         uint32_t                SenseBufferLowAddress;          /* 0x0C */
 1741         uint16_t                SGLFlags;                       /* 0x10 */
 1742         uint8_t                 SenseBufferLength;              /* 0x12 */
 1743         uint8_t                 Reserved4;                      /* 0x13 */
 1744         uint8_t                 SGLOffset0;                     /* 0x14 */
 1745         uint8_t                 SGLOffset1;                     /* 0x15 */
 1746         uint8_t                 SGLOffset2;                     /* 0x16 */
 1747         uint8_t                 SGLOffset3;                     /* 0x17 */
 1748         uint32_t                SkipCount;                      /* 0x18 */
 1749         uint32_t                DataLength;                     /* 0x1C */
 1750         uint32_t                BidirectionalDataLength;        /* 0x20 */
 1751         uint16_t                IoFlags;                        /* 0x24 */
 1752         uint16_t                EEDPFlags;                      /* 0x26 */
 1753         uint32_t                EEDPBlockSize;                  /* 0x28 */
 1754         uint32_t                SecondaryReferenceTag;          /* 0x2C */
 1755         uint16_t                SecondaryApplicationTag;        /* 0x30 */
 1756         uint16_t                ApplicationTagTranslationMask;  /* 0x32 */
 1757         uint8_t                 LUN[8];                         /* 0x34 */
 1758         uint32_t                Control;                        /* 0x3C */
 1759         MPI2_SCSI_IO_CDB_UNION  CDB;                            /* 0x40 */
 1760         MPI2_SCSI_IO_VENDOR_UNIQUE      RaidContext;              /* 0x60 */
 1761         MPI2_SGE_IO_UNION       SGL;                            /* 0x80 */
 1762 } __packed;
 1763 
 1764 /*
 1765  * MPT RAID MFA IO Descriptor.
 1766  */
 1767 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR {
 1768         uint32_t        RequestFlags : 8;
 1769         uint32_t        MessageAddress1 : 24; /* bits 31:8*/
 1770         uint32_t        MessageAddress2;      /* bits 61:32 */
 1771 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR;
 1772 
 1773 struct mfi_mpi2_request_header {
 1774         uint8_t         RequestFlags;       /* 0x00 */
 1775         uint8_t         MSIxIndex;          /* 0x01 */
 1776         uint16_t        SMID;               /* 0x02 */
 1777         uint16_t        LMID;               /* 0x04 */
 1778 };
 1779 
 1780 /* defines for the RequestFlags field */
 1781 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 1782 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 1783 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 1784 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 1785 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 1786 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 1787 
 1788 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 1789 
 1790 struct mfi_mpi2_request_high_priority {
 1791         struct mfi_mpi2_request_header  header;
 1792         uint16_t                        reserved;
 1793 };
 1794 
 1795 struct mfi_mpi2_request_scsi_io {
 1796         struct mfi_mpi2_request_header  header;
 1797         uint16_t                        scsi_io_dev_handle;
 1798 };
 1799 
 1800 struct mfi_mpi2_request_scsi_target {
 1801         struct mfi_mpi2_request_header  header;
 1802         uint16_t                        scsi_target_io_index;
 1803 };
 1804 
 1805 /* Request Descriptors */
 1806 union mfi_mpi2_request_descriptor {
 1807         struct mfi_mpi2_request_header          header;
 1808         struct mfi_mpi2_request_high_priority   high_priority;
 1809         struct mfi_mpi2_request_scsi_io         scsi_io;
 1810         struct mfi_mpi2_request_scsi_target     scsi_target;
 1811         uint64_t                                words;
 1812 };
 1813 
 1814 
 1815 struct mfi_mpi2_reply_header {
 1816         uint8_t         ReplyFlags;                 /* 0x00 */
 1817         uint8_t         MSIxIndex;                  /* 0x01 */
 1818         uint16_t        SMID;                       /* 0x02 */
 1819 };
 1820 
 1821 /* defines for the ReplyFlags field */
 1822 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 1823 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 1824 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 1825 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 1826 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 1827 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 1828 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 1829 
 1830 /* values for marking a reply descriptor as unused */
 1831 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 1832 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 1833 
 1834 struct mfi_mpi2_reply_default {
 1835         struct mfi_mpi2_reply_header    header;
 1836         uint32_t                        DescriptorTypeDependent2;
 1837 };
 1838 
 1839 struct mfi_mpi2_reply_address {
 1840         struct mfi_mpi2_reply_header    header;
 1841         uint32_t                        ReplyFrameAddress;
 1842 };
 1843 
 1844 struct mfi_mpi2_reply_scsi_io {
 1845         struct mfi_mpi2_reply_header    header;
 1846         uint16_t                        TaskTag;                /* 0x04 */
 1847         uint16_t                        Reserved1;              /* 0x06 */
 1848 };
 1849 
 1850 struct mfi_mpi2_reply_target_assist {
 1851         struct mfi_mpi2_reply_header    header;
 1852         uint8_t                         SequenceNumber;         /* 0x04 */
 1853         uint8_t                         Reserved1;              /* 0x04 */
 1854         uint16_t                        IoIndex;                /* 0x06 */
 1855 };
 1856 
 1857 struct mfi_mpi2_reply_target_cmd_buffer {
 1858         struct mfi_mpi2_reply_header    header;
 1859         uint8_t                         SequenceNumber;         /* 0x04 */
 1860         uint8_t                         Flags;                  /* 0x04 */
 1861         uint16_t                        InitiatorDevHandle;     /* 0x06 */
 1862         uint16_t                        IoIndex;                /* 0x06 */
 1863 };
 1864 
 1865 struct mfi_mpi2_reply_raid_accel {
 1866         struct mfi_mpi2_reply_header    header;
 1867         uint8_t                         SequenceNumber;         /* 0x04 */
 1868         uint32_t                        Reserved;               /* 0x04 */
 1869 };
 1870 
 1871 /* union of Reply Descriptors */
 1872 union mfi_mpi2_reply_descriptor {
 1873         struct mfi_mpi2_reply_header            header;
 1874         struct mfi_mpi2_reply_scsi_io           scsi_io;
 1875         struct mfi_mpi2_reply_target_assist     target_assist;
 1876         struct mfi_mpi2_reply_target_cmd_buffer target_cmd;
 1877         struct mfi_mpi2_reply_raid_accel        raid_accel;
 1878         struct mfi_mpi2_reply_default           reply_default;
 1879         uint64_t                                words;
 1880 };
 1881 
 1882 struct IO_REQUEST_INFO {
 1883         uint64_t        ldStartBlock;
 1884         uint32_t        numBlocks;
 1885         uint16_t        ldTgtId;
 1886         uint8_t         isRead;
 1887         uint16_t        devHandle;
 1888         uint64_t        pdBlock;
 1889         uint8_t         fpOkForIo;
 1890 };
 1891 
 1892 #define MFI_SCSI_MAX_TARGETS    128
 1893 #define MFI_SCSI_MAX_LUNS       8
 1894 #define MFI_SCSI_INITIATOR_ID   255
 1895 #define MFI_SCSI_MAX_CMDS       8
 1896 #define MFI_SCSI_MAX_CDB_LEN    16
 1897 
 1898 #endif /* _MFIREG_H */
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FreeBSD/Linux Kernel Cross Reference sys/dev/mfi/mfireg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/mfi/mfireg.h
