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sys/dev/mfi/mfivar.h
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1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 #ifndef _MFIVAR_H 54 #define _MFIVAR_H 55 56 #include <sys/cdefs.h> 57 __FBSDID("$FreeBSD$"); 58 59 #include <sys/lock.h> 60 #include <sys/sx.h> 61 62 #include <sys/types.h> 63 #include <sys/taskqueue.h> 64 #include "opt_mfi.h" 65 66 /* 67 * SCSI structures and definitions are used from here, but no linking 68 * requirements are made to CAM. 69 */ 70 #include <cam/scsi/scsi_all.h> 71 72 struct mfi_hwcomms { 73 uint32_t hw_pi; 74 uint32_t hw_ci; 75 uint32_t hw_reply_q[1]; 76 }; 77 #define MEGASAS_MAX_NAME 32 78 #define MEGASAS_VERSION "4.23" 79 80 struct mfi_softc; 81 struct disk; 82 struct ccb_hdr; 83 84 struct mfi_command { 85 TAILQ_ENTRY(mfi_command) cm_link; 86 time_t cm_timestamp; 87 struct mfi_softc *cm_sc; 88 union mfi_frame *cm_frame; 89 bus_addr_t cm_frame_busaddr; 90 struct mfi_sense *cm_sense; 91 bus_addr_t cm_sense_busaddr; 92 bus_dmamap_t cm_dmamap; 93 union mfi_sgl *cm_sg; 94 void *cm_data; 95 int cm_len; 96 int cm_stp_len; 97 int cm_total_frame_size; 98 int cm_extra_frames; 99 int cm_flags; 100 #define MFI_CMD_MAPPED (1<<0) 101 #define MFI_CMD_DATAIN (1<<1) 102 #define MFI_CMD_DATAOUT (1<<2) 103 #define MFI_CMD_COMPLETED (1<<3) 104 #define MFI_CMD_POLLED (1<<4) 105 #define MFI_ON_MFIQ_FREE (1<<5) 106 #define MFI_ON_MFIQ_READY (1<<6) 107 #define MFI_ON_MFIQ_BUSY (1<<7) 108 #define MFI_ON_MFIQ_MASK ((1<<5)|(1<<6)|(1<<7)) 109 uint8_t retry_for_fw_reset; 110 void (* cm_complete)(struct mfi_command *cm); 111 void *cm_private; 112 int cm_index; 113 int cm_error; 114 }; 115 116 struct mfi_disk { 117 TAILQ_ENTRY(mfi_disk) ld_link; 118 device_t ld_dev; 119 int ld_id; 120 int ld_unit; 121 struct mfi_softc *ld_controller; 122 struct mfi_ld_info *ld_info; 123 struct disk *ld_disk; 124 int ld_flags; 125 #define MFI_DISK_FLAGS_OPEN 0x01 126 #define MFI_DISK_FLAGS_DISABLED 0x02 127 }; 128 129 struct mfi_system_pd { 130 TAILQ_ENTRY(mfi_system_pd) pd_link; 131 device_t pd_dev; 132 int pd_id; 133 int pd_unit; 134 struct mfi_softc *pd_controller; 135 struct mfi_pd_info *pd_info; 136 struct disk *pd_disk; 137 int pd_flags; 138 }; 139 140 struct mfi_evt_queue_elm { 141 TAILQ_ENTRY(mfi_evt_queue_elm) link; 142 struct mfi_evt_detail detail; 143 }; 144 145 struct mfi_aen { 146 TAILQ_ENTRY(mfi_aen) aen_link; 147 struct proc *p; 148 }; 149 150 struct mfi_skinny_dma_info { 151 bus_dma_tag_t dmat[514]; 152 bus_dmamap_t dmamap[514]; 153 uint32_t mem[514]; 154 int noofmaps; 155 }; 156 157 struct megasas_sge 158 { 159 bus_addr_t phys_addr; 160 uint32_t length; 161 }; 162 163 struct mfi_cmd_tbolt; 164 165 struct mfi_softc { 166 device_t mfi_dev; 167 int mfi_flags; 168 #define MFI_FLAGS_SG64 (1<<0) 169 #define MFI_FLAGS_QFRZN (1<<1) 170 #define MFI_FLAGS_OPEN (1<<2) 171 #define MFI_FLAGS_STOP (1<<3) 172 #define MFI_FLAGS_1064R (1<<4) 173 #define MFI_FLAGS_1078 (1<<5) 174 #define MFI_FLAGS_GEN2 (1<<6) 175 #define MFI_FLAGS_SKINNY (1<<7) 176 #define MFI_FLAGS_TBOLT (1<<8) 177 // Start: LSIP200113393 178 bus_dma_tag_t verbuf_h_dmat; 179 bus_dmamap_t verbuf_h_dmamap; 180 bus_addr_t verbuf_h_busaddr; 181 uint32_t *verbuf; 182 void *kbuff_arr[MAX_IOCTL_SGE]; 183 bus_dma_tag_t mfi_kbuff_arr_dmat[2]; 184 bus_dmamap_t mfi_kbuff_arr_dmamap[2]; 185 bus_addr_t mfi_kbuff_arr_busaddr[2]; 186 187 struct mfi_hwcomms *mfi_comms; 188 TAILQ_HEAD(,mfi_command) mfi_free; 189 TAILQ_HEAD(,mfi_command) mfi_ready; 190 TAILQ_HEAD(BUSYQ,mfi_command) mfi_busy; 191 struct bio_queue_head mfi_bioq; 192 struct mfi_qstat mfi_qstat[MFIQ_COUNT]; 193 194 struct resource *mfi_regs_resource; 195 bus_space_handle_t mfi_bhandle; 196 bus_space_tag_t mfi_btag; 197 int mfi_regs_rid; 198 199 bus_dma_tag_t mfi_parent_dmat; 200 bus_dma_tag_t mfi_buffer_dmat; 201 202 bus_dma_tag_t mfi_comms_dmat; 203 bus_dmamap_t mfi_comms_dmamap; 204 bus_addr_t mfi_comms_busaddr; 205 206 bus_dma_tag_t mfi_frames_dmat; 207 bus_dmamap_t mfi_frames_dmamap; 208 bus_addr_t mfi_frames_busaddr; 209 union mfi_frame *mfi_frames; 210 211 bus_dma_tag_t mfi_tb_init_dmat; 212 bus_dmamap_t mfi_tb_init_dmamap; 213 bus_addr_t mfi_tb_init_busaddr; 214 bus_addr_t mfi_tb_ioc_init_busaddr; 215 union mfi_frame *mfi_tb_init; 216 217 TAILQ_HEAD(,mfi_evt_queue_elm) mfi_evt_queue; 218 struct task mfi_evt_task; 219 struct task mfi_map_sync_task; 220 TAILQ_HEAD(,mfi_aen) mfi_aen_pids; 221 struct mfi_command *mfi_aen_cm; 222 struct mfi_command *mfi_skinny_cm; 223 struct mfi_command *mfi_map_sync_cm; 224 int cm_aen_abort; 225 int cm_map_abort; 226 uint32_t mfi_aen_triggered; 227 uint32_t mfi_poll_waiting; 228 uint32_t mfi_boot_seq_num; 229 struct selinfo mfi_select; 230 int mfi_delete_busy_volumes; 231 int mfi_keep_deleted_volumes; 232 int mfi_detaching; 233 234 bus_dma_tag_t mfi_sense_dmat; 235 bus_dmamap_t mfi_sense_dmamap; 236 bus_addr_t mfi_sense_busaddr; 237 struct mfi_sense *mfi_sense; 238 239 struct resource *mfi_irq; 240 void *mfi_intr; 241 int mfi_irq_rid; 242 243 struct intr_config_hook mfi_ich; 244 eventhandler_tag eh; 245 /* OCR flags */ 246 uint8_t adpreset; 247 uint8_t issuepend_done; 248 uint8_t disableOnlineCtrlReset; 249 uint32_t mfiStatus; 250 uint32_t last_seq_num; 251 uint32_t volatile hw_crit_error; 252 253 /* 254 * Allocation for the command array. Used as an indexable array to 255 * recover completed commands. 256 */ 257 struct mfi_command *mfi_commands; 258 /* 259 * How many commands were actually allocated 260 */ 261 int mfi_total_cmds; 262 /* 263 * How many commands the firmware can handle. Also how big the reply 264 * queue is, minus 1. 265 */ 266 int mfi_max_fw_cmds; 267 /* 268 * How many S/G elements we'll ever actually use 269 */ 270 int mfi_max_sge; 271 /* 272 * How many bytes a compound frame is, including all of the extra frames 273 * that are used for S/G elements. 274 */ 275 int mfi_cmd_size; 276 /* 277 * How large an S/G element is. Used to calculate the number of single 278 * frames in a command. 279 */ 280 int mfi_sge_size; 281 /* 282 * Max number of sectors that the firmware allows 283 */ 284 uint32_t mfi_max_io; 285 286 TAILQ_HEAD(,mfi_disk) mfi_ld_tqh; 287 TAILQ_HEAD(,mfi_system_pd) mfi_syspd_tqh; 288 eventhandler_tag mfi_eh; 289 struct cdev *mfi_cdev; 290 291 TAILQ_HEAD(, ccb_hdr) mfi_cam_ccbq; 292 struct mfi_command * (* mfi_cam_start)(void *); 293 struct callout mfi_watchdog_callout; 294 struct mtx mfi_io_lock; 295 struct sx mfi_config_lock; 296 297 /* Controller type specific interfaces */ 298 void (*mfi_enable_intr)(struct mfi_softc *sc); 299 void (*mfi_disable_intr)(struct mfi_softc *sc); 300 int32_t (*mfi_read_fw_status)(struct mfi_softc *sc); 301 int (*mfi_check_clear_intr)(struct mfi_softc *sc); 302 void (*mfi_issue_cmd)(struct mfi_softc *sc, bus_addr_t bus_add, 303 uint32_t frame_cnt); 304 int (*mfi_adp_reset)(struct mfi_softc *sc); 305 int (*mfi_adp_check_reset)(struct mfi_softc *sc); 306 307 /* ThunderBolt */ 308 uint32_t mfi_tbolt; 309 uint32_t MFA_enabled; 310 /* Single Reply structure size */ 311 uint16_t reply_size; 312 /* Singler message size. */ 313 uint16_t raid_io_msg_size; 314 TAILQ_HEAD(TB, mfi_cmd_tbolt) mfi_cmd_tbolt_tqh; 315 /* ThunderBolt base contiguous memory mapping. */ 316 bus_dma_tag_t mfi_tb_dmat; 317 bus_dmamap_t mfi_tb_dmamap; 318 bus_addr_t mfi_tb_busaddr; 319 /* ThunderBolt Contiguous DMA memory Mapping */ 320 uint8_t * request_message_pool; 321 uint8_t * request_message_pool_align; 322 uint8_t * request_desc_pool; 323 bus_addr_t request_msg_busaddr; 324 bus_addr_t reply_frame_busaddr; 325 bus_addr_t sg_frame_busaddr; 326 /* ThunderBolt IOC Init Descriptor */ 327 bus_dma_tag_t mfi_tb_ioc_init_dmat; 328 bus_dmamap_t mfi_tb_ioc_init_dmamap; 329 uint8_t * mfi_tb_ioc_init_desc; 330 struct mfi_cmd_tbolt **mfi_cmd_pool_tbolt; 331 /* Virtual address of reply Frame Pool */ 332 struct mfi_mpi2_reply_header* reply_frame_pool; 333 struct mfi_mpi2_reply_header* reply_frame_pool_align; 334 335 /* Last reply frame address */ 336 uint8_t * reply_pool_limit; 337 uint16_t last_reply_idx; 338 uint8_t max_SGEs_in_chain_message; 339 uint8_t max_SGEs_in_main_message; 340 uint8_t chain_offset_value_for_main_message; 341 uint8_t chain_offset_value_for_mpt_ptmsg; 342 }; 343 344 union desc_value { 345 uint64_t word; 346 struct { 347 uint32_t low; 348 uint32_t high; 349 }u; 350 }; 351 352 // TODO find the right definition 353 #define XXX_MFI_CMD_OP_INIT2 0x9 354 /* 355 * Request descriptor types 356 */ 357 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 358 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 359 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 360 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 361 #define MFI_LOAD_BALANCE_FLAG 0x1 362 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 363 364 //#define MR_PROT_INFO_TYPE_CONTROLLER 0x08 365 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 366 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 367 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 368 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 369 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 370 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 371 #define MEGASAS_EEDPBLOCKSIZE 512 372 struct mfi_cmd_tbolt { 373 union mfi_mpi2_request_descriptor *request_desc; 374 struct mfi_mpi2_request_raid_scsi_io *io_request; 375 bus_addr_t io_request_phys_addr; 376 bus_addr_t sg_frame_phys_addr; 377 bus_addr_t sense_phys_addr; 378 MPI2_SGE_IO_UNION *sg_frame; 379 uint8_t *sense; 380 TAILQ_ENTRY(mfi_cmd_tbolt) next; 381 /* 382 * Context for a MFI frame. 383 * Used to get the mfi cmd from list when a MFI cmd is completed 384 */ 385 uint32_t sync_cmd_idx; 386 uint16_t index; 387 uint8_t status; 388 }; 389 390 extern int mfi_attach(struct mfi_softc *); 391 extern void mfi_free(struct mfi_softc *); 392 extern int mfi_shutdown(struct mfi_softc *); 393 extern void mfi_startio(struct mfi_softc *); 394 extern void mfi_disk_complete(struct bio *); 395 extern int mfi_disk_disable(struct mfi_disk *); 396 extern void mfi_disk_enable(struct mfi_disk *); 397 extern int mfi_dump_blocks(struct mfi_softc *, int id, uint64_t, void *, int); 398 extern int mfi_syspd_disable(struct mfi_system_pd *); 399 extern void mfi_syspd_enable(struct mfi_system_pd *); 400 extern int mfi_dump_syspd_blocks(struct mfi_softc *, int id, uint64_t, void *, 401 int); 402 extern int mfi_transition_firmware(struct mfi_softc *sc); 403 extern int mfi_aen_setup(struct mfi_softc *sc, uint32_t seq_start); 404 extern void mfi_complete(struct mfi_softc *sc, struct mfi_command *cm); 405 extern int mfi_mapcmd(struct mfi_softc *sc,struct mfi_command *cm); 406 extern int mfi_wait_command(struct mfi_softc *sc, struct mfi_command *cm); 407 extern void mfi_tbolt_enable_intr_ppc(struct mfi_softc *); 408 extern void mfi_tbolt_disable_intr_ppc(struct mfi_softc *); 409 extern int32_t mfi_tbolt_read_fw_status_ppc(struct mfi_softc *); 410 extern int32_t mfi_tbolt_check_clear_intr_ppc(struct mfi_softc *); 411 extern void mfi_tbolt_issue_cmd_ppc(struct mfi_softc *, bus_addr_t, uint32_t); 412 extern void mfi_tbolt_init_globals(struct mfi_softc*); 413 extern uint32_t mfi_tbolt_get_memory_requirement(struct mfi_softc *); 414 extern int mfi_tbolt_init_desc_pool(struct mfi_softc *, uint8_t *, uint32_t); 415 extern int mfi_tbolt_init_MFI_queue(struct mfi_softc *); 416 extern void mfi_intr_tbolt(void *arg); 417 extern int mfi_tbolt_alloc_cmd(struct mfi_softc *sc); 418 extern int mfi_tbolt_send_frame(struct mfi_softc *sc, struct mfi_command *cm); 419 extern int mfi_tbolt_adp_reset(struct mfi_softc *sc); 420 extern int mfi_tbolt_reset(struct mfi_softc *sc); 421 extern void mfi_tbolt_sync_map_info(struct mfi_softc *sc); 422 extern void mfi_handle_map_sync(void *context, int pending); 423 extern int mfi_dcmd_command(struct mfi_softc *, struct mfi_command **, 424 uint32_t, void **, size_t); 425 426 #define MFIQ_ADD(sc, qname) \ 427 do { \ 428 struct mfi_qstat *qs; \ 429 \ 430 qs = &(sc)->mfi_qstat[qname]; \ 431 qs->q_length++; \ 432 if (qs->q_length > qs->q_max) \ 433 qs->q_max = qs->q_length; \ 434 } while (0) 435 436 #define MFIQ_REMOVE(sc, qname) (sc)->mfi_qstat[qname].q_length-- 437 438 #define MFIQ_INIT(sc, qname) \ 439 do { \ 440 sc->mfi_qstat[qname].q_length = 0; \ 441 sc->mfi_qstat[qname].q_max = 0; \ 442 } while (0) 443 444 #define MFIQ_COMMAND_QUEUE(name, index) \ 445 static __inline void \ 446 mfi_initq_ ## name (struct mfi_softc *sc) \ 447 { \ 448 TAILQ_INIT(&sc->mfi_ ## name); \ 449 MFIQ_INIT(sc, index); \ 450 } \ 451 static __inline void \ 452 mfi_enqueue_ ## name (struct mfi_command *cm) \ 453 { \ 454 if ((cm->cm_flags & MFI_ON_MFIQ_MASK) != 0) { \ 455 printf("command %p is on another queue, " \ 456 "flags = %#x\n", cm, cm->cm_flags); \ 457 panic("command is on another queue"); \ 458 } \ 459 TAILQ_INSERT_TAIL(&cm->cm_sc->mfi_ ## name, cm, cm_link); \ 460 cm->cm_flags |= MFI_ON_ ## index; \ 461 MFIQ_ADD(cm->cm_sc, index); \ 462 } \ 463 static __inline void \ 464 mfi_requeue_ ## name (struct mfi_command *cm) \ 465 { \ 466 if ((cm->cm_flags & MFI_ON_MFIQ_MASK) != 0) { \ 467 printf("command %p is on another queue, " \ 468 "flags = %#x\n", cm, cm->cm_flags); \ 469 panic("command is on another queue"); \ 470 } \ 471 TAILQ_INSERT_HEAD(&cm->cm_sc->mfi_ ## name, cm, cm_link); \ 472 cm->cm_flags |= MFI_ON_ ## index; \ 473 MFIQ_ADD(cm->cm_sc, index); \ 474 } \ 475 static __inline struct mfi_command * \ 476 mfi_dequeue_ ## name (struct mfi_softc *sc) \ 477 { \ 478 struct mfi_command *cm; \ 479 \ 480 if ((cm = TAILQ_FIRST(&sc->mfi_ ## name)) != NULL) { \ 481 if ((cm->cm_flags & MFI_ON_ ## index) == 0) { \ 482 printf("command %p not in queue, " \ 483 "flags = %#x, bit = %#x\n", cm, \ 484 cm->cm_flags, MFI_ON_ ## index); \ 485 panic("command not in queue"); \ 486 } \ 487 TAILQ_REMOVE(&sc->mfi_ ## name, cm, cm_link); \ 488 cm->cm_flags &= ~MFI_ON_ ## index; \ 489 MFIQ_REMOVE(sc, index); \ 490 } \ 491 return (cm); \ 492 } \ 493 static __inline void \ 494 mfi_remove_ ## name (struct mfi_command *cm) \ 495 { \ 496 if ((cm->cm_flags & MFI_ON_ ## index) == 0) { \ 497 printf("command %p not in queue, flags = %#x, " \ 498 "bit = %#x\n", cm, cm->cm_flags, \ 499 MFI_ON_ ## index); \ 500 panic("command not in queue"); \ 501 } \ 502 TAILQ_REMOVE(&cm->cm_sc->mfi_ ## name, cm, cm_link); \ 503 cm->cm_flags &= ~MFI_ON_ ## index; \ 504 MFIQ_REMOVE(cm->cm_sc, index); \ 505 } \ 506 struct hack 507 508 MFIQ_COMMAND_QUEUE(free, MFIQ_FREE); 509 MFIQ_COMMAND_QUEUE(ready, MFIQ_READY); 510 MFIQ_COMMAND_QUEUE(busy, MFIQ_BUSY); 511 512 static __inline void 513 mfi_initq_bio(struct mfi_softc *sc) 514 { 515 bioq_init(&sc->mfi_bioq); 516 MFIQ_INIT(sc, MFIQ_BIO); 517 } 518 519 static __inline void 520 mfi_enqueue_bio(struct mfi_softc *sc, struct bio *bp) 521 { 522 bioq_insert_tail(&sc->mfi_bioq, bp); 523 MFIQ_ADD(sc, MFIQ_BIO); 524 } 525 526 static __inline struct bio * 527 mfi_dequeue_bio(struct mfi_softc *sc) 528 { 529 struct bio *bp; 530 531 if ((bp = bioq_first(&sc->mfi_bioq)) != NULL) { 532 bioq_remove(&sc->mfi_bioq, bp); 533 MFIQ_REMOVE(sc, MFIQ_BIO); 534 } 535 return (bp); 536 } 537 538 static __inline void 539 mfi_print_sense(struct mfi_softc *sc, void *sense) 540 { 541 int error, key, asc, ascq; 542 543 scsi_extract_sense((struct scsi_sense_data *)sense, 544 &error, &key, &asc, &ascq); 545 device_printf(sc->mfi_dev, "sense error %d, sense_key %d, " 546 "asc %d, ascq %d\n", error, key, asc, ascq); 547 } 548 549 550 #define MFI_WRITE4(sc, reg, val) bus_space_write_4((sc)->mfi_btag, \ 551 sc->mfi_bhandle, (reg), (val)) 552 #define MFI_READ4(sc, reg) bus_space_read_4((sc)->mfi_btag, \ 553 (sc)->mfi_bhandle, (reg)) 554 #define MFI_WRITE2(sc, reg, val) bus_space_write_2((sc)->mfi_btag, \ 555 sc->mfi_bhandle, (reg), (val)) 556 #define MFI_READ2(sc, reg) bus_space_read_2((sc)->mfi_btag, \ 557 (sc)->mfi_bhandle, (reg)) 558 #define MFI_WRITE1(sc, reg, val) bus_space_write_1((sc)->mfi_btag, \ 559 sc->mfi_bhandle, (reg), (val)) 560 #define MFI_READ1(sc, reg) bus_space_read_1((sc)->mfi_btag, \ 561 (sc)->mfi_bhandle, (reg)) 562 563 MALLOC_DECLARE(M_MFIBUF); 564 SYSCTL_DECL(_hw_mfi); 565 566 #define MFI_RESET_WAIT_TIME 180 567 #define MFI_CMD_TIMEOUT 30 568 #define MFI_SYS_PD_IO 0 569 #define MFI_LD_IO 1 570 #define MFI_SKINNY_MEMORY 0x02000000 571 #define MFI_MAXPHYS (128 * 1024) 572 573 #ifdef MFI_DEBUG 574 extern void mfi_print_cmd(struct mfi_command *cm); 575 extern void mfi_dump_cmds(struct mfi_softc *sc); 576 extern void mfi_validate_sg(struct mfi_softc *, struct mfi_command *, const char *, int ); 577 #define MFI_PRINT_CMD(cm) mfi_print_cmd(cm) 578 #define MFI_DUMP_CMDS(sc) mfi_dump_cmds(sc) 579 #define MFI_VALIDATE_CMD(sc, cm) mfi_validate_sg(sc, cm, __FUNCTION__, __LINE__) 580 #else 581 #define MFI_PRINT_CMD(cm) 582 #define MFI_DUMP_CMDS(sc) 583 #define MFI_VALIDATE_CMD(sc, cm) 584 #endif 585 586 extern void mfi_release_command(struct mfi_command *cm); 587 588 #endif /* _MFIVAR_H */
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