Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/atphy.c
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1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mii/atphy.c 230718 2012-01-29 01:35:14Z marius $"); 30 31 /* 32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/socket.h> 40 #include <sys/bus.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/mii.h> 46 #include <dev/mii/miivar.h> 47 #include "miidevs.h" 48 49 #include <dev/mii/atphyreg.h> 50 51 #include "miibus_if.h" 52 53 static int atphy_probe(device_t); 54 static int atphy_attach(device_t); 55 56 struct atphy_softc { 57 struct mii_softc mii_sc; 58 int mii_oui; 59 int mii_model; 60 int mii_rev; 61 }; 62 63 static device_method_t atphy_methods[] = { 64 /* Device interface. */ 65 DEVMETHOD(device_probe, atphy_probe), 66 DEVMETHOD(device_attach, atphy_attach), 67 DEVMETHOD(device_detach, mii_phy_detach), 68 DEVMETHOD(device_shutdown, bus_generic_shutdown), 69 DEVMETHOD_END 70 }; 71 72 static devclass_t atphy_devclass; 73 static driver_t atphy_driver = { 74 "atphy", 75 atphy_methods, 76 sizeof(struct atphy_softc) 77 }; 78 79 DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0); 80 81 static int atphy_service(struct mii_softc *, struct mii_data *, int); 82 static void atphy_status(struct mii_softc *); 83 static void atphy_reset(struct mii_softc *); 84 static uint16_t atphy_anar(struct ifmedia_entry *); 85 static int atphy_setmedia(struct mii_softc *, int); 86 87 static const struct mii_phydesc atphys[] = { 88 MII_PHY_DESC(ATHEROS, F1), 89 MII_PHY_DESC(ATHEROS, F1_7), 90 MII_PHY_DESC(ATHEROS, F2), 91 MII_PHY_END 92 }; 93 94 static int 95 atphy_probe(device_t dev) 96 { 97 98 return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT)); 99 } 100 101 static int 102 atphy_attach(device_t dev) 103 { 104 struct atphy_softc *asc; 105 struct mii_softc *sc; 106 struct mii_attach_args *ma; 107 struct mii_data *mii; 108 109 asc = device_get_softc(dev); 110 sc = &asc->mii_sc; 111 ma = device_get_ivars(dev); 112 sc->mii_dev = device_get_parent(dev); 113 mii = ma->mii_data; 114 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 115 116 sc->mii_flags = miibus_get_flags(dev); 117 sc->mii_inst = mii->mii_instance++; 118 sc->mii_phy = ma->mii_phyno; 119 sc->mii_service = atphy_service; 120 sc->mii_pdata = mii; 121 122 sc->mii_flags |= MIIF_NOMANPAUSE; 123 124 asc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 125 asc->mii_model = MII_MODEL(ma->mii_id2); 126 asc->mii_rev = MII_REV(ma->mii_id2); 127 if (bootverbose) 128 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 129 asc->mii_oui, asc->mii_model, asc->mii_rev); 130 131 atphy_reset(sc); 132 133 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 134 if (sc->mii_capabilities & BMSR_EXTSTAT) 135 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 136 device_printf(dev, " "); 137 mii_phy_add_media(sc); 138 printf("\n"); 139 140 MIIBUS_MEDIAINIT(sc->mii_dev); 141 return (0); 142 } 143 144 static int 145 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 146 { 147 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 148 uint16_t anar, bmcr, bmsr; 149 150 switch (cmd) { 151 case MII_POLLSTAT: 152 break; 153 154 case MII_MEDIACHG: 155 /* 156 * If the interface is not up, don't do anything. 157 */ 158 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 159 break; 160 161 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 162 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 163 atphy_setmedia(sc, ife->ifm_media); 164 break; 165 } 166 167 bmcr = 0; 168 switch (IFM_SUBTYPE(ife->ifm_media)) { 169 case IFM_100_TX: 170 bmcr = BMCR_S100; 171 break; 172 case IFM_10_T: 173 bmcr = BMCR_S10; 174 break; 175 case IFM_NONE: 176 bmcr = PHY_READ(sc, MII_BMCR); 177 /* 178 * XXX 179 * Due to an unknown reason powering down PHY resulted 180 * in unexpected results such as inaccessibility of 181 * hardware of freshly rebooted system. Disable 182 * powering down PHY until I got more information for 183 * Attansic/Atheros PHY hardwares. 184 */ 185 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 186 goto done; 187 default: 188 return (EINVAL); 189 } 190 191 anar = atphy_anar(ife); 192 if ((ife->ifm_media & IFM_FDX) != 0) { 193 bmcr |= BMCR_FDX; 194 if ((ife->ifm_media & IFM_FLOW) != 0 || 195 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 196 anar |= ANAR_PAUSE_TOWARDS; 197 } 198 199 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 200 EXTSR_1000THDX)) != 0) 201 PHY_WRITE(sc, MII_100T2CR, 0); 202 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA); 203 204 /* 205 * Reset the PHY so all changes take effect. 206 */ 207 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN | 208 BMCR_STARTNEG); 209 done: 210 break; 211 212 case MII_TICK: 213 /* 214 * Is the interface even up? 215 */ 216 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 217 return (0); 218 219 /* 220 * Only used for autonegotiation. 221 */ 222 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 223 sc->mii_ticks = 0; 224 break; 225 } 226 227 /* 228 * Check for link. 229 * Read the status register twice; BMSR_LINK is latch-low. 230 */ 231 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 232 if (bmsr & BMSR_LINK) { 233 sc->mii_ticks = 0; 234 break; 235 } 236 237 /* Announce link loss right after it happens. */ 238 if (sc->mii_ticks++ == 0) 239 break; 240 if (sc->mii_ticks <= sc->mii_anegticks) 241 return (0); 242 243 sc->mii_ticks = 0; 244 atphy_setmedia(sc, ife->ifm_media); 245 break; 246 } 247 248 /* Update the media status. */ 249 atphy_status(sc); 250 251 /* Callback if something changed. */ 252 mii_phy_update(sc, cmd); 253 return (0); 254 } 255 256 static void 257 atphy_status(struct mii_softc *sc) 258 { 259 struct mii_data *mii = sc->mii_pdata; 260 uint32_t bmsr, bmcr, ssr; 261 262 mii->mii_media_status = IFM_AVALID; 263 mii->mii_media_active = IFM_ETHER; 264 265 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 266 if ((bmsr & BMSR_LINK) != 0) 267 mii->mii_media_status |= IFM_ACTIVE; 268 269 bmcr = PHY_READ(sc, MII_BMCR); 270 if ((bmcr & BMCR_ISO) != 0) { 271 mii->mii_media_active |= IFM_NONE; 272 mii->mii_media_status = 0; 273 return; 274 } 275 276 if ((bmcr & BMCR_LOOP) != 0) 277 mii->mii_media_active |= IFM_LOOP; 278 279 ssr = PHY_READ(sc, ATPHY_SSR); 280 if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) { 281 /* Erg, still trying, I guess... */ 282 mii->mii_media_active |= IFM_NONE; 283 return; 284 } 285 286 switch (ssr & ATPHY_SSR_SPEED_MASK) { 287 case ATPHY_SSR_1000MBS: 288 mii->mii_media_active |= IFM_1000_T; 289 /* 290 * atphy(4) has a valid link so reset mii_ticks. 291 * Resetting mii_ticks is needed in order to 292 * detect link loss after auto-negotiation. 293 */ 294 sc->mii_ticks = 0; 295 break; 296 case ATPHY_SSR_100MBS: 297 mii->mii_media_active |= IFM_100_TX; 298 sc->mii_ticks = 0; 299 break; 300 case ATPHY_SSR_10MBS: 301 mii->mii_media_active |= IFM_10_T; 302 sc->mii_ticks = 0; 303 break; 304 default: 305 mii->mii_media_active |= IFM_NONE; 306 return; 307 } 308 309 if ((ssr & ATPHY_SSR_DUPLEX) != 0) 310 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 311 else 312 mii->mii_media_active |= IFM_HDX; 313 314 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 315 (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0) 316 mii->mii_media_active |= IFM_ETH_MASTER; 317 } 318 319 static void 320 atphy_reset(struct mii_softc *sc) 321 { 322 struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur; 323 uint32_t reg; 324 int i; 325 326 /* Take PHY out of power down mode. */ 327 PHY_WRITE(sc, 29, 0x29); 328 PHY_WRITE(sc, 30, 0); 329 330 reg = PHY_READ(sc, ATPHY_SCR); 331 /* Enable automatic crossover. */ 332 reg |= ATPHY_SCR_AUTO_X_MODE; 333 /* Disable power down. */ 334 reg &= ~ATPHY_SCR_MAC_PDOWN; 335 /* Enable CRS on Tx. */ 336 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 337 /* Auto correction for reversed cable polarity. */ 338 reg |= ATPHY_SCR_POLARITY_REVERSAL; 339 PHY_WRITE(sc, ATPHY_SCR, reg); 340 341 /* Workaround F1 bug to reset phy. */ 342 atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media); 343 344 for (i = 0; i < 1000; i++) { 345 DELAY(1); 346 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 347 break; 348 } 349 } 350 351 static uint16_t 352 atphy_anar(struct ifmedia_entry *ife) 353 { 354 uint16_t anar; 355 356 anar = 0; 357 switch (IFM_SUBTYPE(ife->ifm_media)) { 358 case IFM_AUTO: 359 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 360 return (anar); 361 case IFM_1000_T: 362 return (anar); 363 case IFM_100_TX: 364 anar |= ANAR_TX; 365 break; 366 case IFM_10_T: 367 anar |= ANAR_10; 368 break; 369 default: 370 return (0); 371 } 372 373 if ((ife->ifm_media & IFM_FDX) != 0) { 374 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 375 anar |= ANAR_TX_FD; 376 else 377 anar |= ANAR_10_FD; 378 } 379 380 return (anar); 381 } 382 383 static int 384 atphy_setmedia(struct mii_softc *sc, int media) 385 { 386 struct atphy_softc *asc; 387 uint16_t anar; 388 389 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 390 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) && 391 ((media & IFM_FLOW) != 0 || 392 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)) 393 anar |= ANAR_PAUSE_TOWARDS; 394 PHY_WRITE(sc, MII_ANAR, anar); 395 if ((sc->mii_extcapabilities & 396 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 397 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 398 GTCR_ADV_1000THDX); 399 else { 400 /* 401 * AR8132 has 10/100 PHY and the PHY uses the same 402 * model number of F1 gigabit PHY. The PHY has no 403 * ability to establish gigabit link so explicitly 404 * disable 1000baseT configuration for the PHY. 405 * Otherwise, there is a case that atphy(4) could 406 * not establish a link against gigabit link partner 407 * unless the link partner supports down-shifting. 408 */ 409 asc = (struct atphy_softc *)sc; 410 if (asc->mii_model == MII_MODEL_ATHEROS_F1) 411 PHY_WRITE(sc, MII_100T2CR, 0); 412 } 413 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 414 415 return (EJUSTRETURN); 416 }
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