FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/brgphy.c
1 /*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
38 * 1000mbps; all we need to negotiate here is full or half duplex.
39 */
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/socket.h>
46 #include <sys/bus.h>
47
48 #include <machine/clock.h>
49
50 #include <net/if.h>
51 #include <net/if_media.h>
52
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56
57 #include <dev/mii/brgphyreg.h>
58 #include <net/if_arp.h>
59 #include <machine/bus.h>
60 #include <dev/bge/if_bgereg.h>
61
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
64
65 #include "miibus_if.h"
66
67 static int brgphy_probe(device_t);
68 static int brgphy_attach(device_t);
69
70 static device_method_t brgphy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, brgphy_probe),
73 DEVMETHOD(device_attach, brgphy_attach),
74 DEVMETHOD(device_detach, mii_phy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 { 0, 0 }
77 };
78
79 static devclass_t brgphy_devclass;
80
81 static driver_t brgphy_driver = {
82 "brgphy",
83 brgphy_methods,
84 sizeof(struct mii_softc)
85 };
86
87 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
88
89 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
90 static void brgphy_status(struct mii_softc *);
91 static int brgphy_mii_phy_auto(struct mii_softc *);
92 static void brgphy_reset(struct mii_softc *);
93 static void brgphy_loop(struct mii_softc *);
94 static void bcm5401_load_dspcode(struct mii_softc *);
95 static void bcm5411_load_dspcode(struct mii_softc *);
96 static void bcm5703_load_dspcode(struct mii_softc *);
97 static void bcm5750_load_dspcode(struct mii_softc *);
98 static int brgphy_mii_model;
99
100 static int
101 brgphy_probe(dev)
102 device_t dev;
103 {
104 struct mii_attach_args *ma;
105
106 ma = device_get_ivars(dev);
107
108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) {
110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400);
111 return(0);
112 }
113
114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) {
116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401);
117 return(0);
118 }
119
120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) {
122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411);
123 return(0);
124 }
125
126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
129 return(0);
130 }
131
132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) {
134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703);
135 return(0);
136 }
137
138 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
139 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) {
140 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704);
141 return(0);
142 }
143
144 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
145 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) {
146 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705);
147 return(0);
148 }
149
150 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
151 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) {
152 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750);
153 return(0);
154 }
155
156 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
157 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) {
158 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714);
159 return(0);
160 }
161
162 return(ENXIO);
163 }
164
165 static int
166 brgphy_attach(dev)
167 device_t dev;
168 {
169 struct mii_softc *sc;
170 struct mii_attach_args *ma;
171 struct mii_data *mii;
172 const char *sep = "";
173 struct bge_softc *bge_sc;
174 int fast_ether_only = FALSE;
175
176 sc = device_get_softc(dev);
177 ma = device_get_ivars(dev);
178 sc->mii_dev = device_get_parent(dev);
179 mii = device_get_softc(sc->mii_dev);
180 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
181
182 sc->mii_inst = mii->mii_instance;
183 sc->mii_phy = ma->mii_phyno;
184 sc->mii_service = brgphy_service;
185 sc->mii_pdata = mii;
186
187 sc->mii_flags |= MIIF_NOISOLATE;
188 mii->mii_instance++;
189
190 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
191 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
192
193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
194 BMCR_ISO);
195 #if 0
196 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
197 BMCR_LOOP|BMCR_S100);
198 #endif
199
200 brgphy_mii_model = MII_MODEL(ma->mii_id2);
201 brgphy_reset(sc);
202
203
204 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
205 sc->mii_capabilities &= ~BMSR_ANEG;
206 device_printf(dev, " ");
207 mii_add_media(sc);
208
209 /* The 590x chips are 10/100 only. */
210
211 bge_sc = mii->mii_ifp->if_softc;
212
213 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
214 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
215 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
216 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
217 fast_ether_only = TRUE;
218
219 if (fast_ether_only == FALSE) {
220 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
221 sc->mii_inst), BRGPHY_BMCR_FDX);
222 PRINT(", 1000baseTX");
223 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
224 IFM_FDX, sc->mii_inst), 0);
225 PRINT("1000baseTX-FDX");
226 }
227
228 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
229 PRINT("auto");
230
231 printf("\n");
232 #undef ADD
233 #undef PRINT
234
235 MIIBUS_MEDIAINIT(sc->mii_dev);
236 return(0);
237 }
238
239 static int
240 brgphy_service(sc, mii, cmd)
241 struct mii_softc *sc;
242 struct mii_data *mii;
243 int cmd;
244 {
245 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
246 int reg, speed, gig;
247
248 switch (cmd) {
249 case MII_POLLSTAT:
250 /*
251 * If we're not polling our PHY instance, just return.
252 */
253 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
254 return (0);
255 break;
256
257 case MII_MEDIACHG:
258 /*
259 * If the media indicates a different PHY instance,
260 * isolate ourselves.
261 */
262 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
263 reg = PHY_READ(sc, MII_BMCR);
264 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
265 return (0);
266 }
267
268 /*
269 * If the interface is not up, don't do anything.
270 */
271 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
272 break;
273
274 brgphy_reset(sc); /* XXX hardware bug work-around */
275
276 switch (IFM_SUBTYPE(ife->ifm_media)) {
277 case IFM_AUTO:
278 #ifdef foo
279 /*
280 * If we're already in auto mode, just return.
281 */
282 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
283 return (0);
284 #endif
285 (void) brgphy_mii_phy_auto(sc);
286 break;
287 case IFM_1000_T:
288 speed = BRGPHY_S1000;
289 goto setit;
290 case IFM_100_TX:
291 speed = BRGPHY_S100;
292 goto setit;
293 case IFM_10_T:
294 speed = BRGPHY_S10;
295 setit:
296 brgphy_loop(sc);
297 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
298 speed |= BRGPHY_BMCR_FDX;
299 gig = BRGPHY_1000CTL_AFD;
300 } else {
301 gig = BRGPHY_1000CTL_AHD;
302 }
303
304 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
305 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
306 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
307
308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
309 break;
310
311 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
312 PHY_WRITE(sc, BRGPHY_MII_BMCR,
313 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
314
315 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
316 break;
317
318 /*
319 * When settning the link manually, one side must
320 * be the master and the other the slave. However
321 * ifmedia doesn't give us a good way to specify
322 * this, so we fake it by using one of the LINK
323 * flags. If LINK0 is set, we program the PHY to
324 * be a master, otherwise it's a slave.
325 */
326 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
327 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
328 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
329 } else {
330 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
331 gig|BRGPHY_1000CTL_MSE);
332 }
333 break;
334 #ifdef foo
335 case IFM_NONE:
336 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
337 break;
338 #endif
339 case IFM_100_T4:
340 default:
341 return (EINVAL);
342 }
343 break;
344
345 case MII_TICK:
346 /*
347 * If we're not currently selected, just return.
348 */
349 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
350 return (0);
351
352 /*
353 * Is the interface even up?
354 */
355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
356 return (0);
357
358 /*
359 * Only used for autonegotiation.
360 */
361 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
362 break;
363
364 /*
365 * Check to see if we have link. If we do, we don't
366 * need to restart the autonegotiation process. Read
367 * the BMSR twice in case it's latched.
368 */
369 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
370 if (reg & BRGPHY_AUXSTS_LINK)
371 break;
372
373 /*
374 * Only retry autonegotiation every 5 seconds.
375 */
376 if (++sc->mii_ticks <= 5)
377 break;
378
379 sc->mii_ticks = 0;
380 brgphy_mii_phy_auto(sc);
381 return (0);
382 }
383
384 /* Update the media status. */
385 brgphy_status(sc);
386
387 /*
388 * Callback if something changed. Note that we need to poke
389 * the DSP on the Broadcom PHYs if the media changes.
390 *
391 */
392 if (sc->mii_media_active != mii->mii_media_active ||
393 sc->mii_media_status != mii->mii_media_status ||
394 cmd == MII_MEDIACHG) {
395 switch (brgphy_mii_model) {
396 case MII_MODEL_xxBROADCOM_BCM5401:
397 bcm5401_load_dspcode(sc);
398 break;
399 case MII_MODEL_xxBROADCOM_BCM5411:
400 bcm5411_load_dspcode(sc);
401 break;
402 }
403 }
404 mii_phy_update(sc, cmd);
405 return (0);
406 }
407
408 static void
409 brgphy_status(sc)
410 struct mii_softc *sc;
411 {
412 struct mii_data *mii = sc->mii_pdata;
413 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
414 int bmsr, bmcr;
415
416 mii->mii_media_status = IFM_AVALID;
417 mii->mii_media_active = IFM_ETHER;
418
419 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
420 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
421 mii->mii_media_status |= IFM_ACTIVE;
422
423 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
424
425 if (bmcr & BRGPHY_BMCR_LOOP)
426 mii->mii_media_active |= IFM_LOOP;
427
428 if (bmcr & BRGPHY_BMCR_AUTOEN) {
429 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
430 /* Erg, still trying, I guess... */
431 mii->mii_media_active |= IFM_NONE;
432 return;
433 }
434
435 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
436 BRGPHY_AUXSTS_AN_RES) {
437 case BRGPHY_RES_1000FD:
438 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
439 break;
440 case BRGPHY_RES_1000HD:
441 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
442 break;
443 case BRGPHY_RES_100FD:
444 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
445 break;
446 case BRGPHY_RES_100T4:
447 mii->mii_media_active |= IFM_100_T4;
448 break;
449 case BRGPHY_RES_100HD:
450 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
451 break;
452 case BRGPHY_RES_10FD:
453 mii->mii_media_active |= IFM_10_T | IFM_FDX;
454 break;
455 case BRGPHY_RES_10HD:
456 mii->mii_media_active |= IFM_10_T | IFM_HDX;
457 break;
458 default:
459 mii->mii_media_active |= IFM_NONE;
460 break;
461 }
462 return;
463 }
464
465 mii->mii_media_active = ife->ifm_media;
466
467 return;
468 }
469
470
471 static int
472 brgphy_mii_phy_auto(mii)
473 struct mii_softc *mii;
474 {
475 int ktcr = 0;
476
477 brgphy_loop(mii);
478 brgphy_reset(mii);
479 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
480 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
481 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
482 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
483 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
484 DELAY(1000);
485 PHY_WRITE(mii, BRGPHY_MII_ANAR,
486 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
487 DELAY(1000);
488 PHY_WRITE(mii, BRGPHY_MII_BMCR,
489 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
490 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
491 return (EJUSTRETURN);
492 }
493
494 static void
495 brgphy_loop(struct mii_softc *sc)
496 {
497 u_int32_t bmsr;
498 int i;
499
500 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
501 for (i = 0; i < 15000; i++) {
502 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
503 if (!(bmsr & BRGPHY_BMSR_LINK)) {
504 #if 0
505 device_printf(sc->mii_dev, "looped %d\n", i);
506 #endif
507 break;
508 }
509 DELAY(10);
510 }
511 }
512
513 /* Turn off tap power management on 5401. */
514 static void
515 bcm5401_load_dspcode(struct mii_softc *sc)
516 {
517 static const struct {
518 int reg;
519 uint16_t val;
520 } dspcode[] = {
521 { BRGPHY_MII_AUXCTL, 0x0c20 },
522 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
523 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
524 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
525 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
526 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
527 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
528 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
529 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
530 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
531 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
532 { 0, 0 },
533 };
534 int i;
535
536 for (i = 0; dspcode[i].reg != 0; i++)
537 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
538 DELAY(40);
539 }
540
541 static void
542 bcm5411_load_dspcode(struct mii_softc *sc)
543 {
544 static const struct {
545 int reg;
546 uint16_t val;
547 } dspcode[] = {
548 { 0x1c, 0x8c23 },
549 { 0x1c, 0x8ca3 },
550 { 0x1c, 0x8c23 },
551 { 0, 0 },
552 };
553 int i;
554
555 for (i = 0; dspcode[i].reg != 0; i++)
556 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
557 }
558
559 static void
560 bcm5703_load_dspcode(struct mii_softc *sc)
561 {
562 static const struct {
563 int reg;
564 uint16_t val;
565 } dspcode[] = {
566 { BRGPHY_MII_AUXCTL, 0x0c00 },
567 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
568 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
569 { 0, 0 },
570 };
571 int i;
572
573 for (i = 0; dspcode[i].reg != 0; i++)
574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
575 }
576
577 static void
578 bcm5704_load_dspcode(struct mii_softc *sc)
579 {
580 static const struct {
581 int reg;
582 u_int16_t val;
583 } dspcode[] = {
584 { 0x1c, 0x8d68 },
585 { 0x1c, 0x8d68 },
586 { 0, 0 },
587 };
588 int i;
589
590 for (i = 0; dspcode[i].reg != 0; i++)
591 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
592 }
593
594 static void
595 bcm5750_load_dspcode(struct mii_softc *sc)
596 {
597 static const struct {
598 int reg;
599 u_int16_t val;
600 } dspcode[] = {
601 { 0x18, 0x0c00 },
602 { 0x17, 0x000a },
603 { 0x15, 0x310b },
604 { 0x17, 0x201f },
605 { 0x15, 0x9506 },
606 { 0x17, 0x401f },
607 { 0x15, 0x14e2 },
608 { 0x18, 0x0400 },
609 { 0, 0 },
610 };
611 int i;
612
613 for (i = 0; dspcode[i].reg != 0; i++)
614 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
615 }
616
617 static void
618 brgphy_reset(struct mii_softc *sc)
619 {
620 u_int32_t val;
621 struct ifnet *ifp;
622 struct bge_softc *bge_sc;
623
624 mii_phy_reset(sc);
625
626 switch (brgphy_mii_model) {
627 case MII_MODEL_xxBROADCOM_BCM5401:
628 bcm5401_load_dspcode(sc);
629 break;
630 case MII_MODEL_xxBROADCOM_BCM5411:
631 bcm5411_load_dspcode(sc);
632 break;
633 case MII_MODEL_xxBROADCOM_BCM5703:
634 bcm5703_load_dspcode(sc);
635 break;
636 case MII_MODEL_xxBROADCOM_BCM5704:
637 bcm5704_load_dspcode(sc);
638 break;
639 case MII_MODEL_xxBROADCOM_BCM5750:
640 case MII_MODEL_xxBROADCOM_BCM5714:
641 bcm5750_load_dspcode(sc);
642 break;
643 }
644
645 ifp = sc->mii_pdata->mii_ifp;
646 bge_sc = ifp->if_softc;
647
648 /*
649 * Don't enable Ethernet@WireSpeed for the 5700 or the
650 * 5705 A1 and A2 chips. Make sure we only do this test
651 * on "bge" NICs, since other drivers may use this same
652 * PHY subdriver.
653 */
654 if (strcmp(ifp->if_dname, "bge") == 0 &&
655 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
656 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
657 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
658 return;
659
660 /* Enable Ethernet@WireSpeed. */
661 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
662 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
663 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
664
665 /* Enable Link LED on Dell boxes */
666 if (bge_sc->bge_no_3_led) {
667 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
668 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
669 & ~BRGPHY_PHY_EXTCTL_3_LED);
670 }
671 }
Cache object: 460b40d7a98f3af158d66a4fe27a75ef
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