Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/mii/brgphy.c
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1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.0/sys/dev/mii/brgphy.c 151778 2005-10-28 01:07:54Z grehan $"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include "miibus_if.h" 66 67 static int brgphy_probe(device_t); 68 static int brgphy_attach(device_t); 69 70 static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static devclass_t brgphy_devclass; 80 81 static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85 }; 86 87 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90 static void brgphy_status(struct mii_softc *); 91 static int brgphy_mii_phy_auto(struct mii_softc *); 92 static void brgphy_reset(struct mii_softc *); 93 static void brgphy_loop(struct mii_softc *); 94 static void bcm5401_load_dspcode(struct mii_softc *); 95 static void bcm5411_load_dspcode(struct mii_softc *); 96 static void bcm5703_load_dspcode(struct mii_softc *); 97 static void bcm5750_load_dspcode(struct mii_softc *); 98 static int brgphy_mii_model; 99 100 static int 101 brgphy_probe(dev) 102 device_t dev; 103 { 104 struct mii_attach_args *ma; 105 106 ma = device_get_ivars(dev); 107 108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 111 return(0); 112 } 113 114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 117 return(0); 118 } 119 120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 123 return(0); 124 } 125 126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 129 return(0); 130 } 131 132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 135 return(0); 136 } 137 138 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 139 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 140 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 141 return(0); 142 } 143 144 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 145 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 146 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 147 return(0); 148 } 149 150 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 151 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 152 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 153 return(0); 154 } 155 156 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 157 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) { 158 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714); 159 return(0); 160 } 161 162 return(ENXIO); 163 } 164 165 static int 166 brgphy_attach(dev) 167 device_t dev; 168 { 169 struct mii_softc *sc; 170 struct mii_attach_args *ma; 171 struct mii_data *mii; 172 const char *sep = ""; 173 struct bge_softc *bge_sc; 174 int fast_ether_only = FALSE; 175 176 sc = device_get_softc(dev); 177 ma = device_get_ivars(dev); 178 sc->mii_dev = device_get_parent(dev); 179 mii = device_get_softc(sc->mii_dev); 180 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 181 182 sc->mii_inst = mii->mii_instance; 183 sc->mii_phy = ma->mii_phyno; 184 sc->mii_service = brgphy_service; 185 sc->mii_pdata = mii; 186 187 sc->mii_flags |= MIIF_NOISOLATE; 188 mii->mii_instance++; 189 190 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 191 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 192 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 194 BMCR_ISO); 195 #if 0 196 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 197 BMCR_LOOP|BMCR_S100); 198 #endif 199 200 brgphy_mii_model = MII_MODEL(ma->mii_id2); 201 brgphy_reset(sc); 202 203 204 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 205 sc->mii_capabilities &= ~BMSR_ANEG; 206 device_printf(dev, " "); 207 mii_add_media(sc); 208 209 /* The 590x chips are 10/100 only. */ 210 211 bge_sc = mii->mii_ifp->if_softc; 212 213 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 214 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 215 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 216 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 217 fast_ether_only = TRUE; 218 219 if (fast_ether_only == FALSE) { 220 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 221 sc->mii_inst), BRGPHY_BMCR_FDX); 222 PRINT(", 1000baseTX"); 223 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 224 IFM_FDX, sc->mii_inst), 0); 225 PRINT("1000baseTX-FDX"); 226 } 227 228 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 229 PRINT("auto"); 230 231 printf("\n"); 232 #undef ADD 233 #undef PRINT 234 235 MIIBUS_MEDIAINIT(sc->mii_dev); 236 return(0); 237 } 238 239 static int 240 brgphy_service(sc, mii, cmd) 241 struct mii_softc *sc; 242 struct mii_data *mii; 243 int cmd; 244 { 245 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 246 int reg, speed, gig; 247 248 switch (cmd) { 249 case MII_POLLSTAT: 250 /* 251 * If we're not polling our PHY instance, just return. 252 */ 253 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 254 return (0); 255 break; 256 257 case MII_MEDIACHG: 258 /* 259 * If the media indicates a different PHY instance, 260 * isolate ourselves. 261 */ 262 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 263 reg = PHY_READ(sc, MII_BMCR); 264 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 265 return (0); 266 } 267 268 /* 269 * If the interface is not up, don't do anything. 270 */ 271 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 272 break; 273 274 brgphy_reset(sc); /* XXX hardware bug work-around */ 275 276 switch (IFM_SUBTYPE(ife->ifm_media)) { 277 case IFM_AUTO: 278 #ifdef foo 279 /* 280 * If we're already in auto mode, just return. 281 */ 282 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 283 return (0); 284 #endif 285 (void) brgphy_mii_phy_auto(sc); 286 break; 287 case IFM_1000_T: 288 speed = BRGPHY_S1000; 289 goto setit; 290 case IFM_100_TX: 291 speed = BRGPHY_S100; 292 goto setit; 293 case IFM_10_T: 294 speed = BRGPHY_S10; 295 setit: 296 brgphy_loop(sc); 297 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 298 speed |= BRGPHY_BMCR_FDX; 299 gig = BRGPHY_1000CTL_AFD; 300 } else { 301 gig = BRGPHY_1000CTL_AHD; 302 } 303 304 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 305 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 306 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 307 308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 309 break; 310 311 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 312 PHY_WRITE(sc, BRGPHY_MII_BMCR, 313 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 314 315 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 316 break; 317 318 /* 319 * When settning the link manually, one side must 320 * be the master and the other the slave. However 321 * ifmedia doesn't give us a good way to specify 322 * this, so we fake it by using one of the LINK 323 * flags. If LINK0 is set, we program the PHY to 324 * be a master, otherwise it's a slave. 325 */ 326 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 327 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 328 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 329 } else { 330 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 331 gig|BRGPHY_1000CTL_MSE); 332 } 333 break; 334 #ifdef foo 335 case IFM_NONE: 336 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 337 break; 338 #endif 339 case IFM_100_T4: 340 default: 341 return (EINVAL); 342 } 343 break; 344 345 case MII_TICK: 346 /* 347 * If we're not currently selected, just return. 348 */ 349 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 350 return (0); 351 352 /* 353 * Is the interface even up? 354 */ 355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 356 return (0); 357 358 /* 359 * Only used for autonegotiation. 360 */ 361 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 362 break; 363 364 /* 365 * Check to see if we have link. If we do, we don't 366 * need to restart the autonegotiation process. Read 367 * the BMSR twice in case it's latched. 368 */ 369 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 370 if (reg & BRGPHY_AUXSTS_LINK) 371 break; 372 373 /* 374 * Only retry autonegotiation every 5 seconds. 375 */ 376 if (++sc->mii_ticks <= 5) 377 break; 378 379 sc->mii_ticks = 0; 380 brgphy_mii_phy_auto(sc); 381 return (0); 382 } 383 384 /* Update the media status. */ 385 brgphy_status(sc); 386 387 /* 388 * Callback if something changed. Note that we need to poke 389 * the DSP on the Broadcom PHYs if the media changes. 390 * 391 */ 392 if (sc->mii_media_active != mii->mii_media_active || 393 sc->mii_media_status != mii->mii_media_status || 394 cmd == MII_MEDIACHG) { 395 switch (brgphy_mii_model) { 396 case MII_MODEL_xxBROADCOM_BCM5400: 397 case MII_MODEL_xxBROADCOM_BCM5401: 398 bcm5401_load_dspcode(sc); 399 break; 400 case MII_MODEL_xxBROADCOM_BCM5411: 401 bcm5411_load_dspcode(sc); 402 break; 403 } 404 } 405 mii_phy_update(sc, cmd); 406 return (0); 407 } 408 409 static void 410 brgphy_status(sc) 411 struct mii_softc *sc; 412 { 413 struct mii_data *mii = sc->mii_pdata; 414 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 415 int bmsr, bmcr; 416 417 mii->mii_media_status = IFM_AVALID; 418 mii->mii_media_active = IFM_ETHER; 419 420 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 421 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 422 mii->mii_media_status |= IFM_ACTIVE; 423 424 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 425 426 if (bmcr & BRGPHY_BMCR_LOOP) 427 mii->mii_media_active |= IFM_LOOP; 428 429 if (bmcr & BRGPHY_BMCR_AUTOEN) { 430 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 431 /* Erg, still trying, I guess... */ 432 mii->mii_media_active |= IFM_NONE; 433 return; 434 } 435 436 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 437 BRGPHY_AUXSTS_AN_RES) { 438 case BRGPHY_RES_1000FD: 439 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 440 break; 441 case BRGPHY_RES_1000HD: 442 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 443 break; 444 case BRGPHY_RES_100FD: 445 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 446 break; 447 case BRGPHY_RES_100T4: 448 mii->mii_media_active |= IFM_100_T4; 449 break; 450 case BRGPHY_RES_100HD: 451 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 452 break; 453 case BRGPHY_RES_10FD: 454 mii->mii_media_active |= IFM_10_T | IFM_FDX; 455 break; 456 case BRGPHY_RES_10HD: 457 mii->mii_media_active |= IFM_10_T | IFM_HDX; 458 break; 459 default: 460 mii->mii_media_active |= IFM_NONE; 461 break; 462 } 463 return; 464 } 465 466 mii->mii_media_active = ife->ifm_media; 467 468 return; 469 } 470 471 472 static int 473 brgphy_mii_phy_auto(mii) 474 struct mii_softc *mii; 475 { 476 int ktcr = 0; 477 478 brgphy_loop(mii); 479 brgphy_reset(mii); 480 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 481 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 482 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 483 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 484 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 485 DELAY(1000); 486 PHY_WRITE(mii, BRGPHY_MII_ANAR, 487 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 488 DELAY(1000); 489 PHY_WRITE(mii, BRGPHY_MII_BMCR, 490 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 491 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 492 return (EJUSTRETURN); 493 } 494 495 static void 496 brgphy_loop(struct mii_softc *sc) 497 { 498 u_int32_t bmsr; 499 int i; 500 501 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 502 for (i = 0; i < 15000; i++) { 503 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 504 if (!(bmsr & BRGPHY_BMSR_LINK)) { 505 #if 0 506 device_printf(sc->mii_dev, "looped %d\n", i); 507 #endif 508 break; 509 } 510 DELAY(10); 511 } 512 } 513 514 /* Turn off tap power management on 5401. */ 515 static void 516 bcm5401_load_dspcode(struct mii_softc *sc) 517 { 518 static const struct { 519 int reg; 520 uint16_t val; 521 } dspcode[] = { 522 { BRGPHY_MII_AUXCTL, 0x0c20 }, 523 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 524 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 525 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 526 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 527 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 528 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 529 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 530 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 531 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 532 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 533 { 0, 0 }, 534 }; 535 int i; 536 537 for (i = 0; dspcode[i].reg != 0; i++) 538 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 539 DELAY(40); 540 } 541 542 static void 543 bcm5411_load_dspcode(struct mii_softc *sc) 544 { 545 static const struct { 546 int reg; 547 uint16_t val; 548 } dspcode[] = { 549 { 0x1c, 0x8c23 }, 550 { 0x1c, 0x8ca3 }, 551 { 0x1c, 0x8c23 }, 552 { 0, 0 }, 553 }; 554 int i; 555 556 for (i = 0; dspcode[i].reg != 0; i++) 557 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 558 } 559 560 static void 561 bcm5703_load_dspcode(struct mii_softc *sc) 562 { 563 static const struct { 564 int reg; 565 uint16_t val; 566 } dspcode[] = { 567 { BRGPHY_MII_AUXCTL, 0x0c00 }, 568 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 569 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 570 { 0, 0 }, 571 }; 572 int i; 573 574 for (i = 0; dspcode[i].reg != 0; i++) 575 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 576 } 577 578 static void 579 bcm5704_load_dspcode(struct mii_softc *sc) 580 { 581 static const struct { 582 int reg; 583 u_int16_t val; 584 } dspcode[] = { 585 { 0x1c, 0x8d68 }, 586 { 0x1c, 0x8d68 }, 587 { 0, 0 }, 588 }; 589 int i; 590 591 for (i = 0; dspcode[i].reg != 0; i++) 592 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 593 } 594 595 static void 596 bcm5750_load_dspcode(struct mii_softc *sc) 597 { 598 static const struct { 599 int reg; 600 u_int16_t val; 601 } dspcode[] = { 602 { 0x18, 0x0c00 }, 603 { 0x17, 0x000a }, 604 { 0x15, 0x310b }, 605 { 0x17, 0x201f }, 606 { 0x15, 0x9506 }, 607 { 0x17, 0x401f }, 608 { 0x15, 0x14e2 }, 609 { 0x18, 0x0400 }, 610 { 0, 0 }, 611 }; 612 int i; 613 614 for (i = 0; dspcode[i].reg != 0; i++) 615 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 616 } 617 618 static void 619 brgphy_reset(struct mii_softc *sc) 620 { 621 u_int32_t val; 622 struct ifnet *ifp; 623 struct bge_softc *bge_sc; 624 625 mii_phy_reset(sc); 626 627 switch (brgphy_mii_model) { 628 case MII_MODEL_xxBROADCOM_BCM5400: 629 case MII_MODEL_xxBROADCOM_BCM5401: 630 bcm5401_load_dspcode(sc); 631 break; 632 case MII_MODEL_xxBROADCOM_BCM5411: 633 bcm5411_load_dspcode(sc); 634 break; 635 case MII_MODEL_xxBROADCOM_BCM5703: 636 bcm5703_load_dspcode(sc); 637 break; 638 case MII_MODEL_xxBROADCOM_BCM5704: 639 bcm5704_load_dspcode(sc); 640 break; 641 case MII_MODEL_xxBROADCOM_BCM5750: 642 case MII_MODEL_xxBROADCOM_BCM5714: 643 bcm5750_load_dspcode(sc); 644 break; 645 } 646 647 ifp = sc->mii_pdata->mii_ifp; 648 bge_sc = ifp->if_softc; 649 650 /* 651 * Don't enable Ethernet@WireSpeed for the 5700 or the 652 * 5705 A1 and A2 chips. Make sure we only do this test 653 * on "bge" NICs, since other drivers may use this same 654 * PHY subdriver. 655 */ 656 if (strcmp(ifp->if_dname, "bge") == 0 && 657 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 658 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 659 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 660 return; 661 662 /* Enable Ethernet@WireSpeed. */ 663 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 664 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 665 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 666 667 /* Enable Link LED on Dell boxes */ 668 if (bge_sc->bge_no_3_led) { 669 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 670 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 671 & ~BRGPHY_PHY_EXTCTL_3_LED); 672 } 673 }
Cache object: 012953a43ff69d43a1470d53a6b0becb
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