FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/brgphy.c
1 /*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/8.2/sys/dev/mii/brgphy.c 215884 2010-11-26 20:55:58Z marius $");
35
36 /*
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46
47 #include <net/if.h>
48 #include <net/ethernet.h>
49 #include <net/if_media.h>
50
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include "miidevs.h"
54
55 #include <dev/mii/brgphyreg.h>
56 #include <net/if_arp.h>
57 #include <machine/bus.h>
58 #include <dev/bge/if_bgereg.h>
59 #include <dev/bce/if_bcereg.h>
60
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63
64 #include "miibus_if.h"
65
66 static int brgphy_probe(device_t);
67 static int brgphy_attach(device_t);
68
69 struct brgphy_softc {
70 struct mii_softc mii_sc;
71 int mii_oui;
72 int mii_model;
73 int mii_rev;
74 int serdes_flags; /* Keeps track of the serdes type used */
75 #define BRGPHY_5706S 0x0001
76 #define BRGPHY_5708S 0x0002
77 #define BRGPHY_NOANWAIT 0x0004
78 #define BRGPHY_5709S 0x0008
79 int bce_phy_flags; /* PHY flags transferred from the MAC driver */
80 };
81
82 static device_method_t brgphy_methods[] = {
83 /* device interface */
84 DEVMETHOD(device_probe, brgphy_probe),
85 DEVMETHOD(device_attach, brgphy_attach),
86 DEVMETHOD(device_detach, mii_phy_detach),
87 DEVMETHOD(device_shutdown, bus_generic_shutdown),
88 { 0, 0 }
89 };
90
91 static devclass_t brgphy_devclass;
92
93 static driver_t brgphy_driver = {
94 "brgphy",
95 brgphy_methods,
96 sizeof(struct brgphy_softc)
97 };
98
99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
100
101 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
102 static void brgphy_setmedia(struct mii_softc *, int);
103 static void brgphy_status(struct mii_softc *);
104 static void brgphy_mii_phy_auto(struct mii_softc *, int);
105 static void brgphy_reset(struct mii_softc *);
106 static void brgphy_enable_loopback(struct mii_softc *);
107 static void bcm5401_load_dspcode(struct mii_softc *);
108 static void bcm5411_load_dspcode(struct mii_softc *);
109 static void bcm54k2_load_dspcode(struct mii_softc *);
110 static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
111 static void brgphy_fixup_adc_bug(struct mii_softc *);
112 static void brgphy_fixup_adjust_trim(struct mii_softc *);
113 static void brgphy_fixup_ber_bug(struct mii_softc *);
114 static void brgphy_fixup_crc_bug(struct mii_softc *);
115 static void brgphy_fixup_jitter_bug(struct mii_softc *);
116 static void brgphy_ethernet_wirespeed(struct mii_softc *);
117 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
118
119 static const struct mii_phydesc brgphys[] = {
120 MII_PHY_DESC(xxBROADCOM, BCM5400),
121 MII_PHY_DESC(xxBROADCOM, BCM5401),
122 MII_PHY_DESC(xxBROADCOM, BCM5411),
123 MII_PHY_DESC(xxBROADCOM, BCM54K2),
124 MII_PHY_DESC(xxBROADCOM, BCM5701),
125 MII_PHY_DESC(xxBROADCOM, BCM5703),
126 MII_PHY_DESC(xxBROADCOM, BCM5704),
127 MII_PHY_DESC(xxBROADCOM, BCM5705),
128 MII_PHY_DESC(xxBROADCOM, BCM5706),
129 MII_PHY_DESC(xxBROADCOM, BCM5714),
130 MII_PHY_DESC(xxBROADCOM, BCM5750),
131 MII_PHY_DESC(xxBROADCOM, BCM5752),
132 MII_PHY_DESC(xxBROADCOM, BCM5754),
133 MII_PHY_DESC(xxBROADCOM, BCM5780),
134 MII_PHY_DESC(xxBROADCOM, BCM5708C),
135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
144 MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C),
145 MII_PHY_DESC(BROADCOM2, BCM5906),
146 MII_PHY_END
147 };
148
149 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
150 #define HS21_BCM_CHIPID 0x57081021
151
152 static int
153 detect_hs21(struct bce_softc *bce_sc)
154 {
155 char *sysenv;
156 int found;
157
158 found = 0;
159 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
160 sysenv = getenv("smbios.system.product");
161 if (sysenv != NULL) {
162 if (strncmp(sysenv, HS21_PRODUCT_ID,
163 strlen(HS21_PRODUCT_ID)) == 0)
164 found = 1;
165 freeenv(sysenv);
166 }
167 }
168 return (found);
169 }
170
171 /* Search for our PHY in the list of known PHYs */
172 static int
173 brgphy_probe(device_t dev)
174 {
175
176 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
177 }
178
179 /* Attach the PHY to the MII bus */
180 static int
181 brgphy_attach(device_t dev)
182 {
183 struct brgphy_softc *bsc;
184 struct bge_softc *bge_sc = NULL;
185 struct bce_softc *bce_sc = NULL;
186 struct mii_softc *sc;
187 struct mii_attach_args *ma;
188 struct mii_data *mii;
189 struct ifnet *ifp;
190
191 bsc = device_get_softc(dev);
192 sc = &bsc->mii_sc;
193 ma = device_get_ivars(dev);
194 sc->mii_dev = device_get_parent(dev);
195 mii = ma->mii_data;
196 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
197
198 /* Initialize mii_softc structure */
199 sc->mii_flags = miibus_get_flags(dev);
200 sc->mii_inst = mii->mii_instance++;
201 sc->mii_phy = ma->mii_phyno;
202 sc->mii_service = brgphy_service;
203 sc->mii_pdata = mii;
204
205 /*
206 * At least some variants wedge when isolating, at least some also
207 * don't support loopback.
208 */
209 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
210
211 /* Initialize brgphy_softc structure */
212 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
213 bsc->mii_model = MII_MODEL(ma->mii_id2);
214 bsc->mii_rev = MII_REV(ma->mii_id2);
215 bsc->serdes_flags = 0;
216
217 if (bootverbose)
218 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
219 bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
220
221 /* Handle any special cases based on the PHY ID */
222 switch (bsc->mii_oui) {
223 case MII_OUI_BROADCOM:
224 case MII_OUI_BROADCOM2:
225 break;
226 case MII_OUI_xxBROADCOM:
227 switch (bsc->mii_model) {
228 case MII_MODEL_xxBROADCOM_BCM5706:
229 case MII_MODEL_xxBROADCOM_BCM5714:
230 /*
231 * The 5464 PHY used in the 5706 supports both copper
232 * and fiber interfaces over GMII. Need to check the
233 * shadow registers to see which mode is actually
234 * in effect, and therefore whether we have 5706C or
235 * 5706S.
236 */
237 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
238 BRGPHY_SHADOW_1C_MODE_CTRL);
239 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
240 BRGPHY_SHADOW_1C_ENA_1000X) {
241 bsc->serdes_flags |= BRGPHY_5706S;
242 sc->mii_flags |= MIIF_HAVEFIBER;
243 }
244 break;
245 } break;
246 case MII_OUI_xxBROADCOM_ALT1:
247 switch (bsc->mii_model) {
248 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
249 bsc->serdes_flags |= BRGPHY_5708S;
250 sc->mii_flags |= MIIF_HAVEFIBER;
251 break;
252 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
253 bsc->serdes_flags |= BRGPHY_5709S;
254 sc->mii_flags |= MIIF_HAVEFIBER;
255 break;
256 }
257 break;
258 case MII_OUI_xxBROADCOM_ALT2:
259 /* No special handling yet. */
260 break;
261 default:
262 device_printf(dev, "Unrecognized OUI for PHY!\n");
263 }
264
265 ifp = sc->mii_pdata->mii_ifp;
266
267 /* Find the MAC driver associated with this PHY. */
268 if (strcmp(ifp->if_dname, "bge") == 0) {
269 bge_sc = ifp->if_softc;
270 } else if (strcmp(ifp->if_dname, "bce") == 0) {
271 bce_sc = ifp->if_softc;
272 }
273
274 brgphy_reset(sc);
275
276 /* Read the PHY's capabilities. */
277 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
278 if (sc->mii_capabilities & BMSR_EXTSTAT)
279 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
280 device_printf(dev, " ");
281
282 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
283
284 /* Add the supported media types */
285 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
286 mii_phy_add_media(sc);
287 printf("\n");
288 } else {
289 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
290 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
291 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
292 printf("1000baseSX-FDX, ");
293 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
294 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
295 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
296 printf("2500baseSX-FDX, ");
297 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
298 (detect_hs21(bce_sc) != 0)) {
299 /*
300 * There appears to be certain silicon revision
301 * in IBM HS21 blades that is having issues with
302 * this driver wating for the auto-negotiation to
303 * complete. This happens with a specific chip id
304 * only and when the 1000baseSX-FDX is the only
305 * mode. Workaround this issue since it's unlikely
306 * to be ever addressed.
307 */
308 printf("auto-neg workaround, ");
309 bsc->serdes_flags |= BRGPHY_NOANWAIT;
310 }
311 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
312 printf("auto\n");
313 }
314
315 #undef ADD
316 MIIBUS_MEDIAINIT(sc->mii_dev);
317 return (0);
318 }
319
320 static int
321 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
322 {
323 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
324 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
325 int val;
326
327 switch (cmd) {
328 case MII_POLLSTAT:
329 break;
330 case MII_MEDIACHG:
331 /* If the interface is not up, don't do anything. */
332 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
333 break;
334
335 /* Todo: Why is this here? Is it really needed? */
336 brgphy_reset(sc); /* XXX hardware bug work-around */
337
338 switch (IFM_SUBTYPE(ife->ifm_media)) {
339 case IFM_AUTO:
340 brgphy_mii_phy_auto(sc, ife->ifm_media);
341 break;
342 case IFM_2500_SX:
343 case IFM_1000_SX:
344 case IFM_1000_T:
345 case IFM_100_TX:
346 case IFM_10_T:
347 brgphy_setmedia(sc, ife->ifm_media);
348 break;
349 default:
350 return (EINVAL);
351 }
352 break;
353 case MII_TICK:
354 /* Bail if the interface isn't up. */
355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
356 return (0);
357
358
359 /* Bail if autoneg isn't in process. */
360 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
361 sc->mii_ticks = 0;
362 break;
363 }
364
365 /*
366 * Check to see if we have link. If we do, we don't
367 * need to restart the autonegotiation process.
368 */
369 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
370 if (val & BMSR_LINK) {
371 sc->mii_ticks = 0; /* Reset autoneg timer. */
372 break;
373 }
374
375 /* Announce link loss right after it happens. */
376 if (sc->mii_ticks++ == 0)
377 break;
378
379 /* Only retry autonegotiation every mii_anegticks seconds. */
380 if (sc->mii_ticks <= sc->mii_anegticks)
381 break;
382
383
384 /* Retry autonegotiation */
385 sc->mii_ticks = 0;
386 brgphy_mii_phy_auto(sc, ife->ifm_media);
387 break;
388 }
389
390 /* Update the media status. */
391 brgphy_status(sc);
392
393 /*
394 * Callback if something changed. Note that we need to poke
395 * the DSP on the Broadcom PHYs if the media changes.
396 */
397 if (sc->mii_media_active != mii->mii_media_active ||
398 sc->mii_media_status != mii->mii_media_status ||
399 cmd == MII_MEDIACHG) {
400 switch (bsc->mii_oui) {
401 case MII_OUI_BROADCOM:
402 break;
403 case MII_OUI_xxBROADCOM:
404 switch (bsc->mii_model) {
405 case MII_MODEL_xxBROADCOM_BCM5400:
406 bcm5401_load_dspcode(sc);
407 break;
408 case MII_MODEL_xxBROADCOM_BCM5401:
409 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
410 bcm5401_load_dspcode(sc);
411 break;
412 case MII_MODEL_xxBROADCOM_BCM5411:
413 bcm5411_load_dspcode(sc);
414 break;
415 case MII_MODEL_xxBROADCOM_BCM54K2:
416 bcm54k2_load_dspcode(sc);
417 break;
418 }
419 break;
420 case MII_OUI_xxBROADCOM_ALT1:
421 break;
422 }
423 }
424 mii_phy_update(sc, cmd);
425 return (0);
426 }
427
428 /****************************************************************************/
429 /* Sets the PHY link speed. */
430 /* */
431 /* Returns: */
432 /* None */
433 /****************************************************************************/
434 static void
435 brgphy_setmedia(struct mii_softc *sc, int media)
436 {
437 int bmcr = 0, gig;
438
439 switch (IFM_SUBTYPE(media)) {
440 case IFM_2500_SX:
441 break;
442 case IFM_1000_SX:
443 case IFM_1000_T:
444 bmcr = BRGPHY_S1000;
445 break;
446 case IFM_100_TX:
447 bmcr = BRGPHY_S100;
448 break;
449 case IFM_10_T:
450 default:
451 bmcr = BRGPHY_S10;
452 break;
453 }
454
455 if ((media & IFM_GMASK) == IFM_FDX) {
456 bmcr |= BRGPHY_BMCR_FDX;
457 gig = BRGPHY_1000CTL_AFD;
458 } else {
459 gig = BRGPHY_1000CTL_AHD;
460 }
461
462 /* Force loopback to disconnect PHY from Ethernet medium. */
463 brgphy_enable_loopback(sc);
464
465 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
466 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
467
468 if (IFM_SUBTYPE(media) != IFM_1000_T &&
469 IFM_SUBTYPE(media) != IFM_1000_SX) {
470 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
471 return;
472 }
473
474 if (IFM_SUBTYPE(media) == IFM_1000_T) {
475 gig |= BRGPHY_1000CTL_MSE;
476 if ((media & IFM_ETH_MASTER) != 0 ||
477 (sc->mii_pdata->mii_ifp->if_flags & IFF_LINK0) != 0)
478 gig |= BRGPHY_1000CTL_MSC;
479 }
480 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
481 PHY_WRITE(sc, BRGPHY_MII_BMCR,
482 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
483 }
484
485 /****************************************************************************/
486 /* Set the media status based on the PHY settings. */
487 /* */
488 /* Returns: */
489 /* None */
490 /****************************************************************************/
491 static void
492 brgphy_status(struct mii_softc *sc)
493 {
494 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
495 struct mii_data *mii = sc->mii_pdata;
496 int aux, bmcr, bmsr, val, xstat;
497 u_int flowstat;
498
499 mii->mii_media_status = IFM_AVALID;
500 mii->mii_media_active = IFM_ETHER;
501
502 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
503 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
504
505 if (bmcr & BRGPHY_BMCR_LOOP) {
506 mii->mii_media_active |= IFM_LOOP;
507 }
508
509 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
510 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
511 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
512 /* Erg, still trying, I guess... */
513 mii->mii_media_active |= IFM_NONE;
514 return;
515 }
516
517 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
518 /*
519 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
520 * wedges at least the PHY of BCM5704 (but not others).
521 */
522 flowstat = mii_phy_flowstatus(sc);
523 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
524 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
525
526 /* If copper link is up, get the negotiated speed/duplex. */
527 if (aux & BRGPHY_AUXSTS_LINK) {
528 mii->mii_media_status |= IFM_ACTIVE;
529 switch (aux & BRGPHY_AUXSTS_AN_RES) {
530 case BRGPHY_RES_1000FD:
531 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
532 case BRGPHY_RES_1000HD:
533 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
534 case BRGPHY_RES_100FD:
535 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
536 case BRGPHY_RES_100T4:
537 mii->mii_media_active |= IFM_100_T4; break;
538 case BRGPHY_RES_100HD:
539 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
540 case BRGPHY_RES_10FD:
541 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
542 case BRGPHY_RES_10HD:
543 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
544 default:
545 mii->mii_media_active |= IFM_NONE; break;
546 }
547
548 if ((mii->mii_media_active & IFM_FDX) != 0)
549 mii->mii_media_active |= flowstat;
550
551 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
552 (xstat & BRGPHY_1000STS_MSR) != 0)
553 mii->mii_media_active |= IFM_ETH_MASTER;
554 }
555 } else {
556 /* Todo: Add support for flow control. */
557 /* If serdes link is up, get the negotiated speed/duplex. */
558 if (bmsr & BRGPHY_BMSR_LINK) {
559 mii->mii_media_status |= IFM_ACTIVE;
560 }
561
562 /* Check the link speed/duplex based on the PHY type. */
563 if (bsc->serdes_flags & BRGPHY_5706S) {
564 mii->mii_media_active |= IFM_1000_SX;
565
566 /* If autoneg enabled, read negotiated duplex settings */
567 if (bmcr & BRGPHY_BMCR_AUTOEN) {
568 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
569 if (val & BRGPHY_SERDES_ANAR_FDX)
570 mii->mii_media_active |= IFM_FDX;
571 else
572 mii->mii_media_active |= IFM_HDX;
573 }
574 } else if (bsc->serdes_flags & BRGPHY_5708S) {
575 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
576 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
577
578 /* Check for MRBE auto-negotiated speed results. */
579 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
580 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
581 mii->mii_media_active |= IFM_10_FL; break;
582 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
583 mii->mii_media_active |= IFM_100_FX; break;
584 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
585 mii->mii_media_active |= IFM_1000_SX; break;
586 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
587 mii->mii_media_active |= IFM_2500_SX; break;
588 }
589
590 /* Check for MRBE auto-negotiated duplex results. */
591 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
592 mii->mii_media_active |= IFM_FDX;
593 else
594 mii->mii_media_active |= IFM_HDX;
595 } else if (bsc->serdes_flags & BRGPHY_5709S) {
596 /* Select GP Status Block of the AN MMD, get autoneg results. */
597 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
598 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
599
600 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
601 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
602
603 /* Check for MRBE auto-negotiated speed results. */
604 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
605 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
606 mii->mii_media_active |= IFM_10_FL; break;
607 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
608 mii->mii_media_active |= IFM_100_FX; break;
609 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
610 mii->mii_media_active |= IFM_1000_SX; break;
611 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
612 mii->mii_media_active |= IFM_2500_SX; break;
613 }
614
615 /* Check for MRBE auto-negotiated duplex results. */
616 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
617 mii->mii_media_active |= IFM_FDX;
618 else
619 mii->mii_media_active |= IFM_HDX;
620 }
621 }
622 }
623
624 static void
625 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
626 {
627 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
628 int anar, ktcr = 0;
629
630 brgphy_reset(sc);
631
632 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
633 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
634 if ((media & IFM_FLOW) != 0 ||
635 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
636 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
637 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
638 } else {
639 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
640 if ((media & IFM_FLOW) != 0 ||
641 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
642 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
643 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
644 }
645
646 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
647 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
648 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
649 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
650 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
651
652 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
653 BRGPHY_BMCR_STARTNEG);
654 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
655 }
656
657 /* Enable loopback to force the link down. */
658 static void
659 brgphy_enable_loopback(struct mii_softc *sc)
660 {
661 int i;
662
663 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
664 for (i = 0; i < 15000; i++) {
665 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
666 break;
667 DELAY(10);
668 }
669 }
670
671 /* Turn off tap power management on 5401. */
672 static void
673 bcm5401_load_dspcode(struct mii_softc *sc)
674 {
675 static const struct {
676 int reg;
677 uint16_t val;
678 } dspcode[] = {
679 { BRGPHY_MII_AUXCTL, 0x0c20 },
680 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
681 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
682 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
683 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
684 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
685 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
686 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
687 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
688 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
689 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
690 { 0, 0 },
691 };
692 int i;
693
694 for (i = 0; dspcode[i].reg != 0; i++)
695 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
696 DELAY(40);
697 }
698
699 static void
700 bcm5411_load_dspcode(struct mii_softc *sc)
701 {
702 static const struct {
703 int reg;
704 uint16_t val;
705 } dspcode[] = {
706 { 0x1c, 0x8c23 },
707 { 0x1c, 0x8ca3 },
708 { 0x1c, 0x8c23 },
709 { 0, 0 },
710 };
711 int i;
712
713 for (i = 0; dspcode[i].reg != 0; i++)
714 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
715 }
716
717 void
718 bcm54k2_load_dspcode(struct mii_softc *sc)
719 {
720 static const struct {
721 int reg;
722 uint16_t val;
723 } dspcode[] = {
724 { 4, 0x01e1 },
725 { 9, 0x0300 },
726 { 0, 0 },
727 };
728 int i;
729
730 for (i = 0; dspcode[i].reg != 0; i++)
731 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
732
733 }
734
735 static void
736 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
737 {
738 static const struct {
739 int reg;
740 uint16_t val;
741 } dspcode[] = {
742 { 0x1c, 0x8d68 },
743 { 0x1c, 0x8d68 },
744 { 0, 0 },
745 };
746 int i;
747
748 for (i = 0; dspcode[i].reg != 0; i++)
749 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
750 }
751
752 static void
753 brgphy_fixup_adc_bug(struct mii_softc *sc)
754 {
755 static const struct {
756 int reg;
757 uint16_t val;
758 } dspcode[] = {
759 { BRGPHY_MII_AUXCTL, 0x0c00 },
760 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
761 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
762 { 0, 0 },
763 };
764 int i;
765
766 for (i = 0; dspcode[i].reg != 0; i++)
767 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
768 }
769
770 static void
771 brgphy_fixup_adjust_trim(struct mii_softc *sc)
772 {
773 static const struct {
774 int reg;
775 uint16_t val;
776 } dspcode[] = {
777 { BRGPHY_MII_AUXCTL, 0x0c00 },
778 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
779 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
780 { BRGPHY_MII_TEST1, 0x0014 },
781 { BRGPHY_MII_AUXCTL, 0x0400 },
782 { 0, 0 },
783 };
784 int i;
785
786 for (i = 0; dspcode[i].reg != 0; i++)
787 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
788 }
789
790 static void
791 brgphy_fixup_ber_bug(struct mii_softc *sc)
792 {
793 static const struct {
794 int reg;
795 uint16_t val;
796 } dspcode[] = {
797 { BRGPHY_MII_AUXCTL, 0x0c00 },
798 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
799 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
800 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
801 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
802 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
803 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
804 { BRGPHY_MII_AUXCTL, 0x0400 },
805 { 0, 0 },
806 };
807 int i;
808
809 for (i = 0; dspcode[i].reg != 0; i++)
810 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
811 }
812
813 static void
814 brgphy_fixup_crc_bug(struct mii_softc *sc)
815 {
816 static const struct {
817 int reg;
818 uint16_t val;
819 } dspcode[] = {
820 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
821 { 0x1c, 0x8c68 },
822 { 0x1c, 0x8d68 },
823 { 0x1c, 0x8c68 },
824 { 0, 0 },
825 };
826 int i;
827
828 for (i = 0; dspcode[i].reg != 0; i++)
829 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
830 }
831
832 static void
833 brgphy_fixup_jitter_bug(struct mii_softc *sc)
834 {
835 static const struct {
836 int reg;
837 uint16_t val;
838 } dspcode[] = {
839 { BRGPHY_MII_AUXCTL, 0x0c00 },
840 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
841 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
842 { BRGPHY_MII_AUXCTL, 0x0400 },
843 { 0, 0 },
844 };
845 int i;
846
847 for (i = 0; dspcode[i].reg != 0; i++)
848 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
849 }
850
851 static void
852 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
853 {
854 uint32_t val;
855
856 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
857 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
858 val &= ~(1 << 8);
859 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
860
861 }
862
863 static void
864 brgphy_ethernet_wirespeed(struct mii_softc *sc)
865 {
866 uint32_t val;
867
868 /* Enable Ethernet@WireSpeed. */
869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
870 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
871 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
872 }
873
874 static void
875 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
876 {
877 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
878 uint32_t val;
879
880 /* Set or clear jumbo frame settings in the PHY. */
881 if (mtu > ETHER_MAX_LEN) {
882 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
883 /* BCM5401 PHY cannot read-modify-write. */
884 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
885 } else {
886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
887 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
888 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
889 val | BRGPHY_AUXCTL_LONG_PKT);
890 }
891
892 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
893 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
894 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
895 } else {
896 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
897 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
898 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
899 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
900
901 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
902 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
903 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
904 }
905 }
906
907 static void
908 brgphy_reset(struct mii_softc *sc)
909 {
910 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
911 struct bge_softc *bge_sc = NULL;
912 struct bce_softc *bce_sc = NULL;
913 struct ifnet *ifp;
914 int val;
915
916 /* Perform a standard PHY reset. */
917 mii_phy_reset(sc);
918
919 /* Handle any PHY specific procedures following the reset. */
920 switch (bsc->mii_oui) {
921 case MII_OUI_BROADCOM:
922 break;
923 case MII_OUI_xxBROADCOM:
924 switch (bsc->mii_model) {
925 case MII_MODEL_xxBROADCOM_BCM5400:
926 bcm5401_load_dspcode(sc);
927 break;
928 case MII_MODEL_xxBROADCOM_BCM5401:
929 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
930 bcm5401_load_dspcode(sc);
931 break;
932 case MII_MODEL_xxBROADCOM_BCM5411:
933 bcm5411_load_dspcode(sc);
934 break;
935 case MII_MODEL_xxBROADCOM_BCM54K2:
936 bcm54k2_load_dspcode(sc);
937 break;
938 }
939 break;
940 case MII_OUI_xxBROADCOM_ALT1:
941 case MII_OUI_xxBROADCOM_ALT2:
942 break;
943 }
944
945 ifp = sc->mii_pdata->mii_ifp;
946
947 /* Find the driver associated with this PHY. */
948 if (strcmp(ifp->if_dname, "bge") == 0) {
949 bge_sc = ifp->if_softc;
950 } else if (strcmp(ifp->if_dname, "bce") == 0) {
951 bce_sc = ifp->if_softc;
952 }
953
954 if (bge_sc) {
955 /* Fix up various bugs */
956 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
957 brgphy_fixup_5704_a0_bug(sc);
958 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
959 brgphy_fixup_adc_bug(sc);
960 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
961 brgphy_fixup_adjust_trim(sc);
962 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
963 brgphy_fixup_ber_bug(sc);
964 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
965 brgphy_fixup_crc_bug(sc);
966 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
967 brgphy_fixup_jitter_bug(sc);
968
969 brgphy_jumbo_settings(sc, ifp->if_mtu);
970
971 if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED)
972 brgphy_ethernet_wirespeed(sc);
973
974 /* Enable Link LED on Dell boxes */
975 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
976 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
977 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
978 ~BRGPHY_PHY_EXTCTL_3_LED);
979 }
980
981 /* Adjust output voltage (From Linux driver) */
982 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
983 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
984 } else if (bce_sc) {
985 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
986 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
987
988 /* Store autoneg capabilities/results in digital block (Page 0) */
989 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
990 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
991 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
992 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
993
994 /* Enable fiber mode and autodetection */
995 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
996 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
997 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
998 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
999
1000 /* Enable parallel detection */
1001 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1002 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1003 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1004
1005 /* Advertise 2.5G support through next page during autoneg */
1006 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1007 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1008 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1009 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1010
1011 /* Increase TX signal amplitude */
1012 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1013 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1014 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1015 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1016 BRGPHY_5708S_TX_MISC_PG5);
1017 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1018 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1019 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1020 BRGPHY_5708S_DIG_PG0);
1021 }
1022
1023 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1024 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1025 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1026 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1027 BRGPHY_5708S_TX_MISC_PG5);
1028 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1029 bce_sc->bce_port_hw_cfg &
1030 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1032 BRGPHY_5708S_DIG_PG0);
1033 }
1034 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1035 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1036
1037 /* Select the SerDes Digital block of the AN MMD. */
1038 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1039 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1040 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1041 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1042 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1043
1044 /* Select the Over 1G block of the AN MMD. */
1045 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1046
1047 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1048 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1049 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1050 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1051 else
1052 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1053 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1054
1055 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1056 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1057
1058 /* Enable MRBE speed autoneg. */
1059 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1060 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1061 BRGPHY_MRBE_MSG_PG5_NP_T2;
1062 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1063
1064 /* Select the Clause 73 User B0 block of the AN MMD. */
1065 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1066
1067 /* Enable MRBE speed autoneg. */
1068 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1069 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1070 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1071 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1072
1073 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1074 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1075 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1076 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1077 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1078 brgphy_fixup_disable_early_dac(sc);
1079
1080 brgphy_jumbo_settings(sc, ifp->if_mtu);
1081 brgphy_ethernet_wirespeed(sc);
1082 } else {
1083 brgphy_fixup_ber_bug(sc);
1084 brgphy_jumbo_settings(sc, ifp->if_mtu);
1085 brgphy_ethernet_wirespeed(sc);
1086 }
1087 }
1088 }
Cache object: 42b18fb2c1780cbcb43fb6c126d6405e
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