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sys/dev/mii/brgphy.c
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1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mii/brgphy.c 245866 2013-01-24 02:20:25Z yongari $"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75 #define BRGPHY_5706S 0x0001 76 #define BRGPHY_5708S 0x0002 77 #define BRGPHY_NOANWAIT 0x0004 78 #define BRGPHY_5709S 0x0008 79 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 80 }; 81 82 static device_method_t brgphy_methods[] = { 83 /* device interface */ 84 DEVMETHOD(device_probe, brgphy_probe), 85 DEVMETHOD(device_attach, brgphy_attach), 86 DEVMETHOD(device_detach, mii_phy_detach), 87 DEVMETHOD(device_shutdown, bus_generic_shutdown), 88 DEVMETHOD_END 89 }; 90 91 static devclass_t brgphy_devclass; 92 93 static driver_t brgphy_driver = { 94 "brgphy", 95 brgphy_methods, 96 sizeof(struct brgphy_softc) 97 }; 98 99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 100 101 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102 static void brgphy_setmedia(struct mii_softc *, int); 103 static void brgphy_status(struct mii_softc *); 104 static void brgphy_mii_phy_auto(struct mii_softc *, int); 105 static void brgphy_reset(struct mii_softc *); 106 static void brgphy_enable_loopback(struct mii_softc *); 107 static void bcm5401_load_dspcode(struct mii_softc *); 108 static void bcm5411_load_dspcode(struct mii_softc *); 109 static void bcm54k2_load_dspcode(struct mii_softc *); 110 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 111 static void brgphy_fixup_adc_bug(struct mii_softc *); 112 static void brgphy_fixup_adjust_trim(struct mii_softc *); 113 static void brgphy_fixup_ber_bug(struct mii_softc *); 114 static void brgphy_fixup_crc_bug(struct mii_softc *); 115 static void brgphy_fixup_jitter_bug(struct mii_softc *); 116 static void brgphy_ethernet_wirespeed(struct mii_softc *); 117 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119 static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(xxBROADCOM, BCM5400), 121 MII_PHY_DESC(xxBROADCOM, BCM5401), 122 MII_PHY_DESC(xxBROADCOM, BCM5411), 123 MII_PHY_DESC(xxBROADCOM, BCM54K2), 124 MII_PHY_DESC(xxBROADCOM, BCM5701), 125 MII_PHY_DESC(xxBROADCOM, BCM5703), 126 MII_PHY_DESC(xxBROADCOM, BCM5704), 127 MII_PHY_DESC(xxBROADCOM, BCM5705), 128 MII_PHY_DESC(xxBROADCOM, BCM5706), 129 MII_PHY_DESC(xxBROADCOM, BCM5714), 130 MII_PHY_DESC(xxBROADCOM, BCM5750), 131 MII_PHY_DESC(xxBROADCOM, BCM5752), 132 MII_PHY_DESC(xxBROADCOM, BCM5754), 133 MII_PHY_DESC(xxBROADCOM, BCM5780), 134 MII_PHY_DESC(xxBROADCOM, BCM5708C), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), 144 MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C), 145 MII_PHY_DESC(xxBROADCOM_ALT2, BCM5719C), 146 MII_PHY_DESC(xxBROADCOM_ALT2, BCM5720C), 147 MII_PHY_DESC(xxBROADCOM_ALT2, BCM57765), 148 MII_PHY_DESC(xxBROADCOM_ALT2, BCM57780), 149 MII_PHY_DESC(BROADCOM2, BCM5906), 150 MII_PHY_END 151 }; 152 153 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 154 #define HS21_BCM_CHIPID 0x57081021 155 156 static int 157 detect_hs21(struct bce_softc *bce_sc) 158 { 159 char *sysenv; 160 int found; 161 162 found = 0; 163 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 164 sysenv = getenv("smbios.system.product"); 165 if (sysenv != NULL) { 166 if (strncmp(sysenv, HS21_PRODUCT_ID, 167 strlen(HS21_PRODUCT_ID)) == 0) 168 found = 1; 169 freeenv(sysenv); 170 } 171 } 172 return (found); 173 } 174 175 /* Search for our PHY in the list of known PHYs */ 176 static int 177 brgphy_probe(device_t dev) 178 { 179 180 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 181 } 182 183 /* Attach the PHY to the MII bus */ 184 static int 185 brgphy_attach(device_t dev) 186 { 187 struct brgphy_softc *bsc; 188 struct bge_softc *bge_sc = NULL; 189 struct bce_softc *bce_sc = NULL; 190 struct mii_softc *sc; 191 struct mii_attach_args *ma; 192 struct mii_data *mii; 193 struct ifnet *ifp; 194 195 bsc = device_get_softc(dev); 196 sc = &bsc->mii_sc; 197 ma = device_get_ivars(dev); 198 sc->mii_dev = device_get_parent(dev); 199 mii = ma->mii_data; 200 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 201 202 /* Initialize mii_softc structure */ 203 sc->mii_flags = miibus_get_flags(dev); 204 sc->mii_inst = mii->mii_instance++; 205 sc->mii_phy = ma->mii_phyno; 206 sc->mii_service = brgphy_service; 207 sc->mii_pdata = mii; 208 209 /* 210 * At least some variants wedge when isolating, at least some also 211 * don't support loopback. 212 */ 213 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE; 214 215 /* Initialize brgphy_softc structure */ 216 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 217 bsc->mii_model = MII_MODEL(ma->mii_id2); 218 bsc->mii_rev = MII_REV(ma->mii_id2); 219 bsc->serdes_flags = 0; 220 ifp = sc->mii_pdata->mii_ifp; 221 222 if (bootverbose) 223 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 224 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 225 226 /* Find the MAC driver associated with this PHY. */ 227 if (strcmp(ifp->if_dname, "bge") == 0) 228 bge_sc = ifp->if_softc; 229 else if (strcmp(ifp->if_dname, "bce") == 0) 230 bce_sc = ifp->if_softc; 231 232 /* Handle any special cases based on the PHY ID */ 233 switch (bsc->mii_oui) { 234 case MII_OUI_xxBROADCOM: 235 switch (bsc->mii_model) { 236 case MII_MODEL_xxBROADCOM_BCM5706: 237 case MII_MODEL_xxBROADCOM_BCM5714: 238 /* 239 * The 5464 PHY used in the 5706 supports both copper 240 * and fiber interfaces over GMII. Need to check the 241 * shadow registers to see which mode is actually 242 * in effect, and therefore whether we have 5706C or 243 * 5706S. 244 */ 245 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 246 BRGPHY_SHADOW_1C_MODE_CTRL); 247 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 248 BRGPHY_SHADOW_1C_ENA_1000X) { 249 bsc->serdes_flags |= BRGPHY_5706S; 250 sc->mii_flags |= MIIF_HAVEFIBER; 251 } 252 break; 253 } 254 break; 255 case MII_OUI_xxBROADCOM_ALT1: 256 switch (bsc->mii_model) { 257 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 258 bsc->serdes_flags |= BRGPHY_5708S; 259 sc->mii_flags |= MIIF_HAVEFIBER; 260 break; 261 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 262 /* 263 * XXX 264 * 5720S and 5709S shares the same PHY id. 265 * Assume 5720S PHY if parent device is bge(4). 266 */ 267 if (bge_sc != NULL) 268 bsc->serdes_flags |= BRGPHY_5708S; 269 else 270 bsc->serdes_flags |= BRGPHY_5709S; 271 sc->mii_flags |= MIIF_HAVEFIBER; 272 break; 273 } 274 break; 275 } 276 277 brgphy_reset(sc); 278 279 /* Read the PHY's capabilities. */ 280 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 281 if (sc->mii_capabilities & BMSR_EXTSTAT) 282 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 283 device_printf(dev, " "); 284 285 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 286 287 /* Add the supported media types */ 288 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 289 mii_phy_add_media(sc); 290 printf("\n"); 291 } else { 292 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 293 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 294 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 295 printf("1000baseSX-FDX, "); 296 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 297 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 298 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 299 printf("2500baseSX-FDX, "); 300 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 301 (detect_hs21(bce_sc) != 0)) { 302 /* 303 * There appears to be certain silicon revision 304 * in IBM HS21 blades that is having issues with 305 * this driver wating for the auto-negotiation to 306 * complete. This happens with a specific chip id 307 * only and when the 1000baseSX-FDX is the only 308 * mode. Workaround this issue since it's unlikely 309 * to be ever addressed. 310 */ 311 printf("auto-neg workaround, "); 312 bsc->serdes_flags |= BRGPHY_NOANWAIT; 313 } 314 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 315 printf("auto\n"); 316 } 317 318 #undef ADD 319 MIIBUS_MEDIAINIT(sc->mii_dev); 320 return (0); 321 } 322 323 static int 324 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 325 { 326 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 327 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 328 int val; 329 330 switch (cmd) { 331 case MII_POLLSTAT: 332 break; 333 case MII_MEDIACHG: 334 /* If the interface is not up, don't do anything. */ 335 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 336 break; 337 338 /* Todo: Why is this here? Is it really needed? */ 339 brgphy_reset(sc); /* XXX hardware bug work-around */ 340 341 switch (IFM_SUBTYPE(ife->ifm_media)) { 342 case IFM_AUTO: 343 brgphy_mii_phy_auto(sc, ife->ifm_media); 344 break; 345 case IFM_2500_SX: 346 case IFM_1000_SX: 347 case IFM_1000_T: 348 case IFM_100_TX: 349 case IFM_10_T: 350 brgphy_setmedia(sc, ife->ifm_media); 351 break; 352 default: 353 return (EINVAL); 354 } 355 break; 356 case MII_TICK: 357 /* Bail if the interface isn't up. */ 358 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 359 return (0); 360 361 362 /* Bail if autoneg isn't in process. */ 363 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 364 sc->mii_ticks = 0; 365 break; 366 } 367 368 /* 369 * Check to see if we have link. If we do, we don't 370 * need to restart the autonegotiation process. 371 */ 372 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 373 if (val & BMSR_LINK) { 374 sc->mii_ticks = 0; /* Reset autoneg timer. */ 375 break; 376 } 377 378 /* Announce link loss right after it happens. */ 379 if (sc->mii_ticks++ == 0) 380 break; 381 382 /* Only retry autonegotiation every mii_anegticks seconds. */ 383 if (sc->mii_ticks <= sc->mii_anegticks) 384 break; 385 386 387 /* Retry autonegotiation */ 388 sc->mii_ticks = 0; 389 brgphy_mii_phy_auto(sc, ife->ifm_media); 390 break; 391 } 392 393 /* Update the media status. */ 394 brgphy_status(sc); 395 396 /* 397 * Callback if something changed. Note that we need to poke 398 * the DSP on the Broadcom PHYs if the media changes. 399 */ 400 if (sc->mii_media_active != mii->mii_media_active || 401 sc->mii_media_status != mii->mii_media_status || 402 cmd == MII_MEDIACHG) { 403 switch (bsc->mii_oui) { 404 case MII_OUI_xxBROADCOM: 405 switch (bsc->mii_model) { 406 case MII_MODEL_xxBROADCOM_BCM5400: 407 bcm5401_load_dspcode(sc); 408 break; 409 case MII_MODEL_xxBROADCOM_BCM5401: 410 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 411 bcm5401_load_dspcode(sc); 412 break; 413 case MII_MODEL_xxBROADCOM_BCM5411: 414 bcm5411_load_dspcode(sc); 415 break; 416 case MII_MODEL_xxBROADCOM_BCM54K2: 417 bcm54k2_load_dspcode(sc); 418 break; 419 } 420 break; 421 } 422 } 423 mii_phy_update(sc, cmd); 424 return (0); 425 } 426 427 /****************************************************************************/ 428 /* Sets the PHY link speed. */ 429 /* */ 430 /* Returns: */ 431 /* None */ 432 /****************************************************************************/ 433 static void 434 brgphy_setmedia(struct mii_softc *sc, int media) 435 { 436 int bmcr = 0, gig; 437 438 switch (IFM_SUBTYPE(media)) { 439 case IFM_2500_SX: 440 break; 441 case IFM_1000_SX: 442 case IFM_1000_T: 443 bmcr = BRGPHY_S1000; 444 break; 445 case IFM_100_TX: 446 bmcr = BRGPHY_S100; 447 break; 448 case IFM_10_T: 449 default: 450 bmcr = BRGPHY_S10; 451 break; 452 } 453 454 if ((media & IFM_FDX) != 0) { 455 bmcr |= BRGPHY_BMCR_FDX; 456 gig = BRGPHY_1000CTL_AFD; 457 } else { 458 gig = BRGPHY_1000CTL_AHD; 459 } 460 461 /* Force loopback to disconnect PHY from Ethernet medium. */ 462 brgphy_enable_loopback(sc); 463 464 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 465 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 466 467 if (IFM_SUBTYPE(media) != IFM_1000_T && 468 IFM_SUBTYPE(media) != IFM_1000_SX) { 469 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 470 return; 471 } 472 473 if (IFM_SUBTYPE(media) == IFM_1000_T) { 474 gig |= BRGPHY_1000CTL_MSE; 475 if ((media & IFM_ETH_MASTER) != 0 || 476 (sc->mii_pdata->mii_ifp->if_flags & IFF_LINK0) != 0) 477 gig |= BRGPHY_1000CTL_MSC; 478 } 479 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 480 PHY_WRITE(sc, BRGPHY_MII_BMCR, 481 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 482 } 483 484 /****************************************************************************/ 485 /* Set the media status based on the PHY settings. */ 486 /* */ 487 /* Returns: */ 488 /* None */ 489 /****************************************************************************/ 490 static void 491 brgphy_status(struct mii_softc *sc) 492 { 493 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 494 struct mii_data *mii = sc->mii_pdata; 495 int aux, bmcr, bmsr, val, xstat; 496 u_int flowstat; 497 498 mii->mii_media_status = IFM_AVALID; 499 mii->mii_media_active = IFM_ETHER; 500 501 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 502 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 503 504 if (bmcr & BRGPHY_BMCR_LOOP) { 505 mii->mii_media_active |= IFM_LOOP; 506 } 507 508 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 509 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 510 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 511 /* Erg, still trying, I guess... */ 512 mii->mii_media_active |= IFM_NONE; 513 return; 514 } 515 516 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 517 /* 518 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 519 * wedges at least the PHY of BCM5704 (but not others). 520 */ 521 flowstat = mii_phy_flowstatus(sc); 522 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 523 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 524 525 /* If copper link is up, get the negotiated speed/duplex. */ 526 if (aux & BRGPHY_AUXSTS_LINK) { 527 mii->mii_media_status |= IFM_ACTIVE; 528 switch (aux & BRGPHY_AUXSTS_AN_RES) { 529 case BRGPHY_RES_1000FD: 530 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 531 case BRGPHY_RES_1000HD: 532 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 533 case BRGPHY_RES_100FD: 534 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 535 case BRGPHY_RES_100T4: 536 mii->mii_media_active |= IFM_100_T4; break; 537 case BRGPHY_RES_100HD: 538 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 539 case BRGPHY_RES_10FD: 540 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 541 case BRGPHY_RES_10HD: 542 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 543 default: 544 mii->mii_media_active |= IFM_NONE; break; 545 } 546 547 if ((mii->mii_media_active & IFM_FDX) != 0) 548 mii->mii_media_active |= flowstat; 549 550 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 551 (xstat & BRGPHY_1000STS_MSR) != 0) 552 mii->mii_media_active |= IFM_ETH_MASTER; 553 } 554 } else { 555 /* Todo: Add support for flow control. */ 556 /* If serdes link is up, get the negotiated speed/duplex. */ 557 if (bmsr & BRGPHY_BMSR_LINK) { 558 mii->mii_media_status |= IFM_ACTIVE; 559 } 560 561 /* Check the link speed/duplex based on the PHY type. */ 562 if (bsc->serdes_flags & BRGPHY_5706S) { 563 mii->mii_media_active |= IFM_1000_SX; 564 565 /* If autoneg enabled, read negotiated duplex settings */ 566 if (bmcr & BRGPHY_BMCR_AUTOEN) { 567 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 568 if (val & BRGPHY_SERDES_ANAR_FDX) 569 mii->mii_media_active |= IFM_FDX; 570 else 571 mii->mii_media_active |= IFM_HDX; 572 } 573 } else if (bsc->serdes_flags & BRGPHY_5708S) { 574 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 575 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 576 577 /* Check for MRBE auto-negotiated speed results. */ 578 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 579 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 580 mii->mii_media_active |= IFM_10_FL; break; 581 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 582 mii->mii_media_active |= IFM_100_FX; break; 583 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 584 mii->mii_media_active |= IFM_1000_SX; break; 585 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 586 mii->mii_media_active |= IFM_2500_SX; break; 587 } 588 589 /* Check for MRBE auto-negotiated duplex results. */ 590 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 591 mii->mii_media_active |= IFM_FDX; 592 else 593 mii->mii_media_active |= IFM_HDX; 594 } else if (bsc->serdes_flags & BRGPHY_5709S) { 595 /* Select GP Status Block of the AN MMD, get autoneg results. */ 596 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 597 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 598 599 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 600 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 601 602 /* Check for MRBE auto-negotiated speed results. */ 603 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 604 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 605 mii->mii_media_active |= IFM_10_FL; break; 606 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 607 mii->mii_media_active |= IFM_100_FX; break; 608 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 609 mii->mii_media_active |= IFM_1000_SX; break; 610 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 611 mii->mii_media_active |= IFM_2500_SX; break; 612 } 613 614 /* Check for MRBE auto-negotiated duplex results. */ 615 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 616 mii->mii_media_active |= IFM_FDX; 617 else 618 mii->mii_media_active |= IFM_HDX; 619 } 620 } 621 } 622 623 static void 624 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 625 { 626 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 627 int anar, ktcr = 0; 628 629 brgphy_reset(sc); 630 631 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 632 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 633 if ((media & IFM_FLOW) != 0 || 634 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 635 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 636 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 637 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 638 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 639 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 640 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 641 PHY_READ(sc, BRGPHY_MII_1000CTL); 642 } else { 643 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 644 if ((media & IFM_FLOW) != 0 || 645 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 646 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 647 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 648 } 649 650 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 651 BRGPHY_BMCR_STARTNEG); 652 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 653 } 654 655 /* Enable loopback to force the link down. */ 656 static void 657 brgphy_enable_loopback(struct mii_softc *sc) 658 { 659 int i; 660 661 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 662 for (i = 0; i < 15000; i++) { 663 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 664 break; 665 DELAY(10); 666 } 667 } 668 669 /* Turn off tap power management on 5401. */ 670 static void 671 bcm5401_load_dspcode(struct mii_softc *sc) 672 { 673 static const struct { 674 int reg; 675 uint16_t val; 676 } dspcode[] = { 677 { BRGPHY_MII_AUXCTL, 0x0c20 }, 678 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 679 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 680 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 681 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 682 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 683 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 684 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 685 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 686 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 687 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 688 { 0, 0 }, 689 }; 690 int i; 691 692 for (i = 0; dspcode[i].reg != 0; i++) 693 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 694 DELAY(40); 695 } 696 697 static void 698 bcm5411_load_dspcode(struct mii_softc *sc) 699 { 700 static const struct { 701 int reg; 702 uint16_t val; 703 } dspcode[] = { 704 { 0x1c, 0x8c23 }, 705 { 0x1c, 0x8ca3 }, 706 { 0x1c, 0x8c23 }, 707 { 0, 0 }, 708 }; 709 int i; 710 711 for (i = 0; dspcode[i].reg != 0; i++) 712 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 713 } 714 715 void 716 bcm54k2_load_dspcode(struct mii_softc *sc) 717 { 718 static const struct { 719 int reg; 720 uint16_t val; 721 } dspcode[] = { 722 { 4, 0x01e1 }, 723 { 9, 0x0300 }, 724 { 0, 0 }, 725 }; 726 int i; 727 728 for (i = 0; dspcode[i].reg != 0; i++) 729 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 730 731 } 732 733 static void 734 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 735 { 736 static const struct { 737 int reg; 738 uint16_t val; 739 } dspcode[] = { 740 { 0x1c, 0x8d68 }, 741 { 0x1c, 0x8d68 }, 742 { 0, 0 }, 743 }; 744 int i; 745 746 for (i = 0; dspcode[i].reg != 0; i++) 747 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 748 } 749 750 static void 751 brgphy_fixup_adc_bug(struct mii_softc *sc) 752 { 753 static const struct { 754 int reg; 755 uint16_t val; 756 } dspcode[] = { 757 { BRGPHY_MII_AUXCTL, 0x0c00 }, 758 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 759 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 760 { 0, 0 }, 761 }; 762 int i; 763 764 for (i = 0; dspcode[i].reg != 0; i++) 765 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 766 } 767 768 static void 769 brgphy_fixup_adjust_trim(struct mii_softc *sc) 770 { 771 static const struct { 772 int reg; 773 uint16_t val; 774 } dspcode[] = { 775 { BRGPHY_MII_AUXCTL, 0x0c00 }, 776 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 777 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 778 { BRGPHY_MII_TEST1, 0x0014 }, 779 { BRGPHY_MII_AUXCTL, 0x0400 }, 780 { 0, 0 }, 781 }; 782 int i; 783 784 for (i = 0; dspcode[i].reg != 0; i++) 785 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 786 } 787 788 static void 789 brgphy_fixup_ber_bug(struct mii_softc *sc) 790 { 791 static const struct { 792 int reg; 793 uint16_t val; 794 } dspcode[] = { 795 { BRGPHY_MII_AUXCTL, 0x0c00 }, 796 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 797 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 798 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 799 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 800 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 801 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 802 { BRGPHY_MII_AUXCTL, 0x0400 }, 803 { 0, 0 }, 804 }; 805 int i; 806 807 for (i = 0; dspcode[i].reg != 0; i++) 808 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 809 } 810 811 static void 812 brgphy_fixup_crc_bug(struct mii_softc *sc) 813 { 814 static const struct { 815 int reg; 816 uint16_t val; 817 } dspcode[] = { 818 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 819 { 0x1c, 0x8c68 }, 820 { 0x1c, 0x8d68 }, 821 { 0x1c, 0x8c68 }, 822 { 0, 0 }, 823 }; 824 int i; 825 826 for (i = 0; dspcode[i].reg != 0; i++) 827 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 828 } 829 830 static void 831 brgphy_fixup_jitter_bug(struct mii_softc *sc) 832 { 833 static const struct { 834 int reg; 835 uint16_t val; 836 } dspcode[] = { 837 { BRGPHY_MII_AUXCTL, 0x0c00 }, 838 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 839 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 840 { BRGPHY_MII_AUXCTL, 0x0400 }, 841 { 0, 0 }, 842 }; 843 int i; 844 845 for (i = 0; dspcode[i].reg != 0; i++) 846 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 847 } 848 849 static void 850 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 851 { 852 uint32_t val; 853 854 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 855 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 856 val &= ~(1 << 8); 857 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 858 859 } 860 861 static void 862 brgphy_ethernet_wirespeed(struct mii_softc *sc) 863 { 864 uint32_t val; 865 866 /* Enable Ethernet@WireSpeed. */ 867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 868 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 870 } 871 872 static void 873 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 874 { 875 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 876 uint32_t val; 877 878 /* Set or clear jumbo frame settings in the PHY. */ 879 if (mtu > ETHER_MAX_LEN) { 880 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 881 /* BCM5401 PHY cannot read-modify-write. */ 882 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 883 } else { 884 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 885 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 887 val | BRGPHY_AUXCTL_LONG_PKT); 888 } 889 890 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 891 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 892 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 893 } else { 894 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 895 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 896 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 897 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 898 899 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 900 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 901 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 902 } 903 } 904 905 static void 906 brgphy_reset(struct mii_softc *sc) 907 { 908 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 909 struct bge_softc *bge_sc = NULL; 910 struct bce_softc *bce_sc = NULL; 911 struct ifnet *ifp; 912 int i, val; 913 914 /* 915 * Perform a reset. Note that at least some Broadcom PHYs default to 916 * being powered down as well as isolated after a reset but don't work 917 * if one or both of these bits are cleared. However, they just work 918 * fine if both bits remain set, so we don't use mii_phy_reset() here. 919 */ 920 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 921 922 /* Wait 100ms for it to complete. */ 923 for (i = 0; i < 100; i++) { 924 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 925 break; 926 DELAY(1000); 927 } 928 929 /* Handle any PHY specific procedures following the reset. */ 930 switch (bsc->mii_oui) { 931 case MII_OUI_xxBROADCOM: 932 switch (bsc->mii_model) { 933 case MII_MODEL_xxBROADCOM_BCM5400: 934 bcm5401_load_dspcode(sc); 935 break; 936 case MII_MODEL_xxBROADCOM_BCM5401: 937 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 938 bcm5401_load_dspcode(sc); 939 break; 940 case MII_MODEL_xxBROADCOM_BCM5411: 941 bcm5411_load_dspcode(sc); 942 break; 943 case MII_MODEL_xxBROADCOM_BCM54K2: 944 bcm54k2_load_dspcode(sc); 945 break; 946 } 947 break; 948 case MII_OUI_xxBROADCOM_ALT2: 949 switch (bsc->mii_model) { 950 case MII_MODEL_xxBROADCOM_ALT2_BCM5717C: 951 case MII_MODEL_xxBROADCOM_ALT2_BCM5719C: 952 case MII_MODEL_xxBROADCOM_ALT2_BCM5720C: 953 case MII_MODEL_xxBROADCOM_ALT2_BCM57765: 954 return; 955 } 956 break; 957 } 958 959 ifp = sc->mii_pdata->mii_ifp; 960 961 /* Find the driver associated with this PHY. */ 962 if (strcmp(ifp->if_dname, "bge") == 0) { 963 bge_sc = ifp->if_softc; 964 } else if (strcmp(ifp->if_dname, "bce") == 0) { 965 bce_sc = ifp->if_softc; 966 } 967 968 if (bge_sc) { 969 /* Fix up various bugs */ 970 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 971 brgphy_fixup_5704_a0_bug(sc); 972 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 973 brgphy_fixup_adc_bug(sc); 974 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 975 brgphy_fixup_adjust_trim(sc); 976 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 977 brgphy_fixup_ber_bug(sc); 978 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 979 brgphy_fixup_crc_bug(sc); 980 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 981 brgphy_fixup_jitter_bug(sc); 982 983 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 984 brgphy_jumbo_settings(sc, ifp->if_mtu); 985 986 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 987 brgphy_ethernet_wirespeed(sc); 988 989 /* Enable Link LED on Dell boxes */ 990 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 991 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 992 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 993 ~BRGPHY_PHY_EXTCTL_3_LED); 994 } 995 996 /* Adjust output voltage (From Linux driver) */ 997 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 998 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 999 } else if (bce_sc) { 1000 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1001 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1002 1003 /* Store autoneg capabilities/results in digital block (Page 0) */ 1004 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1005 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1006 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1007 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1008 1009 /* Enable fiber mode and autodetection */ 1010 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1011 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1012 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1013 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1014 1015 /* Enable parallel detection */ 1016 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1017 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1018 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1019 1020 /* Advertise 2.5G support through next page during autoneg */ 1021 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1022 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1023 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1024 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1025 1026 /* Increase TX signal amplitude */ 1027 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1028 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1029 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1030 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1031 BRGPHY_5708S_TX_MISC_PG5); 1032 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1033 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1034 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1035 BRGPHY_5708S_DIG_PG0); 1036 } 1037 1038 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1039 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1040 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1041 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1042 BRGPHY_5708S_TX_MISC_PG5); 1043 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1044 bce_sc->bce_port_hw_cfg & 1045 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1046 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1047 BRGPHY_5708S_DIG_PG0); 1048 } 1049 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1050 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1051 1052 /* Select the SerDes Digital block of the AN MMD. */ 1053 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1054 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1055 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1056 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1057 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1058 1059 /* Select the Over 1G block of the AN MMD. */ 1060 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1061 1062 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1063 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1064 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1065 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1066 else 1067 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1068 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1069 1070 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1071 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1072 1073 /* Enable MRBE speed autoneg. */ 1074 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1075 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1076 BRGPHY_MRBE_MSG_PG5_NP_T2; 1077 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1078 1079 /* Select the Clause 73 User B0 block of the AN MMD. */ 1080 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1081 1082 /* Enable MRBE speed autoneg. */ 1083 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1084 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1085 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1086 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1087 1088 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1089 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1090 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1091 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1092 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1093 brgphy_fixup_disable_early_dac(sc); 1094 1095 brgphy_jumbo_settings(sc, ifp->if_mtu); 1096 brgphy_ethernet_wirespeed(sc); 1097 } else { 1098 brgphy_fixup_ber_bug(sc); 1099 brgphy_jumbo_settings(sc, ifp->if_mtu); 1100 brgphy_ethernet_wirespeed(sc); 1101 } 1102 } 1103 }
Cache object: 53dbe38c38b199e9f189460ab7ffb351
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