The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/brgphyreg.h

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    1 /*
    2  * Copyright (c) 2000
    3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.0/sys/dev/mii/brgphyreg.h 84035 2001-09-27 17:32:49Z wpaul $
   33  */
   34 
   35 #ifndef _DEV_MII_BRGPHYREG_H_
   36 #define _DEV_MII_BRGPHYREG_H_
   37 
   38 /*
   39  * Broadcom BCM5400 registers
   40  */
   41 
   42 #define BRGPHY_MII_BMCR         0x00
   43 #define BRGPHY_BMCR_RESET       0x8000
   44 #define BRGPHY_BMCR_LOOP        0x4000
   45 #define BRGPHY_BMCR_SPD0        0x2000  /* speed select, lower bit */
   46 #define BRGPHY_BMCR_AUTOEN      0x1000  /* Autoneg enabled */
   47 #define BRGPHY_BMCR_PDOWN       0x0800  /* Power down */
   48 #define BRGPHY_BMCR_ISO         0x0400  /* Isolate */
   49 #define BRGPHY_BMCR_STARTNEG    0x0200  /* Restart autoneg */
   50 #define BRGPHY_BMCR_FDX         0x0100  /* Duplex mode */
   51 #define BRGPHY_BMCR_CTEST       0x0080  /* Collision test enable */
   52 #define BRGPHY_BMCR_SPD1        0x0040  /* Speed select, upper bit */
   53 
   54 #define BRGPHY_S1000            BRGPHY_BMCR_SPD1        /* 1000mbps */
   55 #define BRGPHY_S100             BRGPHY_BMCR_SPD0        /* 100mpbs */
   56 #define BRGPHY_S10              0                       /* 10mbps */
   57 
   58 #define BRGPHY_MII_BMSR         0x01
   59 #define BRGPHY_BMSR_EXTSTS      0x0100  /* Extended status present */
   60 #define BRGPHY_BMSR_PRESUB      0x0040  /* Preamble surpression */
   61 #define BRGPHY_BMSR_ACOMP       0x0020  /* Autoneg complete */
   62 #define BRGPHY_BMSR_RFAULT      0x0010  /* Remote fault condition occured */
   63 #define BRGPHY_BMSR_ANEG        0x0008  /* Autoneg capable */
   64 #define BRGPHY_BMSR_LINK        0x0004  /* Link status */
   65 #define BRGPHY_BMSR_JABBER      0x0002  /* Jabber detected */
   66 #define BRGPHY_BMSR_EXT         0x0001  /* Extended capability */
   67 
   68 #define BRGPHY_MII_ANAR         0x04
   69 #define BRGPHY_ANAR_NP          0x8000  /* Next page */
   70 #define BRGPHY_ANAR_RF          0x2000  /* Remote fault */
   71 #define BRGPHY_ANAR_ASP         0x0800  /* Asymmetric Pause */
   72 #define BRGPHY_ANAR_PC          0x0400  /* Pause capable */
   73 #define BRGPHY_ANAR_SEL         0x001F  /* selector field, 00001=Ethernet */
   74 
   75 #define BRGPHY_MII_ANLPAR       0x05
   76 #define BRGPHY_ANLPAR_NP        0x8000  /* Next page */
   77 #define BRGPHY_ANLPAR_RF        0x2000  /* Remote fault */
   78 #define BRGPHY_ANLPAR_ASP       0x0800  /* Asymmetric Pause */
   79 #define BRGPHY_ANLPAR_PC        0x0400  /* Pause capable */
   80 #define BRGPHY_ANLPAR_SEL       0x001F  /* selector field, 00001=Ethernet */
   81 
   82 #define BRGPHY_SEL_TYPE         0x0001  /* ethernet */
   83 
   84 #define BRGPHY_MII_ANER         0x06
   85 #define BRGPHY_ANER_PDF         0x0010  /* Parallel detection fault */
   86 #define BRGPHY_ANER_LPNP        0x0008  /* Link partner can next page */
   87 #define BRGPHY_ANER_NP          0x0004  /* Local PHY can next page */
   88 #define BRGPHY_ANER_RX          0x0002  /* Next page received */
   89 #define BRGPHY_ANER_LPAN        0x0001  /* Link partner autoneg capable */
   90 
   91 #define BRGPHY_MII_NEXTP        0x07    /* Next page */
   92 
   93 #define BRGPHY_MII_NEXTP_LP     0x08    /* Next page of link partner */
   94 
   95 #define BRGPHY_MII_1000CTL      0x09    /* 1000baseT control */
   96 #define BRGPHY_1000CTL_TST      0xE000  /* test modes */
   97 #define BRGPHY_1000CTL_MSE      0x1000  /* Master/Slave enable */
   98 #define BRGPHY_1000CTL_MSC      0x0800  /* Master/Slave configuration */
   99 #define BRGPHY_1000CTL_RD       0x0400  /* Repeater/DTE */
  100 #define BRGPHY_1000CTL_AFD      0x0200  /* Advertise full duplex */
  101 #define BRGPHY_1000CTL_AHD      0x0100  /* Advertise half duplex */
  102 
  103 #define BRGPHY_MII_1000STS      0x0A    /* 1000baseT status */
  104 #define BRGPHY_1000STS_MSF      0x8000  /* Master/slave fault */
  105 #define BRGPHY_1000STS_MSR      0x4000  /* Master/slave result */
  106 #define BRGPHY_1000STS_LRS      0x2000  /* Local receiver status */
  107 #define BRGPHY_1000STS_RRS      0x1000  /* Remote receiver status */
  108 #define BRGPHY_1000STS_LPFD     0x0800  /* Link partner can FD */
  109 #define BRGPHY_1000STS_LPHD     0x0400  /* Link partner can HD */
  110 #define BRGPHY_1000STS_IEC      0x00FF  /* Idle error count */
  111 
  112 #define BRGPHY_MII_EXTSTS       0x0F    /* Extended status */
  113 #define BRGPHY_EXTSTS_X_FD_CAP  0x8000  /* 1000base-X FD capable */
  114 #define BRGPHY_EXTSTS_X_HD_CAP  0x4000  /* 1000base-X HD capable */
  115 #define BRGPHY_EXTSTS_T_FD_CAP  0x2000  /* 1000base-T FD capable */
  116 #define BRGPHY_EXTSTS_T_HD_CAP  0x1000  /* 1000base-T HD capable */
  117 
  118 #define BRGPHY_MII_PHY_EXTCTL   0x10    /* PHY extended control */
  119 #define BRGPHY_PHY_EXTCTL_MAC_PHY       0x8000  /* 10BIT/GMI-interface */
  120 #define BRGPHY_PHY_EXTCTL_DIS_CROSS     0x4000  /* Disable MDI crossover */
  121 #define BRGPHY_PHY_EXTCTL_TX_DIS        0x2000  /* Tx output disable d*/
  122 #define BRGPHY_PHY_EXTCTL_INT_DIS       0x1000  /* Interrupts disabled */
  123 #define BRGPHY_PHY_EXTCTL_F_INT         0x0800  /* Force interrupt */
  124 #define BRGPHY_PHY_EXTCTL_BY_45         0x0400  /* Bypass 4B5B-Decoder */
  125 #define BRGPHY_PHY_EXTCTL_BY_SCR        0x0200  /* Bypass scrambler */
  126 #define BRGPHY_PHY_EXTCTL_BY_MLT3       0x0100  /* Bypass MLT3 encoder */
  127 #define BRGPHY_PHY_EXTCTL_BY_RXA        0x0080  /* Bypass RX alignment */
  128 #define BRGPHY_PHY_EXTCTL_RES_SCR       0x0040  /* Reset scrambler */
  129 #define BRGPHY_PHY_EXTCTL_EN_LTR        0x0020  /* Enable LED traffic mode */
  130 #define BRGPHY_PHY_EXTCTL_LED_ON        0x0010  /* Force LEDs on */
  131 #define BRGPHY_PHY_EXTCTL_LED_OFF       0x0008  /* Force LEDs off */
  132 #define BRGPHY_PHY_EXTCTL_EX_IPG        0x0004  /* Extended TX IPG mode */
  133 #define BRGPHY_PHY_EXTCTL_3_LED         0x0002  /* Three link LED mode */
  134 #define BRGPHY_PHY_EXTCTL_HIGH_LA       0x0001  /* GMII Fifo Elasticy (?) */
  135 
  136 #define BRGPHY_MII_PHY_EXTSTS   0x11    /* PHY extended status */
  137 #define BRGPHY_PHY_EXTSTS_CROSS_STAT    0x2000  /* MDI crossover status */
  138 #define BRGPHY_PHY_EXTSTS_INT_STAT      0x1000  /* Interrupt status */
  139 #define BRGPHY_PHY_EXTSTS_RRS           0x0800  /* Remote receiver status */
  140 #define BRGPHY_PHY_EXTSTS_LRS           0x0400  /* Local receiver status */
  141 #define BRGPHY_PHY_EXTSTS_LOCKED        0x0200  /* Locked */
  142 #define BRGPHY_PHY_EXTSTS_LS            0x0100  /* Link status */
  143 #define BRGPHY_PHY_EXTSTS_RF            0x0080  /* Remove fault */
  144 #define BRGPHY_PHY_EXTSTS_CE_ER         0x0040  /* Carrier ext error */
  145 #define BRGPHY_PHY_EXTSTS_BAD_SSD       0x0020  /* Bad SSD */
  146 #define BRGPHY_PHY_EXTSTS_BAD_ESD       0x0010  /* Bad ESS */
  147 #define BRGPHY_PHY_EXTSTS_RX_ER         0x0008  /* RX error */
  148 #define BRGPHY_PHY_EXTSTS_TX_ER         0x0004  /* TX error */
  149 #define BRGPHY_PHY_EXTSTS_LOCK_ER       0x0002  /* Lock error */
  150 #define BRGPHY_PHY_EXTSTS_MLT3_ER       0x0001  /* MLT3 code error */
  151 
  152 #define BRGPHY_MII_RXERRCNT     0x12    /* RX error counter */
  153 
  154 #define BRGPHY_MII_FCERRCNT     0x13    /* false carrier sense counter */
  155 #define BGRPHY_FCERRCNT         0x00FF  /* False carrier counter */
  156 
  157 #define BRGPHY_MII_RXNOCNT      0x14    /* RX not OK counter */
  158 #define BRGPHY_RXNOCNT_LOCAL    0xFF00  /* Local RX not OK counter */
  159 #define BRGPHY_RXNOCNT_REMOTE   0x00FF  /* Local RX not OK counter */
  160 
  161 #define BRGPHY_MII_DSP_RW_PORT  0x15    /* DSP coefficient r/w port */
  162 
  163 #define BRGPHY_MII_DSP_ADDR_REG 0x17    /* DSP coefficient addr register */
  164 
  165 #define BRGPHY_DSP_TAP_NUMBER_MASK              0x00
  166 #define BRGPHY_DSP_AGC_A                        0x00
  167 #define BRGPHY_DSP_AGC_B                        0x01
  168 #define BRGPHY_DSP_MSE_PAIR_STATUS              0x02
  169 #define BRGPHY_DSP_SOFT_DECISION                0x03
  170 #define BRGPHY_DSP_PHASE_REG                    0x04
  171 #define BRGPHY_DSP_SKEW                         0x05
  172 #define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND      0x06
  173 #define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND      0x07
  174 #define BRGPHY_DSP_LAST_ECHO                    0x08
  175 #define BRGPHY_DSP_FREQUENCY                    0x09
  176 #define BRGPHY_DSP_PLL_BANDWIDTH                0x0A
  177 #define BRGPHY_DSP_PLL_PHASE_OFFSET             0x0B
  178 
  179 #define BRGPHYDSP_FILTER_DCOFFSET               0x0C00
  180 #define BRGPHY_DSP_FILTER_FEXT3                 0x0B00
  181 #define BRGPHY_DSP_FILTER_FEXT2                 0x0A00
  182 #define BRGPHY_DSP_FILTER_FEXT1                 0x0900
  183 #define BRGPHY_DSP_FILTER_FEXT0                 0x0800
  184 #define BRGPHY_DSP_FILTER_NEXT3                 0x0700
  185 #define BRGPHY_DSP_FILTER_NEXT2                 0x0600
  186 #define BRGPHY_DSP_FILTER_NEXT1                 0x0500
  187 #define BRGPHY_DSP_FILTER_NEXT0                 0x0400
  188 #define BRGPHY_DSP_FILTER_ECHO                  0x0300
  189 #define BRGPHY_DSP_FILTER_DFE                   0x0200
  190 #define BRGPHY_DSP_FILTER_FFE                   0x0100
  191 
  192 #define BRGPHY_DSP_CONTROL_ALL_FILTERS          0x1000
  193 
  194 #define BRGPHY_DSP_SEL_CH_0                     0x0000
  195 #define BRGPHY_DSP_SEL_CH_1                     0x2000
  196 #define BRGPHY_DSP_SEL_CH_2                     0x4000
  197 #define BRGPHY_DSP_SEL_CH_3                     0x6000
  198 
  199 #define BRGPHY_MII_AUXCTL       0x18    /* AUX control */
  200 #define BRGPHY_AUXCTL_LOW_SQ    0x8000  /* Low squelch */
  201 #define BRGPHY_AUXCTL_LONG_PKT  0x4000  /* RX long packets */
  202 #define BRGPHY_AUXCTL_ER_CTL    0x3000  /* Edgerate control */
  203 #define BRGPHY_AUXCTL_TX_TST    0x0400  /* TX test, always 1 */
  204 #define BRGPHY_AUXCTL_DIS_PRF   0x0080  /* dis part resp filter */
  205 #define BRGPHY_AUXCTL_DIAG_MODE 0x0004  /* Diagnostic mode */
  206 
  207 #define BRGPHY_MII_AUXSTS       0x19    /* AUX status */
  208 #define BRGPHY_AUXSTS_ACOMP     0x8000  /* autoneg complete */
  209 #define BRGPHY_AUXSTS_AN_ACK    0x4000  /* autoneg complete ack */
  210 #define BRGPHY_AUXSTS_AN_ACK_D  0x2000  /* autoneg complete ack detect */
  211 #define BRGPHY_AUXSTS_AN_NPW    0x1000  /* autoneg next page wait */
  212 #define BRGPHY_AUXSTS_AN_RES    0x0700  /* AN HDC */
  213 #define BRGPHY_AUXSTS_PDF       0x0080  /* Parallel detect. fault */
  214 #define BRGPHY_AUXSTS_RF        0x0040  /* remote fault */
  215 #define BRGPHY_AUXSTS_ANP_R     0x0020  /* AN page received */
  216 #define BRGPHY_AUXSTS_LP_ANAB   0x0010  /* LP AN ability */
  217 #define BRGPHY_AUXSTS_LP_NPAB   0x0008  /* LP Next page ability */
  218 #define BRGPHY_AUXSTS_LINK      0x0004  /* Link status */
  219 #define BRGPHY_AUXSTS_PRR       0x0002  /* Pause resolution-RX */
  220 #define BRGPHY_AUXSTS_PRT       0x0001  /* Pause resolution-TX */
  221 
  222 #define BRGPHY_RES_1000FD       0x0700  /* 1000baseT full duplex */
  223 #define BRGPHY_RES_1000HD       0x0600  /* 1000baseT half duplex */
  224 #define BRGPHY_RES_100FD        0x0500  /* 100baseT full duplex */
  225 #define BRGPHY_RES_100T4        0x0400  /* 100baseT4 */
  226 #define BRGPHY_RES_100HD        0x0300  /* 100baseT half duplex */
  227 #define BRGPHY_RES_10HD         0x0200  /* 10baseT full duplex */
  228 #define BRGPHY_RES_10FD         0x0100  /* 10baseT half duplex */
  229 
  230 #define BRGPHY_MII_ISR          0x1A    /* interrupt status */
  231 #define BRGPHY_ISR_PSERR        0x4000  /* Pair swap error */
  232 #define BRGPHY_ISR_MDXI_SC      0x2000  /* MDIX Status Change */
  233 #define BRGPHY_ISR_HCT          0x1000  /* counter above 32K */
  234 #define BRGPHY_ISR_LCT          0x0800  /* all counter below 128 */
  235 #define BRGPHY_ISR_AN_PR        0x0400  /* Autoneg page received */
  236 #define BRGPHY_ISR_NO_HDCL      0x0200  /* No HCD Link */
  237 #define BRGPHY_ISR_NO_HDC       0x0100  /* No HCD */
  238 #define BRGPHY_ISR_USHDC        0x0080  /* Negotiated Unsupported HCD */
  239 #define BRGPHY_ISR_SCR_S_ERR    0x0040  /* Scrambler sync error */
  240 #define BRGPHY_ISR_RRS_CHG      0x0020  /* Remote RX status change */
  241 #define BRGPHY_ISR_LRS_CHG      0x0010  /* Local RX status change */
  242 #define BRGPHY_ISR_DUP_CHG      0x0008  /* Duplex mode change */
  243 #define BRGPHY_ISR_LSP_CHG      0x0004  /* Link speed changed */
  244 #define BRGPHY_ISR_LNK_CHG      0x0002  /* Link status change */
  245 #define BRGPHY_ISR_CRCERR       0x0001  /* CEC error */
  246 
  247 #define BRGPHY_MII_IMR          0x1B    /* interrupt mask */
  248 #define BRGPHY_IMR_PSERR        0x4000  /* Pair swap error */
  249 #define BRGPHY_IMR_MDXI_SC      0x2000  /* MDIX Status Change */
  250 #define BRGPHY_IMR_HCT          0x1000  /* counter above 32K */
  251 #define BRGPHY_IMR_LCT          0x0800  /* all counter below 128 */
  252 #define BRGPHY_IMR_AN_PR        0x0400  /* Autoneg page received */
  253 #define BRGPHY_IMR_NO_HDCL      0x0200  /* No HCD Link */
  254 #define BRGPHY_IMR_NO_HDC       0x0100  /* No HCD */
  255 #define BRGPHY_IMR_USHDC        0x0080  /* Negotiated Unsupported HCD */
  256 #define BRGPHY_IMR_SCR_S_ERR    0x0040  /* Scrambler sync error */
  257 #define BRGPHY_IMR_RRS_CHG      0x0020  /* Remote RX status change */
  258 #define BRGPHY_IMR_LRS_CHG      0x0010  /* Local RX status change */
  259 #define BRGPHY_IMR_DUP_CHG      0x0008  /* Duplex mode change */
  260 #define BRGPHY_IMR_LSP_CHG      0x0004  /* Link speed changed */
  261 #define BRGPHY_IMR_LNK_CHG      0x0002  /* Link status change */
  262 #define BRGPHY_IMR_CRCERR       0x0001  /* CEC error */
  263 
  264 #define BRGPHY_INTRS    \
  265         ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
  266 
  267 #endif /* _DEV_BRGPHY_MIIREG_H_ */

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