FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/ciphy.c
1 /*-
2 * Copyright (c) 2004
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46
47 #include <net/if.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
50
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include "miidevs.h"
54
55 #include <dev/mii/ciphyreg.h>
56
57 #include "miibus_if.h"
58
59 #include <machine/bus.h>
60
61 static int ciphy_probe(device_t);
62 static int ciphy_attach(device_t);
63
64 static device_method_t ciphy_methods[] = {
65 /* device interface */
66 DEVMETHOD(device_probe, ciphy_probe),
67 DEVMETHOD(device_attach, ciphy_attach),
68 DEVMETHOD(device_detach, mii_phy_detach),
69 DEVMETHOD(device_shutdown, bus_generic_shutdown),
70 DEVMETHOD_END
71 };
72
73 static devclass_t ciphy_devclass;
74
75 static driver_t ciphy_driver = {
76 "ciphy",
77 ciphy_methods,
78 sizeof(struct mii_softc)
79 };
80
81 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
82
83 static int ciphy_service(struct mii_softc *, struct mii_data *, int);
84 static void ciphy_status(struct mii_softc *);
85 static void ciphy_reset(struct mii_softc *);
86 static void ciphy_fixup(struct mii_softc *);
87
88 static const struct mii_phydesc ciphys[] = {
89 MII_PHY_DESC(xxCICADA, CS8201),
90 MII_PHY_DESC(xxCICADA, CS8201A),
91 MII_PHY_DESC(xxCICADA, CS8201B),
92 MII_PHY_DESC(xxCICADA, CS8204),
93 MII_PHY_DESC(xxCICADA, VSC8211),
94 MII_PHY_DESC(xxCICADA, VSC8221),
95 MII_PHY_DESC(xxCICADA, CS8244),
96 MII_PHY_DESC(xxVITESSE, VSC8601),
97 MII_PHY_DESC(xxVITESSE, VSC8641),
98 MII_PHY_END
99 };
100
101 static const struct mii_phy_funcs ciphy_funcs = {
102 ciphy_service,
103 ciphy_status,
104 ciphy_reset
105 };
106
107 static int
108 ciphy_probe(device_t dev)
109 {
110
111 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
112 }
113
114 static int
115 ciphy_attach(device_t dev)
116 {
117
118 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
119 &ciphy_funcs, 1);
120 return (0);
121 }
122
123 static int
124 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
125 {
126 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
127 int reg, speed, gig;
128
129 switch (cmd) {
130 case MII_POLLSTAT:
131 break;
132
133 case MII_MEDIACHG:
134 /*
135 * If the interface is not up, don't do anything.
136 */
137 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
138 break;
139
140 ciphy_fixup(sc); /* XXX hardware bug work-around */
141
142 switch (IFM_SUBTYPE(ife->ifm_media)) {
143 case IFM_AUTO:
144 #ifdef foo
145 /*
146 * If we're already in auto mode, just return.
147 */
148 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
149 return (0);
150 #endif
151 (void)mii_phy_auto(sc);
152 break;
153 case IFM_1000_T:
154 speed = CIPHY_S1000;
155 goto setit;
156 case IFM_100_TX:
157 speed = CIPHY_S100;
158 goto setit;
159 case IFM_10_T:
160 speed = CIPHY_S10;
161 setit:
162 if ((ife->ifm_media & IFM_FDX) != 0) {
163 speed |= CIPHY_BMCR_FDX;
164 gig = CIPHY_1000CTL_AFD;
165 } else
166 gig = CIPHY_1000CTL_AHD;
167
168 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
169 gig |= CIPHY_1000CTL_MSE;
170 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
171 gig |= CIPHY_1000CTL_MSC;
172 speed |=
173 CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
174 } else
175 gig = 0;
176 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
177 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
178 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
179 break;
180 case IFM_NONE:
181 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
182 break;
183 default:
184 return (EINVAL);
185 }
186 break;
187
188 case MII_TICK:
189 /*
190 * Is the interface even up?
191 */
192 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
193 return (0);
194
195 /*
196 * Only used for autonegotiation.
197 */
198 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
199 break;
200
201 /*
202 * Check to see if we have link. If we do, we don't
203 * need to restart the autonegotiation process. Read
204 * the BMSR twice in case it's latched.
205 */
206 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
207 if (reg & BMSR_LINK)
208 break;
209
210 /* Announce link loss right after it happens. */
211 if (++sc->mii_ticks == 0)
212 break;
213 /*
214 * Only retry autonegotiation every mii_anegticks seconds.
215 */
216 if (sc->mii_ticks <= sc->mii_anegticks)
217 break;
218
219 sc->mii_ticks = 0;
220 mii_phy_auto(sc);
221 break;
222 }
223
224 /* Update the media status. */
225 PHY_STATUS(sc);
226
227 /*
228 * Callback if something changed. Note that we need to poke
229 * apply fixups for certain PHY revs.
230 */
231 if (sc->mii_media_active != mii->mii_media_active ||
232 sc->mii_media_status != mii->mii_media_status ||
233 cmd == MII_MEDIACHG) {
234 ciphy_fixup(sc);
235 }
236 mii_phy_update(sc, cmd);
237 return (0);
238 }
239
240 static void
241 ciphy_status(struct mii_softc *sc)
242 {
243 struct mii_data *mii = sc->mii_pdata;
244 int bmsr, bmcr;
245
246 mii->mii_media_status = IFM_AVALID;
247 mii->mii_media_active = IFM_ETHER;
248
249 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
250
251 if (bmsr & BMSR_LINK)
252 mii->mii_media_status |= IFM_ACTIVE;
253
254 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
255
256 if (bmcr & CIPHY_BMCR_LOOP)
257 mii->mii_media_active |= IFM_LOOP;
258
259 if (bmcr & CIPHY_BMCR_AUTOEN) {
260 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
261 /* Erg, still trying, I guess... */
262 mii->mii_media_active |= IFM_NONE;
263 return;
264 }
265 }
266
267 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
268 switch (bmsr & CIPHY_AUXCSR_SPEED) {
269 case CIPHY_SPEED10:
270 mii->mii_media_active |= IFM_10_T;
271 break;
272 case CIPHY_SPEED100:
273 mii->mii_media_active |= IFM_100_TX;
274 break;
275 case CIPHY_SPEED1000:
276 mii->mii_media_active |= IFM_1000_T;
277 break;
278 default:
279 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
280 bmsr & CIPHY_AUXCSR_SPEED);
281 break;
282 }
283
284 if (bmsr & CIPHY_AUXCSR_FDX)
285 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
286 else
287 mii->mii_media_active |= IFM_HDX;
288
289 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
290 (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
291 mii->mii_media_active |= IFM_ETH_MASTER;
292 }
293
294 static void
295 ciphy_reset(struct mii_softc *sc)
296 {
297
298 mii_phy_reset(sc);
299 DELAY(1000);
300 }
301
302 #define PHY_SETBIT(x, y, z) \
303 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
304 #define PHY_CLRBIT(x, y, z) \
305 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
306
307 static void
308 ciphy_fixup(struct mii_softc *sc)
309 {
310 uint16_t model;
311 uint16_t status, speed;
312 uint16_t val;
313
314 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
315 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
316 speed = status & CIPHY_AUXCSR_SPEED;
317
318 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
319 "nfe") == 0) {
320 /* need to set for 2.5V RGMII for NVIDIA adapters */
321 val = PHY_READ(sc, CIPHY_MII_ECTL1);
322 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
323 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
324 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
325 /* From Linux. */
326 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
327 val |= CIPHY_AUXCSR_MDPPS;
328 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
329 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
330 val |= CIPHY_10BTCSR_ECHO;
331 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
332 }
333
334 switch (model) {
335 case MII_MODEL_xxCICADA_CS8204:
336 case MII_MODEL_xxCICADA_CS8201:
337
338 /* Turn off "aux mode" (whatever that means) */
339 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
340
341 /*
342 * Work around speed polling bug in VT3119/VT3216
343 * when using MII in full duplex mode.
344 */
345 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
346 (status & CIPHY_AUXCSR_FDX)) {
347 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
348 } else {
349 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
350 }
351
352 /* Enable link/activity LED blink. */
353 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
354
355 break;
356
357 case MII_MODEL_xxCICADA_CS8201A:
358 case MII_MODEL_xxCICADA_CS8201B:
359
360 /*
361 * Work around speed polling bug in VT3119/VT3216
362 * when using MII in full duplex mode.
363 */
364 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
365 (status & CIPHY_AUXCSR_FDX)) {
366 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
367 } else {
368 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
369 }
370
371 break;
372 case MII_MODEL_xxCICADA_VSC8211:
373 case MII_MODEL_xxCICADA_VSC8221:
374 case MII_MODEL_xxCICADA_CS8244:
375 case MII_MODEL_xxVITESSE_VSC8601:
376 case MII_MODEL_xxVITESSE_VSC8641:
377 break;
378 default:
379 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
380 model);
381 break;
382 }
383 }
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