The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/ciphy.c

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    1 /*-
    2  * Copyright (c) 2004
    3  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mii/ciphy.c 230718 2012-01-29 01:35:14Z marius $");
   35 
   36 /*
   37  * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
   38  */
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/kernel.h>
   43 #include <sys/module.h>
   44 #include <sys/socket.h>
   45 #include <sys/bus.h>
   46 
   47 #include <net/if.h>
   48 #include <net/if_arp.h>
   49 #include <net/if_media.h>
   50 
   51 #include <dev/mii/mii.h>
   52 #include <dev/mii/miivar.h>
   53 #include "miidevs.h"
   54 
   55 #include <dev/mii/ciphyreg.h>
   56 
   57 #include "miibus_if.h"
   58 
   59 #include <machine/bus.h>
   60 
   61 static int ciphy_probe(device_t);
   62 static int ciphy_attach(device_t);
   63 
   64 static device_method_t ciphy_methods[] = {
   65         /* device interface */
   66         DEVMETHOD(device_probe,         ciphy_probe),
   67         DEVMETHOD(device_attach,        ciphy_attach),
   68         DEVMETHOD(device_detach,        mii_phy_detach),
   69         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
   70         DEVMETHOD_END
   71 };
   72 
   73 static devclass_t ciphy_devclass;
   74 
   75 static driver_t ciphy_driver = {
   76         "ciphy",
   77         ciphy_methods,
   78         sizeof(struct mii_softc)
   79 };
   80 
   81 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
   82 
   83 static int      ciphy_service(struct mii_softc *, struct mii_data *, int);
   84 static void     ciphy_status(struct mii_softc *);
   85 static void     ciphy_reset(struct mii_softc *);
   86 static void     ciphy_fixup(struct mii_softc *);
   87 
   88 static const struct mii_phydesc ciphys[] = {
   89         MII_PHY_DESC(CICADA, CS8201),
   90         MII_PHY_DESC(CICADA, CS8201A),
   91         MII_PHY_DESC(CICADA, CS8201B),
   92         MII_PHY_DESC(CICADA, CS8204),
   93         MII_PHY_DESC(CICADA, VSC8211),
   94         MII_PHY_DESC(CICADA, CS8244),
   95         MII_PHY_DESC(VITESSE, VSC8601),
   96         MII_PHY_END
   97 };
   98 
   99 static int
  100 ciphy_probe(device_t dev)
  101 {
  102 
  103         return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
  104 }
  105 
  106 static int
  107 ciphy_attach(device_t dev)
  108 {
  109         struct mii_softc *sc;
  110         struct mii_attach_args *ma;
  111         struct mii_data *mii;
  112 
  113         sc = device_get_softc(dev);
  114         ma = device_get_ivars(dev);
  115         sc->mii_dev = device_get_parent(dev);
  116         mii = ma->mii_data;
  117         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
  118 
  119         sc->mii_flags = miibus_get_flags(dev);
  120         sc->mii_inst = mii->mii_instance++;
  121         sc->mii_phy = ma->mii_phyno;
  122         sc->mii_service = ciphy_service;
  123         sc->mii_pdata = mii;
  124 
  125         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOMANPAUSE;
  126 
  127         ciphy_reset(sc);
  128 
  129         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
  130         if (sc->mii_capabilities & BMSR_EXTSTAT)
  131                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
  132         device_printf(dev, " ");
  133         mii_phy_add_media(sc);
  134         printf("\n");
  135 
  136         MIIBUS_MEDIAINIT(sc->mii_dev);
  137         return (0);
  138 }
  139 
  140 static int
  141 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  142 {
  143         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  144         int reg, speed, gig;
  145 
  146         switch (cmd) {
  147         case MII_POLLSTAT:
  148                 break;
  149 
  150         case MII_MEDIACHG:
  151                 /*
  152                  * If the interface is not up, don't do anything.
  153                  */
  154                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  155                         break;
  156 
  157                 ciphy_fixup(sc);        /* XXX hardware bug work-around */
  158 
  159                 switch (IFM_SUBTYPE(ife->ifm_media)) {
  160                 case IFM_AUTO:
  161 #ifdef foo
  162                         /*
  163                          * If we're already in auto mode, just return.
  164                          */
  165                         if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
  166                                 return (0);
  167 #endif
  168                         (void)mii_phy_auto(sc);
  169                         break;
  170                 case IFM_1000_T:
  171                         speed = CIPHY_S1000;
  172                         goto setit;
  173                 case IFM_100_TX:
  174                         speed = CIPHY_S100;
  175                         goto setit;
  176                 case IFM_10_T:
  177                         speed = CIPHY_S10;
  178 setit:
  179                         if ((ife->ifm_media & IFM_FDX) != 0) {
  180                                 speed |= CIPHY_BMCR_FDX;
  181                                 gig = CIPHY_1000CTL_AFD;
  182                         } else
  183                                 gig = CIPHY_1000CTL_AHD;
  184 
  185                         if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
  186                                 gig |= CIPHY_1000CTL_MSE;
  187                                 if ((ife->ifm_media & IFM_ETH_MASTER) != 0 ||
  188                                     (mii->mii_ifp->if_flags & IFF_LINK0) != 0)
  189                                         gig |= CIPHY_1000CTL_MSC;
  190                                 speed |=
  191                                     CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
  192                         } else
  193                                 gig = 0;
  194                         PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
  195                         PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
  196                         PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
  197                         break;
  198                 case IFM_NONE:
  199                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
  200                         break;
  201                 default:
  202                         return (EINVAL);
  203                 }
  204                 break;
  205 
  206         case MII_TICK:
  207                 /*
  208                  * Is the interface even up?
  209                  */
  210                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  211                         return (0);
  212 
  213                 /*
  214                  * Only used for autonegotiation.
  215                  */
  216                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
  217                         break;
  218 
  219                 /*
  220                  * Check to see if we have link.  If we do, we don't
  221                  * need to restart the autonegotiation process.  Read
  222                  * the BMSR twice in case it's latched.
  223                  */
  224                 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
  225                 if (reg & BMSR_LINK)
  226                         break;
  227 
  228                 /* Announce link loss right after it happens. */
  229                 if (++sc->mii_ticks == 0)
  230                         break;
  231                 /*
  232                  * Only retry autonegotiation every mii_anegticks seconds.
  233                  */
  234                 if (sc->mii_ticks <= sc->mii_anegticks)
  235                         break;
  236 
  237                 sc->mii_ticks = 0;
  238                 mii_phy_auto(sc);
  239                 break;
  240         }
  241 
  242         /* Update the media status. */
  243         ciphy_status(sc);
  244 
  245         /*
  246          * Callback if something changed. Note that we need to poke
  247          * apply fixups for certain PHY revs.
  248          */
  249         if (sc->mii_media_active != mii->mii_media_active ||
  250             sc->mii_media_status != mii->mii_media_status ||
  251             cmd == MII_MEDIACHG) {
  252                 ciphy_fixup(sc);
  253         }
  254         mii_phy_update(sc, cmd);
  255         return (0);
  256 }
  257 
  258 static void
  259 ciphy_status(struct mii_softc *sc)
  260 {
  261         struct mii_data *mii = sc->mii_pdata;
  262         int bmsr, bmcr;
  263 
  264         mii->mii_media_status = IFM_AVALID;
  265         mii->mii_media_active = IFM_ETHER;
  266 
  267         bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
  268 
  269         if (bmsr & BMSR_LINK)
  270                 mii->mii_media_status |= IFM_ACTIVE;
  271 
  272         bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
  273 
  274         if (bmcr & CIPHY_BMCR_LOOP)
  275                 mii->mii_media_active |= IFM_LOOP;
  276 
  277         if (bmcr & CIPHY_BMCR_AUTOEN) {
  278                 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
  279                         /* Erg, still trying, I guess... */
  280                         mii->mii_media_active |= IFM_NONE;
  281                         return;
  282                 }
  283         }
  284 
  285         bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
  286         switch (bmsr & CIPHY_AUXCSR_SPEED) {
  287         case CIPHY_SPEED10:
  288                 mii->mii_media_active |= IFM_10_T;
  289                 break;
  290         case CIPHY_SPEED100:
  291                 mii->mii_media_active |= IFM_100_TX;
  292                 break;
  293         case CIPHY_SPEED1000:
  294                 mii->mii_media_active |= IFM_1000_T;
  295                 break;
  296         default:
  297                 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
  298                     bmsr & CIPHY_AUXCSR_SPEED);
  299                 break;
  300         }
  301 
  302         if (bmsr & CIPHY_AUXCSR_FDX)
  303                 mii->mii_media_active |= IFM_FDX;
  304         else
  305                 mii->mii_media_active |= IFM_HDX;
  306 
  307         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
  308            (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
  309                 mii->mii_media_active |= IFM_ETH_MASTER;
  310 }
  311 
  312 static void
  313 ciphy_reset(struct mii_softc *sc)
  314 {
  315 
  316         mii_phy_reset(sc);
  317         DELAY(1000);
  318 }
  319 
  320 #define PHY_SETBIT(x, y, z) \
  321         PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
  322 #define PHY_CLRBIT(x, y, z) \
  323         PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
  324 
  325 static void
  326 ciphy_fixup(struct mii_softc *sc)
  327 {
  328         uint16_t                model;
  329         uint16_t                status, speed;
  330         uint16_t                val;
  331 
  332         model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
  333         status = PHY_READ(sc, CIPHY_MII_AUXCSR);
  334         speed = status & CIPHY_AUXCSR_SPEED;
  335 
  336         if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
  337             "nfe") == 0) {
  338                 /* need to set for 2.5V RGMII for NVIDIA adapters */
  339                 val = PHY_READ(sc, CIPHY_MII_ECTL1);
  340                 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
  341                 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
  342                 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
  343                 /* From Linux. */
  344                 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
  345                 val |= CIPHY_AUXCSR_MDPPS;
  346                 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
  347                 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
  348                 val |= CIPHY_10BTCSR_ECHO;
  349                 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
  350         }
  351 
  352         switch (model) {
  353         case MII_MODEL_CICADA_CS8204:
  354         case MII_MODEL_CICADA_CS8201:
  355 
  356                 /* Turn off "aux mode" (whatever that means) */
  357                 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
  358 
  359                 /*
  360                  * Work around speed polling bug in VT3119/VT3216
  361                  * when using MII in full duplex mode.
  362                  */
  363                 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
  364                     (status & CIPHY_AUXCSR_FDX)) {
  365                         PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  366                 } else {
  367                         PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  368                 }
  369 
  370                 /* Enable link/activity LED blink. */
  371                 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
  372 
  373                 break;
  374 
  375         case MII_MODEL_CICADA_CS8201A:
  376         case MII_MODEL_CICADA_CS8201B:
  377 
  378                 /*
  379                  * Work around speed polling bug in VT3119/VT3216
  380                  * when using MII in full duplex mode.
  381                  */
  382                 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
  383                     (status & CIPHY_AUXCSR_FDX)) {
  384                         PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  385                 } else {
  386                         PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  387                 }
  388 
  389                 break;
  390         case MII_MODEL_CICADA_VSC8211:
  391         case MII_MODEL_CICADA_CS8244:
  392         case MII_MODEL_VITESSE_VSC8601:
  393                 break;
  394         default:
  395                 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
  396                     model);
  397                 break;
  398         }
  399 }

Cache object: 34126ae4bd51b4745af9c7ae70a3c71e


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