ciphy.c

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    1 /*      $OpenBSD: ciphy.c,v 1.28 2022/04/06 18:59:29 naddy Exp $        */
    2 /*      $FreeBSD: ciphy.c,v 1.1 2004/09/10 20:57:45 wpaul Exp $ */
    3 /*
    4  * Copyright (c) 2004
    5  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   34 
   35 /*
   36  * Driver for the Cicada CS8201 10/100/1000 copper PHY.
   37  */
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/kernel.h>
   42 #include <sys/device.h>
   43 #include <sys/socket.h>
   44 #include <sys/errno.h>
   45 
   46 #include <net/if.h>
   47 #include <net/if_var.h>
   48 #include <net/if_media.h>
   49 
   50 #include <dev/mii/mii.h>
   51 #include <dev/mii/miivar.h>
   52 #include <dev/mii/miidevs.h>
   53 
   54 #include <dev/mii/ciphyreg.h>
   55 
   56 int     ciphymatch(struct device *, void *, void *);
   57 void    ciphyattach(struct device *, struct device *, void *);
   58 
   59 const struct cfattach ciphy_ca = {
   60         sizeof(struct mii_softc), ciphymatch, ciphyattach, mii_phy_detach
   61 };
   62 
   63 struct cfdriver ciphy_cd = {
   64         NULL, "ciphy", DV_DULL
   65 };
   66 
   67 int     ciphy_service(struct mii_softc *, struct mii_data *, int);
   68 void    ciphy_status(struct mii_softc *);
   69 void    ciphy_reset(struct mii_softc *);
   70 void    ciphy_fixup(struct mii_softc *);
   71 
   72 const struct mii_phy_funcs ciphy_funcs = {
   73         ciphy_service, ciphy_status, ciphy_reset,
   74 };
   75 
   76 static const struct mii_phydesc ciphys[] = {
   77         { MII_OUI_CICADA,               MII_MODEL_CICADA_CS8201,
   78           MII_STR_CICADA_CS8201 },
   79         { MII_OUI_CICADA,               MII_MODEL_CICADA_CS8201A,
   80           MII_STR_CICADA_CS8201A },
   81         { MII_OUI_CICADA,               MII_MODEL_CICADA_CS8201B,
   82           MII_STR_CICADA_CS8201B },
   83         { MII_OUI_CICADA,               MII_MODEL_CICADA_CS8204,
   84           MII_STR_CICADA_CS8204 },
   85         { MII_OUI_CICADA,               MII_MODEL_CICADA_VSC8211,
   86           MII_STR_CICADA_VSC8211 },
   87         { MII_OUI_CICADA,               MII_MODEL_CICADA_CS8244,
   88           MII_STR_CICADA_CS8244 },
   89         { MII_OUI_xxCICADA,             MII_MODEL_xxCICADA_CS8201B,
   90           MII_STR_xxCICADA_CS8201B },
   91         { MII_OUI_VITESSE,              MII_MODEL_VITESSE_VSC8601,
   92           MII_STR_VITESSE_VSC8601 },
   93 
   94         { 0,                    0,
   95           NULL },
   96 };
   97 
   98 int
   99 ciphymatch(struct device *parent, void *match, void *aux)
  100 {
  101         struct mii_attach_args *ma = aux;
  102 
  103         if (mii_phy_match(ma, ciphys) != NULL)
  104                 return (10);
  105 
  106         return (0);
  107 }
  108 
  109 void
  110 ciphyattach(struct device *parent, struct device *self, void *aux)
  111 {
  112         struct mii_softc *sc = (struct mii_softc *)self;
  113         struct mii_attach_args *ma = aux;
  114         struct mii_data *mii = ma->mii_data;
  115         const struct mii_phydesc *mpd;
  116 
  117         mpd = mii_phy_match(ma, ciphys);
  118         printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
  119 
  120         sc->mii_inst = mii->mii_instance;
  121         sc->mii_phy = ma->mii_phyno;
  122         sc->mii_funcs = &ciphy_funcs;
  123         sc->mii_pdata = mii;
  124         sc->mii_flags = ma->mii_flags;
  125         sc->mii_anegticks = MII_ANEGTICKS;
  126 
  127         sc->mii_flags |= MIIF_NOISOLATE;
  128 
  129         PHY_RESET(sc);
  130 
  131         sc->mii_capabilities =
  132             PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
  133         if (sc->mii_capabilities & BMSR_EXTSTAT)
  134                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
  135         if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
  136             (sc->mii_capabilities & EXTSR_MEDIAMASK))
  137                 mii_phy_add_media(sc);
  138 }
  139 
  140 int
  141 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  142 {
  143         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  144         int reg, speed, gig;
  145 
  146         switch (cmd) {
  147         case MII_POLLSTAT:
  148                 /*
  149                  * If we're not polling our PHY instance, just return.
  150                  */
  151                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  152                         return (0);
  153                 break;
  154 
  155         case MII_MEDIACHG:
  156                 /*
  157                  * If the media indicates a different PHY instance,
  158                  * isolate ourselves.
  159                  */
  160                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
  161                         reg = PHY_READ(sc, MII_BMCR);
  162                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
  163                         return (0);
  164                 }
  165 
  166                 /*
  167                  * If the interface is not up, don't do anything.
  168                  */
  169                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  170                         break;
  171 
  172                 ciphy_fixup(sc);        /* XXX hardware bug work-around */
  173 
  174                 switch (IFM_SUBTYPE(ife->ifm_media)) {
  175                 case IFM_AUTO:
  176                         if (mii_phy_auto(sc, 0) == EJUSTRETURN)
  177                                 return (0);
  178                         break;
  179                 case IFM_1000_T:
  180                         speed = BMCR_S1000;
  181                         goto setit;
  182                 case IFM_100_TX:
  183                         speed = BMCR_S100;
  184                         goto setit;
  185                 case IFM_10_T:
  186                         speed = BMCR_S10;
  187 setit:
  188                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
  189                                 speed |= BMCR_FDX;
  190                                 gig = GTCR_ADV_1000TFDX;
  191                         } else {
  192                                 gig = GTCR_ADV_1000THDX;
  193                         }
  194 
  195                         PHY_WRITE(sc, MII_100T2CR, 0);
  196                         PHY_WRITE(sc, MII_BMCR, speed);
  197                         PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
  198 
  199                         if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 
  200                                 break;
  201 
  202                         PHY_WRITE(sc, MII_100T2CR, gig);
  203                         PHY_WRITE(sc, MII_BMCR,
  204                             speed|BMCR_AUTOEN|BMCR_STARTNEG);
  205 
  206                         if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
  207                                 gig |= GTCR_MAN_MS | GTCR_ADV_MS;
  208                         PHY_WRITE(sc, MII_100T2CR, gig);
  209                         break;
  210                 case IFM_NONE:
  211                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
  212                         break;
  213                 default:
  214                         return (EINVAL);
  215                 }
  216                 break;
  217 
  218         case MII_TICK:
  219                 /*
  220                  * If we're not currently selected, just return.
  221                  */
  222                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  223                         return (0);
  224 
  225                 if (mii_phy_tick(sc) == EJUSTRETURN)
  226                         return (0);
  227                 break;
  228         }
  229 
  230         /* Update the media status. */
  231         mii_phy_status(sc);
  232 
  233         /*
  234          * Callback if something changed. Note that we need to poke
  235          * apply fixups for certain PHY revs.
  236          */
  237         if (sc->mii_media_active != mii->mii_media_active || 
  238             sc->mii_media_status != mii->mii_media_status ||
  239             cmd == MII_MEDIACHG) {
  240                 ciphy_fixup(sc);
  241         }
  242         mii_phy_update(sc, cmd);
  243         return (0);
  244 }
  245 
  246 void
  247 ciphy_status(struct mii_softc *sc)
  248 {
  249         struct mii_data *mii = sc->mii_pdata;
  250         int bmsr, bmcr, gsr;
  251 
  252         mii->mii_media_status = IFM_AVALID;
  253         mii->mii_media_active = IFM_ETHER;
  254 
  255         bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
  256 
  257         if (bmsr & BMSR_LINK)
  258                 mii->mii_media_status |= IFM_ACTIVE;
  259 
  260         bmcr = PHY_READ(sc, MII_BMCR);
  261 
  262         if (bmcr & BMCR_LOOP)
  263                 mii->mii_media_active |= IFM_LOOP;
  264 
  265         if (bmcr & BMCR_AUTOEN) {
  266                 if ((bmsr & BMSR_ACOMP) == 0) {
  267                         /* Erg, still trying, I guess... */
  268                         mii->mii_media_active |= IFM_NONE;
  269                         return;
  270                 }
  271         }
  272 
  273         bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
  274         switch (bmsr & CIPHY_AUXCSR_SPEED) {
  275         case CIPHY_SPEED10:
  276                 mii->mii_media_active |= IFM_10_T;
  277                 break;
  278         case CIPHY_SPEED100:
  279                 mii->mii_media_active |= IFM_100_TX;
  280                 break;
  281         case CIPHY_SPEED1000:
  282                 mii->mii_media_active |= IFM_1000_T;
  283                 break;
  284         default:
  285                 printf("%s: unknown PHY speed %x\n",
  286                     sc->mii_dev.dv_xname, bmsr & CIPHY_AUXCSR_SPEED);
  287                 break;
  288         }
  289 
  290         if (bmsr & CIPHY_AUXCSR_FDX)
  291                 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
  292         else
  293                 mii->mii_media_active |= IFM_HDX;
  294 
  295         gsr = PHY_READ(sc, MII_100T2SR);
  296         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
  297             gsr & GTSR_MS_RES)
  298                 mii->mii_media_active |= IFM_ETH_MASTER;
  299 }
  300 
  301 void
  302 ciphy_reset(struct mii_softc *sc)
  303 {
  304         mii_phy_reset(sc);
  305         DELAY(1000);
  306 }
  307 
  308 #define PHY_SETBIT(x, y, z) \
  309         PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
  310 #define PHY_CLRBIT(x, y, z) \
  311         PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
  312 
  313 void
  314 ciphy_fixup(struct mii_softc *sc)
  315 {
  316         uint16_t                model;
  317         uint16_t                status, speed;
  318 
  319         model = MII_MODEL(PHY_READ(sc, MII_PHYIDR2));
  320         status = PHY_READ(sc, CIPHY_MII_AUXCSR);
  321         speed = status & CIPHY_AUXCSR_SPEED;
  322 
  323         if (strcmp(sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name, "nfe") == 0) {
  324                 /* need to set for 2.5V RGMII for NVIDIA adapters */
  325                 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
  326                 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
  327         }
  328 
  329         switch (model) {
  330         case MII_MODEL_CICADA_CS8201:
  331         case MII_MODEL_CICADA_CS8204:
  332 
  333                 /* Turn off "aux mode" (whatever that means) */
  334                 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
  335 
  336                 /*
  337                  * Work around speed polling bug in VT3119/VT3216
  338                  * when using MII in full duplex mode.
  339                  */
  340                 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
  341                     (status & CIPHY_AUXCSR_FDX)) {
  342                         PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  343                 } else {
  344                         PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  345                 }
  346 
  347                 /* Enable link/activity LED blink. */
  348                 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
  349 
  350                 break;
  351 
  352         case MII_MODEL_CICADA_CS8201A:
  353         case MII_MODEL_CICADA_CS8201B:
  354 
  355                 /*
  356                  * Work around speed polling bug in VT3119/VT3216
  357                  * when using MII in full duplex mode.
  358                  */
  359                 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
  360                     (status & CIPHY_AUXCSR_FDX)) {
  361                         PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  362                 } else {
  363                         PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
  364                 }
  365 
  366                 break;
  367         case MII_MODEL_CICADA_VSC8211:
  368         case MII_MODEL_CICADA_CS8244:
  369         case MII_MODEL_VITESSE_VSC8601:
  370                 break;
  371         default:
  372                 printf("%s: unknown CICADA PHY model %x\n",
  373                     sc->mii_dev.dv_xname, model);
  374                 break;
  375         }
  376 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/mii/ciphy.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/ciphy.c
