The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/ciphyreg.h

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    1 /*-
    2  * Copyright (c) 2004
    3  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 #ifndef _DEV_MII_CIPHYREG_H_
   36 #define _DEV_MII_CIPHYREG_H_
   37 
   38 /*
   39  * Register definitions for the Cicada CS8201 10/100/1000 gigE copper
   40  * PHY, embedded within the VIA Networks VT6122 controller.
   41  */
   42 
   43 /* Command register */
   44 #define CIPHY_MII_BMCR          0x00
   45 #define CIPHY_BMCR_RESET        0x8000
   46 #define CIPHY_BMCR_LOOP         0x4000
   47 #define CIPHY_BMCR_SPD0         0x2000  /* speed select, lower bit */
   48 #define CIPHY_BMCR_AUTOEN       0x1000  /* Autoneg enabled */
   49 #define CIPHY_BMCR_PDOWN        0x0800  /* Power down */
   50 #define CIPHY_BMCR_STARTNEG     0x0200  /* Restart autoneg */
   51 #define CIPHY_BMCR_FDX          0x0100  /* Duplex mode */
   52 #define CIPHY_BMCR_CTEST        0x0080  /* Collision test enable */
   53 #define CIPHY_BMCR_SPD1         0x0040  /* Speed select, upper bit */
   54 
   55 #define CIPHY_S1000             CIPHY_BMCR_SPD1 /* 1000mbps */
   56 #define CIPHY_S100              CIPHY_BMCR_SPD0 /* 100mpbs */
   57 #define CIPHY_S10               0               /* 10mbps */
   58 
   59 /* Status register */
   60 #define CIPHY_MII_BMSR          0x01
   61 #define CIPHY_BMSR_100T4        0x8000  /* 100 base T4 capable */
   62 #define CIPHY_BMSR_100TXFDX     0x4000  /* 100 base Tx full duplex capable */
   63 #define CIPHY_BMSR_100TXHDX     0x2000  /* 100 base Tx half duplex capable */
   64 #define CIPHY_BMSR_10TFDX       0x1000  /* 10 base T full duplex capable */
   65 #define CIPHY_BMSR_10THDX       0x0800  /* 10 base T half duplex capable */
   66 #define CIPHY_BMSR_100T2FDX     0x0400  /* 100 base T2 full duplex capable */
   67 #define CIPHY_BMSR_100T2HDX     0x0200  /* 100 base T2 half duplex capable */
   68 #define CIPHY_BMSR_EXTSTS       0x0100  /* Extended status present */
   69 #define CIPHY_BMSR_PRESUB       0x0040  /* Preamble surpression */
   70 #define CIPHY_BMSR_ACOMP        0x0020  /* Autoneg complete */
   71 #define CIPHY_BMSR_RFAULT       0x0010  /* Remote fault condition occured */
   72 #define CIPHY_BMSR_ANEG         0x0008  /* Autoneg capable */
   73 #define CIPHY_BMSR_LINK         0x0004  /* Link status */
   74 #define CIPHY_BMSR_JABBER       0x0002  /* Jabber detected */
   75 #define CIPHY_BMSR_EXT          0x0001  /* Extended capability */
   76 
   77 /* PHY ID registers */
   78 #define CIPHY_MII_PHYIDR1       0x02
   79 #define CIPHY_MII_PHYIDR2       0x03
   80 
   81 /* Autoneg advertisement */
   82 #define CIPHY_MII_ANAR          0x04
   83 #define CIPHY_ANAR_NP           0x8000  /* Next page */
   84 #define CIPHY_ANAR_RF           0x2000  /* Remote fault */
   85 #define CIPHY_ANAR_ASP          0x0800  /* Asymmetric Pause */
   86 #define CIPHY_ANAR_PC           0x0400  /* Pause capable */
   87 #define CIPHY_ANAR_T4           0x0200  /* local device supports 100bT4 */
   88 #define CIPHY_ANAR_TX_FD        0x0100  /* local device supports 100bTx FD */
   89 #define CIPHY_ANAR_TX           0x0080  /* local device supports 100bTx */
   90 #define CIPHY_ANAR_10_FD        0x0040  /* local device supports 10bT FD */
   91 #define CIPHY_ANAR_10           0x0020  /* local device supports 10bT */
   92 #define CIPHY_ANAR_SEL          0x001F  /* selector field, 00001=Ethernet */
   93 
   94 /* Autoneg link partner ability */
   95 #define CIPHY_MII_ANLPAR        0x05
   96 #define CIPHY_ANLPAR_NP         0x8000  /* Next page */
   97 #define CIPHY_ANLPAR_ACK        0x4000  /* link partner acknowledge */
   98 #define CIPHY_ANLPAR_RF         0x2000  /* Remote fault */
   99 #define CIPHY_ANLPAR_ASP        0x0800  /* Asymmetric Pause */
  100 #define CIPHY_ANLPAR_PC         0x0400  /* Pause capable */
  101 #define CIPHY_ANLPAR_T4         0x0200  /* link partner supports 100bT4 */
  102 #define CIPHY_ANLPAR_TX_FD      0x0100  /* link partner supports 100bTx FD */
  103 #define CIPHY_ANLPAR_TX         0x0080  /* link partner supports 100bTx */
  104 #define CIPHY_ANLPAR_10_FD      0x0040  /* link partner supports 10bT FD */
  105 #define CIPHY_ANLPAR_10         0x0020  /* link partner supports 10bT */
  106 #define CIPHY_ANLPAR_SEL        0x001F  /* selector field, 00001=Ethernet */
  107 
  108 #define CIPHY_SEL_TYPE          0x0001  /* ethernet */
  109 
  110 /* Antoneg expansion register */
  111 #define CIPHY_MII_ANER          0x06
  112 #define CIPHY_ANER_PDF          0x0010  /* Parallel detection fault */
  113 #define CIPHY_ANER_LPNP         0x0008  /* Link partner can next page */
  114 #define CIPHY_ANER_NP           0x0004  /* Local PHY can next page */
  115 #define CIPHY_ANER_RX           0x0002  /* Next page received */
  116 #define CIPHY_ANER_LPAN         0x0001  /* Link partner autoneg capable */
  117 
  118 /* Autoneg next page transmit regisyer */
  119 #define CIPHY_MII_NEXTP         0x07
  120 #define CIPHY_NEXTP_MOREP       0x8000  /* More pages to follow */
  121 #define CIPHY_NEXTP_MESS        0x2000  /* 1 = message page, 0 = unformatted */
  122 #define CIPHY_NEXTP_ACK2        0x1000  /* MAC acknowledge */
  123 #define CIPHY_NEXTP_TOGGLE      0x0800  /* Toggle */
  124 #define CIPHY_NEXTP_CODE        0x07FF  /* Code bits */
  125 
  126 /* Autoneg link partner next page receive register */
  127 #define CIPHY_MII_NEXTP_LP      0x08
  128 #define CIPHY_NEXTPLP_MOREP     0x8000  /* More pages to follow */
  129 #define CIPHY_NEXTPLP_MESS      0x2000  /* 1 = message page, 0 = unformatted */
  130 #define CIPHY_NEXTPLP_ACK2      0x1000  /* MAC acknowledge */
  131 #define CIPHY_NEXTPLP_TOGGLE    0x0800  /* Toggle */
  132 #define CIPHY_NEXTPLP_CODE      0x07FF  /* Code bits */
  133 
  134 /* 1000BT control register */
  135 #define CIPHY_MII_1000CTL       0x09
  136 #define CIPHY_1000CTL_TST       0xE000  /* test modes */
  137 #define CIPHY_1000CTL_MSE       0x1000  /* Master/Slave manual enable */
  138 #define CIPHY_1000CTL_MSC       0x0800  /* Master/Slave select */
  139 #define CIPHY_1000CTL_RD        0x0400  /* Repeater/DTE */
  140 #define CIPHY_1000CTL_AFD       0x0200  /* Advertise full duplex */
  141 #define CIPHY_1000CTL_AHD       0x0100  /* Advertise half duplex */
  142 
  143 #define CIPHY_TEST_TX_JITTER                    0x2000
  144 #define CIPHY_TEST_TX_JITTER_MASTER_MODE        0x4000
  145 #define CIPHY_TEST_TX_JITTER_SLAVE_MODE         0x6000
  146 #define CIPHY_TEST_TX_DISTORTION                0x8000
  147 
  148 /* 1000BT status register */
  149 #define CIPHY_MII_1000STS       0x0A
  150 #define CIPHY_1000STS_MSF       0x8000  /* Master/slave fault */
  151 #define CIPHY_1000STS_MSR       0x4000  /* Master/slave result */
  152 #define CIPHY_1000STS_LRS       0x2000  /* Local receiver status */
  153 #define CIPHY_1000STS_RRS       0x1000  /* Remote receiver status */
  154 #define CIPHY_1000STS_LPFD      0x0800  /* Link partner can FD */
  155 #define CIPHY_1000STS_LPHD      0x0400  /* Link partner can HD */
  156 #define CIPHY_1000STS_IEC       0x00FF  /* Idle error count */
  157 
  158 #define CIPHY_MII_EXTSTS        0x0F    /* Extended status */
  159 #define CIPHY_EXTSTS_X_FD_CAP   0x8000  /* 1000base-X FD capable */
  160 #define CIPHY_EXTSTS_X_HD_CAP   0x4000  /* 1000base-X HD capable */
  161 #define CIPHY_EXTSTS_T_FD_CAP   0x2000  /* 1000base-T FD capable */
  162 #define CIPHY_EXTSTS_T_HD_CAP   0x1000  /* 1000base-T HD capable */
  163 
  164 /* 1000BT status extension register #1 */
  165 #define CIPHY_MII_1000STS1      0x0F
  166 #define CIPHY_1000STS1_1000XFDX 0x8000  /* 1000baseX FDX capable */
  167 #define CIPHY_1000STS1_1000XHDX 0x4000  /* 1000baseX HDX capable */
  168 #define CIPHY_1000STS1_1000TFDX 0x2000  /* 1000baseT FDX capable */
  169 #define CIPHY_1000STS1_1000THDX 0x1000  /* 1000baseT HDX capable */
  170 
  171 /* Vendor-specific PHY registers */
  172 
  173 /* 100baseTX status extention register */
  174 #define CIPHY_MII_100STS        0x10
  175 #define CIPHY_100STS_DESLCK     0x8000  /* descrambler locked */
  176 #define CIPHY_100STS_LKCERR     0x4000  /* lock error detected/lock lost */
  177 #define CIPHY_100STS_DISC       0x2000  /* disconnect state */
  178 #define CIPHY_100STS_LINK       0x1000  /* current link state */
  179 #define CIPHY_100STS_RXERR      0x0800  /* receive error detected */
  180 #define CIPHY_100STS_TXERR      0x0400  /* transmit error detected */
  181 #define CIPHY_100STS_SSDERR     0x0200  /* false carrier error detected */
  182 #define CIPHY_100STS_ESDERR     0x0100  /* premature end of stream error */
  183 
  184 /* 1000BT status extention register #2 */
  185 #define CIPHY_MII_1000STS2      0x11
  186 #define CIPHY_1000STS2_DESLCK   0x8000  /* descrambler locked */
  187 #define CIPHY_1000STS2_LKCERR   0x4000  /* lock error detected/lock lost */
  188 #define CIPHY_1000STS2_DISC     0x2000  /* disconnect state */
  189 #define CIPHY_1000STS2_LINK     0x1000  /* current link state */
  190 #define CIPHY_1000STS2_RXERR    0x0800  /* receive error detected */
  191 #define CIPHY_1000STS2_TXERR    0x0400  /* transmit error detected */
  192 #define CIPHY_1000STS2_SSDERR   0x0200  /* false carrier error detected */
  193 #define CIPHY_1000STS2_ESDERR   0x0100  /* premature end of stream error */
  194 #define CIPHY_1000STS2_CARREXT  0x0080  /* carrier extention err detected */
  195 #define CIPHY_1000STS2_BCM5400  0x0040  /* non-complient BCM5400 detected */
  196 
  197 /* Bypass control register */
  198 #define CIPHY_MII_BYPASS        0x12
  199 #define CIPHY_BYPASS_TX         0x8000  /* transmit disable */
  200 #define CIPHY_BYPASS_4B5B       0x4000  /* bypass the 4B5B encoder */
  201 #define CIPHY_BYPASS_SCRAM      0x2000  /* bypass scrambler */
  202 #define CIPHY_BYPASS_DSCAM      0x1000  /* bypass descrambler */
  203 #define CIPHY_BYPASS_PCSRX      0x0800  /* bypass PCS receive */
  204 #define CIPHY_BYPASS_PCSTX      0x0400  /* bypass PCS transmit */
  205 #define CIPHY_BYPASS_LFI        0x0200  /* bypass LFI timer */
  206 #define CIPHY_BYPASS_TXCLK      0x0100  /* enable transmit clock on LED4 pin */
  207 #define CIPHY_BYPASS_BCM5400_F  0x0080  /* force BCM5400 detect */
  208 #define CIPHY_BYPASS_BCM5400    0x0040  /* bypass BCM5400 detect */
  209 #define CIPHY_BYPASS_PAIRSWAP   0x0020  /* disable automatic pair swap */
  210 #define CIPHY_BYPASS_POLARITY   0x0010  /* disable polarity correction */
  211 #define CIPHY_BYPASS_PARALLEL   0x0008  /* parallel detect enable */
  212 #define CIPHY_BYPASS_PULSE      0x0004  /* disable pulse shaping filter */
  213 #define CIPHY_BYPASS_1000BNP    0x0002  /* disable 1000BT next page exchange */
  214 
  215 /* RX error count register */
  216 #define CIPHY_MII_RXERR         0x13
  217 
  218 /* False carrier sense count register */
  219 #define CIPHY_MII_FCSERR        0x14
  220 
  221 /* Ddisconnect error counter */
  222 #define CIPHY_MII_DISCERR       0x15
  223 
  224 /* 10baseT control/status register */
  225 #define CIPHY_MII_10BTCSR       0x16
  226 #define CIPHY_10BTCSR_DLIT      0x8000  /* Disable data link integrity test */
  227 #define CIPHY_10BTCSR_JABBER    0x4000  /* Disable jabber detect */
  228 #define CIPHY_10BTCSR_ECHO      0x2000  /* Disable echo mode */
  229 #define CIPHY_10BTCSR_SQE       0x1000  /* Disable signal quality error */
  230 #define CIPHY_10BTCSR_SQUENCH   0x0C00  /* Squelch control */
  231 #define CIPHY_10BTCSR_EOFERR    0x0100  /* End of Frame error */
  232 #define CIPHY_10BTCSR_DISC      0x0080  /* Disconnect status */
  233 #define CIPHY_10BTCSR_LINK      0x0040  /* current link state */
  234 #define CIPHY_10BTCSR_ITRIM     0x0038  /* current reference trim */
  235 #define CIPHY_10BTCSR_CSR       0x0006  /* CSR behavior control */
  236 
  237 #define CIPHY_SQUELCH_300MV     0x0000
  238 #define CIPHY_SQUELCH_197MV     0x0400
  239 #define CIPHY_SQUELCH_450MV     0x0800
  240 #define CIPHY_SQUELCH_RSVD      0x0C00
  241 
  242 #define CIPHY_ITRIM_PLUS2       0x0000
  243 #define CIPHY_ITRIM_PLUS4       0x0008
  244 #define CIPHY_ITRIM_PLUS6       0x0010
  245 #define CIPHY_ITRIM_PLUS6_      0x0018
  246 #define CIPHY_ITRIM_MINUS4      0x0020
  247 #define CIPHY_ITRIM_MINUS4_     0x0028
  248 #define CIPHY_ITRIM_MINUS2      0x0030
  249 #define CIPHY_ITRIM_ZERO        0x0038
  250 
  251 /* Extended PHY control register #1 */
  252 #define CIPHY_MII_ECTL1         0x17
  253 #define CIPHY_ECTL1_ACTIPHY     0x0020  /* Enable ActiPHY power saving */
  254 #define CIPHY_ECTL1_IOVOL       0x0e00  /* MAC interface and I/O voltage select */
  255 #define CIPHY_ECTL1_INTSEL      0xf000  /* select MAC interface */
  256 
  257 #define CIPHY_IOVOL_3300MV      0x0000  /* 3.3V for I/O pins */
  258 #define CIPHY_IOVOL_2500MV      0x0200  /* 2.5V for I/O pins */
  259 
  260 #define CIPHY_INTSEL_GMII       0x0000  /* GMII/MII */
  261 #define CIPHY_INTSEL_RGMII      0x1000
  262 #define CIPHY_INTSEL_TBI        0x2000
  263 #define CIPHY_INTSEL_RTBI       0x3000
  264 
  265 /* Extended PHY control register #2 */
  266 #define CIPHY_MII_ECTL2         0x18
  267 #define CIPHY_ECTL2_ERATE       0xE000  /* 10/1000 edge rate control */
  268 #define CIPHY_ECTL2_VTRIM       0x1C00  /* voltage reference trim */
  269 #define CIPHY_ECTL2_CABLELEN    0x000E  /* Cable quality/length */
  270 #define CIPHY_ECTL2_ANALOGLOOP  0x0001  /* 1000BT analog loopback */
  271 
  272 #define CIPHY_CABLELEN_0TO10M           0x0000
  273 #define CIPHY_CABLELEN_10TO20M          0x0002
  274 #define CIPHY_CABLELEN_20TO40M          0x0004
  275 #define CIPHY_CABLELEN_40TO80M          0x0006
  276 #define CIPHY_CABLELEN_80TO100M         0x0008
  277 #define CIPHY_CABLELEN_100TO140M        0x000A
  278 #define CIPHY_CABLELEN_140TO180M        0x000C
  279 #define CIPHY_CABLELEN_OVER180M         0x000E
  280 
  281 /* Interrupt mask register */
  282 #define CIPHY_MII_IMR           0x19
  283 #define CIPHY_IMR_PINENABLE     0x8000  /* Interrupt pin enable */
  284 #define CIPHY_IMR_SPEED         0x4000  /* speed changed event */
  285 #define CIPHY_IMR_LINK          0x2000  /* link change/ActiPHY event */
  286 #define CIPHY_IMR_DPX           0x1000  /* duplex change event */
  287 #define CIPHY_IMR_ANEGERR       0x0800  /* autoneg error event */
  288 #define CIPHY_IMR_ANEGDONE      0x0400  /* autoneg done event */
  289 #define CIPHY_IMR_NPRX          0x0200  /* page received event */
  290 #define CIPHY_IMR_SYMERR        0x0100  /* symbol error event */
  291 #define CIPHY_IMR_LOCKERR       0x0080  /* descrambler lock lost event */
  292 #define CIPHY_IMR_XOVER         0x0040  /* MDI crossover change event */
  293 #define CIPHY_IMR_POLARITY      0x0020  /* polarity change event */
  294 #define CIPHY_IMR_JABBER        0x0010  /* jabber detect event */
  295 #define CIPHY_IMR_SSDERR        0x0008  /* false carrier detect event */
  296 #define CIPHY_IMR_ESDERR        0x0004  /* parallel detect error event */
  297 #define CIPHY_IMR_MASTERSLAVE   0x0002  /* master/slave resolve done event */
  298 #define CIPHY_IMR_RXERR         0x0001  /* RX error event */
  299 
  300 /* Interrupt status register */
  301 #define CIPHY_MII_ISR           0x1A
  302 #define CIPHY_ISR_IPENDING      0x8000  /* Interrupt is pending */
  303 #define CIPHY_ISR_SPEED         0x4000  /* speed changed event */
  304 #define CIPHY_ISR_LINK          0x2000  /* link change/ActiPHY event */
  305 #define CIPHY_ISR_DPX           0x1000  /* duplex change event */
  306 #define CIPHY_ISR_ANEGERR       0x0800  /* autoneg error event */
  307 #define CIPHY_ISR_ANEGDONE      0x0400  /* autoneg done event */
  308 #define CIPHY_ISR_NPRX          0x0200  /* page received event */
  309 #define CIPHY_ISR_SYMERR        0x0100  /* symbol error event */
  310 #define CIPHY_ISR_LOCKERR       0x0080  /* descrambler lock lost event */
  311 #define CIPHY_ISR_XOVER         0x0040  /* MDI crossover change event */
  312 #define CIPHY_ISR_POLARITY      0x0020  /* polarity change event */
  313 #define CIPHY_ISR_JABBER        0x0010  /* jabber detect event */
  314 #define CIPHY_ISR_SSDERR        0x0008  /* false carrier detect event */
  315 #define CIPHY_ISR_ESDERR        0x0004  /* parallel detect error event */
  316 #define CIPHY_ISR_MASTERSLAVE   0x0002  /* master/slave resolve done event */
  317 #define CIPHY_ISR_RXERR         0x0001  /* RX error event */
  318 
  319 /* LED control register */
  320 #define CIPHY_MII_LED           0x1B
  321 #define CIPHY_LED_LINK10FORCE   0x8000  /* Force on link10 LED */
  322 #define CIPHY_LED_LINK10DIS     0x4000  /* Disable link10 LED */
  323 #define CIPHY_LED_LINK100FORCE  0x2000  /* Force on link10 LED */
  324 #define CIPHY_LED_LINK100DIS    0x1000  /* Disable link100 LED */
  325 #define CIPHY_LED_LINK1000FORCE 0x0800  /* Force on link1000 LED */
  326 #define CIPHY_LED_LINK1000DIS   0x0400  /* Disable link1000 LED */
  327 #define CIPHY_LED_FDXFORCE      0x0200  /* Force on duplex LED */
  328 #define CIPHY_LED_FDXDIS        0x0100  /* Disable duplex LED */
  329 #define CIPHY_LED_ACTFORCE      0x0080  /* Force on activity LED */
  330 #define CIPHY_LED_ACTDIS        0x0040  /* Disable activity LED */
  331 #define CIPHY_LED_PULSE         0x0008  /* LED pulse enable */
  332 #define CIPHY_LED_LINKACTBLINK  0x0004  /* enable link/activity LED blink */
  333 #define CIPHY_LED_BLINKRATE     0x0002  /* blink rate 0=10hz, 1=5hz */
  334 
  335 /* Auxilliary control and status register */
  336 #define CIPHY_MII_AUXCSR        0x1C
  337 #define CIPHY_AUXCSR_ANEGDONE   0x8000  /* Autoneg complete */
  338 #define CIPHY_AUXCSR_ANEGOFF    0x4000  /* Autoneg disabled */
  339 #define CIPHY_AUXCSR_XOVER      0x2000  /* MDI/MDI-X crossover indication */
  340 #define CIPHY_AUXCSR_PAIRSWAP   0x1000  /* pair swap indication */
  341 #define CIPHY_AUXCSR_APOLARITY  0x0800  /* polarity inversion pair A */
  342 #define CIPHY_AUXCSR_BPOLARITY  0x0400  /* polarity inversion pair B */
  343 #define CIPHY_AUXCSR_CPOLARITY  0x0200  /* polarity inversion pair C */
  344 #define CIPHY_AUXCSR_DPOLARITY  0x0100  /* polarity inversion pair D */
  345 #define CIPHY_AUXCSR_FDX        0x0020  /* duplex 1=full, 0=half */
  346 #define CIPHY_AUXCSR_SPEED      0x0018  /* speed */
  347 #define CIPHY_AUXCSR_MDPPS      0x0004  /* No idea, not documented */
  348 #define CIPHY_AUXCSR_STICKYREST 0x0002  /* reset clears sticky bits */
  349 
  350 #define CIPHY_SPEED10           0x0000
  351 #define CIPHY_SPEED100          0x0008
  352 #define CIPHY_SPEED1000         0x0010
  353 
  354 /* Delay skew status register */
  355 #define CIPHY_MII_DSKEW         0x1D
  356 #define CIPHY_DSKEW_PAIRA       0x7000  /* Pair A skew in symbol times */
  357 #define CIPHY_DSKEW_PAIRB       0x0700  /* Pair B skew in symbol times */
  358 #define CIPHY_DSKEW_PAIRC       0x0070  /* Pair C skew in symbol times */
  359 #define CIPHY_DSKEW_PAIRD       0x0007  /* Pair D skew in symbol times */
  360 
  361 #endif /* _DEV_CIPHY_MIIREG_H_ */

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