Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/dcphy.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: releng/5.0/sys/dev/mii/dcphy.c 105135 2002-10-14 22:31:52Z alfred $ 33 */ 34 35 /* 36 * Pseudo-driver for internal NWAY support on DEC 21143 and workalike 37 * controllers. Technically we're abusing the miibus code to handle 38 * media selection and NWAY support here since there is no MII 39 * interface. However the logical operations are roughly the same, 40 * and the alternative is to create a fake MII interface in the driver, 41 * which is harder to do. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/errno.h> 49 #include <sys/lock.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/if_media.h> 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 #include <dev/mii/miidevs.h> 61 62 #include <machine/bus_pio.h> 63 #include <machine/bus_memio.h> 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 #include <sys/bus.h> 67 68 #include <pci/pcivar.h> 69 70 #include <pci/if_dcreg.h> 71 72 #include "miibus_if.h" 73 74 #if !defined(lint) 75 static const char rcsid[] = 76 "$FreeBSD: releng/5.0/sys/dev/mii/dcphy.c 105135 2002-10-14 22:31:52Z alfred $"; 77 #endif 78 79 #define DC_SETBIT(sc, reg, x) \ 80 CSR_WRITE_4(sc, reg, \ 81 CSR_READ_4(sc, reg) | x) 82 83 #define DC_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, \ 85 CSR_READ_4(sc, reg) & ~x) 86 87 #define MIIF_AUTOTIMEOUT 0x0004 88 89 /* 90 * This is the subsystem ID for the built-in 21143 ethernet 91 * in several Compaq Presario systems. Apparently these are 92 * 10Mbps only, so we need to treat them specially. 93 */ 94 #define COMPAQ_PRESARIO_ID 0xb0bb0e11 95 96 static int dcphy_probe(device_t); 97 static int dcphy_attach(device_t); 98 99 static device_method_t dcphy_methods[] = { 100 /* device interface */ 101 DEVMETHOD(device_probe, dcphy_probe), 102 DEVMETHOD(device_attach, dcphy_attach), 103 DEVMETHOD(device_detach, mii_phy_detach), 104 DEVMETHOD(device_shutdown, bus_generic_shutdown), 105 { 0, 0 } 106 }; 107 108 static devclass_t dcphy_devclass; 109 110 static driver_t dcphy_driver = { 111 "dcphy", 112 dcphy_methods, 113 sizeof(struct mii_softc) 114 }; 115 116 DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0); 117 118 static int dcphy_service(struct mii_softc *, struct mii_data *, int); 119 static void dcphy_status(struct mii_softc *); 120 static void dcphy_reset(struct mii_softc *); 121 static int dcphy_auto(struct mii_softc *); 122 123 static int 124 dcphy_probe(dev) 125 device_t dev; 126 { 127 struct mii_attach_args *ma; 128 129 ma = device_get_ivars(dev); 130 131 /* 132 * The dc driver will report the 21143 vendor and device 133 * ID to let us know that it wants us to attach. 134 */ 135 if (ma->mii_id1 != DC_VENDORID_DEC || 136 ma->mii_id2 != DC_DEVICEID_21143) 137 return(ENXIO); 138 139 device_set_desc(dev, "Intel 21143 NWAY media interface"); 140 141 return (0); 142 } 143 144 static int 145 dcphy_attach(dev) 146 device_t dev; 147 { 148 struct mii_softc *sc; 149 struct mii_attach_args *ma; 150 struct mii_data *mii; 151 struct dc_softc *dc_sc; 152 153 sc = device_get_softc(dev); 154 ma = device_get_ivars(dev); 155 sc->mii_dev = device_get_parent(dev); 156 mii = device_get_softc(sc->mii_dev); 157 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 158 159 sc->mii_inst = mii->mii_instance; 160 sc->mii_phy = ma->mii_phyno; 161 sc->mii_service = dcphy_service; 162 sc->mii_pdata = mii; 163 164 sc->mii_flags |= MIIF_NOISOLATE; 165 mii->mii_instance++; 166 167 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 168 169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 170 BMCR_ISO); 171 172 /*dcphy_reset(sc);*/ 173 dc_sc = mii->mii_ifp->if_softc; 174 CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); 175 CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); 176 177 switch(pci_read_config(device_get_parent(sc->mii_dev), 178 DC_PCI_CSID, 4)) { 179 case COMPAQ_PRESARIO_ID: 180 /* Example of how to only allow 10Mbps modes. */ 181 sc->mii_capabilities = BMSR_ANEG|BMSR_10TFDX|BMSR_10THDX; 182 break; 183 default: 184 if (dc_sc->dc_pmode == DC_PMODE_SIA) { 185 sc->mii_capabilities = 186 BMSR_ANEG|BMSR_10TFDX|BMSR_10THDX; 187 } else { 188 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, 189 sc->mii_inst), BMCR_LOOP|BMCR_S100); 190 191 sc->mii_capabilities = 192 BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX| 193 BMSR_10TFDX|BMSR_10THDX; 194 } 195 break; 196 } 197 198 sc->mii_capabilities &= ma->mii_capmask; 199 device_printf(dev, " "); 200 mii_add_media(sc); 201 printf("\n"); 202 #undef ADD 203 204 MIIBUS_MEDIAINIT(sc->mii_dev); 205 return(0); 206 } 207 208 static int 209 dcphy_service(sc, mii, cmd) 210 struct mii_softc *sc; 211 struct mii_data *mii; 212 int cmd; 213 { 214 struct dc_softc *dc_sc; 215 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 216 int reg; 217 u_int32_t mode; 218 219 dc_sc = mii->mii_ifp->if_softc; 220 221 switch (cmd) { 222 case MII_POLLSTAT: 223 /* 224 * If we're not polling our PHY instance, just return. 225 */ 226 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 227 return (0); 228 } 229 break; 230 231 case MII_MEDIACHG: 232 /* 233 * If the media indicates a different PHY instance, 234 * isolate ourselves. 235 */ 236 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 237 return (0); 238 } 239 240 /* 241 * If the interface is not up, don't do anything. 242 */ 243 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 244 break; 245 246 sc->mii_flags = 0; 247 mii->mii_media_active = IFM_NONE; 248 mode = CSR_READ_4(dc_sc, DC_NETCFG); 249 mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL| 250 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL); 251 252 switch (IFM_SUBTYPE(ife->ifm_media)) { 253 case IFM_AUTO: 254 /*dcphy_reset(sc);*/ 255 (void) dcphy_auto(sc); 256 break; 257 case IFM_100_T4: 258 /* 259 * XXX Not supported as a manual setting right now. 260 */ 261 return (EINVAL); 262 case IFM_100_TX: 263 dcphy_reset(sc); 264 DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 265 mode |= DC_NETCFG_PORTSEL|DC_NETCFG_PCS| 266 DC_NETCFG_SCRAMBLER; 267 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) 268 mode |= DC_NETCFG_FULLDUPLEX; 269 else 270 mode &= ~DC_NETCFG_FULLDUPLEX; 271 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); 272 break; 273 case IFM_10_T: 274 DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); 275 DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF); 276 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) 277 DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D); 278 else 279 DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F); 280 DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); 281 DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 282 mode &= ~DC_NETCFG_PORTSEL; 283 mode |= DC_NETCFG_SPEEDSEL; 284 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) 285 mode |= DC_NETCFG_FULLDUPLEX; 286 else 287 mode &= ~DC_NETCFG_FULLDUPLEX; 288 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); 289 break; 290 default: 291 return(EINVAL); 292 break; 293 } 294 break; 295 296 case MII_TICK: 297 /* 298 * If we're not currently selected, just return. 299 */ 300 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 301 return (0); 302 303 /* 304 * Is the interface even up? 305 */ 306 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 307 return (0); 308 309 /* 310 * Only used for autonegotiation. 311 */ 312 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 313 break; 314 315 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); 316 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) 317 break; 318 319 /* 320 * Only retry autonegotiation every 5 seconds. 321 * 322 * Otherwise, fall through to calling dcphy_status() 323 * since real Intel 21143 chips don't show valid link 324 * status until autonegotiation is switched off, and 325 * that only happens in dcphy_status(). Without this, 326 * successful autonegotation is never recognised on 327 * these chips. 328 */ 329 if (++sc->mii_ticks != 50) 330 break; 331 332 sc->mii_ticks = 0; 333 dcphy_auto(sc); 334 335 break; 336 } 337 338 /* Update the media status. */ 339 dcphy_status(sc); 340 341 /* Callback if something changed. */ 342 mii_phy_update(sc, cmd); 343 return (0); 344 } 345 346 static void 347 dcphy_status(sc) 348 struct mii_softc *sc; 349 { 350 struct mii_data *mii = sc->mii_pdata; 351 int reg, anlpar, tstat = 0; 352 struct dc_softc *dc_sc; 353 354 dc_sc = mii->mii_ifp->if_softc; 355 356 mii->mii_media_status = IFM_AVALID; 357 mii->mii_media_active = IFM_ETHER; 358 359 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 360 return; 361 362 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); 363 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) 364 mii->mii_media_status |= IFM_ACTIVE; 365 366 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { 367 /* Erg, still trying, I guess... */ 368 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); 369 if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) { 370 if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) && 371 (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE) 372 goto skip; 373 mii->mii_media_active |= IFM_NONE; 374 return; 375 } 376 377 if (tstat & DC_TSTAT_LP_CAN_NWAY) { 378 anlpar = tstat >> 16; 379 if (anlpar & ANLPAR_T4 && 380 sc->mii_capabilities & BMSR_100TXHDX) 381 mii->mii_media_active |= IFM_100_T4; 382 else if (anlpar & ANLPAR_TX_FD && 383 sc->mii_capabilities & BMSR_100TXFDX) 384 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 385 else if (anlpar & ANLPAR_TX && 386 sc->mii_capabilities & BMSR_100TXHDX) 387 mii->mii_media_active |= IFM_100_TX; 388 else if (anlpar & ANLPAR_10_FD) 389 mii->mii_media_active |= IFM_10_T|IFM_FDX; 390 else if (anlpar & ANLPAR_10) 391 mii->mii_media_active |= IFM_10_T; 392 else 393 mii->mii_media_active |= IFM_NONE; 394 if (DC_IS_INTEL(dc_sc)) 395 DC_CLRBIT(dc_sc, DC_10BTCTRL, 396 DC_TCTL_AUTONEGENBL); 397 return; 398 } 399 /* 400 * If the other side doesn't support NWAY, then the 401 * best we can do is determine if we have a 10Mbps or 402 * 100Mbps link. There's no way to know if the link 403 * is full or half duplex, so we default to half duplex 404 * and hope that the user is clever enough to manually 405 * change the media settings if we're wrong. 406 */ 407 if (!(reg & DC_TSTAT_LS100)) 408 mii->mii_media_active |= IFM_100_TX; 409 else if (!(reg & DC_TSTAT_LS10)) 410 mii->mii_media_active |= IFM_10_T; 411 else 412 mii->mii_media_active |= IFM_NONE; 413 if (DC_IS_INTEL(dc_sc)) 414 DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 415 return; 416 } 417 418 skip: 419 420 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) 421 mii->mii_media_active |= IFM_10_T; 422 else 423 mii->mii_media_active |= IFM_100_TX; 424 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) 425 mii->mii_media_active |= IFM_FDX; 426 427 return; 428 } 429 430 static int 431 dcphy_auto(mii) 432 struct mii_softc *mii; 433 { 434 struct dc_softc *sc; 435 436 sc = mii->mii_pdata->mii_ifp->if_softc; 437 438 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 440 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 441 if (mii->mii_capabilities & BMSR_100TXHDX) 442 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); 443 else 444 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); 445 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 446 DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 447 DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE); 448 449 return(EJUSTRETURN); 450 } 451 452 static void 453 dcphy_reset(mii) 454 struct mii_softc *mii; 455 { 456 struct dc_softc *sc; 457 458 sc = mii->mii_pdata->mii_ifp->if_softc; 459 460 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 461 DELAY(1000); 462 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 463 464 return; 465 } 466
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